GB2560480B - Three-dimensional integration of neurosynaptic chips - Google Patents

Three-dimensional integration of neurosynaptic chips Download PDF

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Publication number
GB2560480B
GB2560480B GB1810430.7A GB201810430A GB2560480B GB 2560480 B GB2560480 B GB 2560480B GB 201810430 A GB201810430 A GB 201810430A GB 2560480 B GB2560480 B GB 2560480B
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United Kingdom
Prior art keywords
dimensional integration
neurosynaptic chips
neurosynaptic
chips
integration
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GB1810430.7A
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GB201810430D0 (en
GB2560480A (en
Inventor
Liu Fei
Cao Qing
Cheng Kangguo
Li Zhengwen
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/049—Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • General Health & Medical Sciences (AREA)
  • Data Mining & Analysis (AREA)
  • Evolutionary Computation (AREA)
  • Computational Linguistics (AREA)
  • Molecular Biology (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Artificial Intelligence (AREA)
  • Neurology (AREA)
  • Semiconductor Memories (AREA)
GB1810430.7A 2015-11-30 2016-11-22 Three-dimensional integration of neurosynaptic chips Active GB2560480B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/953,585 US10832127B2 (en) 2015-11-30 2015-11-30 Three-dimensional integration of neurosynaptic chips
PCT/IB2016/057027 WO2017093848A1 (en) 2015-11-30 2016-11-22 Three-dimensional integration of neurosynaptic chips

Publications (3)

Publication Number Publication Date
GB201810430D0 GB201810430D0 (en) 2018-08-08
GB2560480A GB2560480A (en) 2018-09-12
GB2560480B true GB2560480B (en) 2022-02-09

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ID=58777244

Family Applications (1)

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GB1810430.7A Active GB2560480B (en) 2015-11-30 2016-11-22 Three-dimensional integration of neurosynaptic chips

Country Status (6)

Country Link
US (1) US10832127B2 (en)
JP (1) JP6943847B2 (en)
CN (1) CN107851215B (en)
DE (1) DE112016003571B4 (en)
GB (1) GB2560480B (en)
WO (1) WO2017093848A1 (en)

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US11205116B2 (en) * 2016-12-09 2021-12-21 Fu-Chang Hsu Three-dimensional neural network array
US11609623B2 (en) 2017-09-01 2023-03-21 Qualcomm Incorporated Ultra-low power neuromorphic artificial intelligence computing accelerator
US11763139B2 (en) * 2018-01-19 2023-09-19 International Business Machines Corporation Neuromorphic chip for updating precise synaptic weight values
KR102112393B1 (en) * 2018-02-28 2020-05-18 부산대학교 산학협력단 Three-dimensional stacked synapse array-based neuromorphic system and method of operating and manufacturing the same
KR102589968B1 (en) * 2018-04-17 2023-10-16 삼성전자주식회사 Neuromorphic circuit having 3D stacked structure and Semiconductor device having the same
US11157213B2 (en) 2018-10-12 2021-10-26 Micron Technology, Inc. Parallel memory access and computation in memory devices
US10461076B1 (en) 2018-10-24 2019-10-29 Micron Technology, Inc. 3D stacked integrated circuits having functional blocks configured to accelerate artificial neural network (ANN) computation
CN110111234B (en) * 2019-04-11 2023-12-15 上海集成电路研发中心有限公司 Image processing system architecture based on neural network
US20200410319A1 (en) * 2019-06-26 2020-12-31 Micron Technology, Inc. Stacked artificial neural networks
JP7277682B2 (en) * 2019-07-03 2023-05-19 公立大学法人会津大学 Spiking Neural Network with 3D Network-on-Chip
KR20210050966A (en) 2019-10-29 2021-05-10 삼성전자주식회사 Stacked neuromorphic devices and neuromorphic computing devices
JP2021149981A (en) 2020-03-17 2021-09-27 キオクシア株式会社 Semiconductor storage device
RU2744440C1 (en) * 2020-09-23 2021-03-09 Федеральное государственное бюджетное учреждение науки Институт физики твердого тела Российской академии наук (ИФТТ РАН) Method of writing and reading information for permanent memory elements of neuromorphic systems
US20240038726A1 (en) * 2021-02-10 2024-02-01 Panasonic Intellectual Property Management Co., Ltd. Ai module

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US20090313195A1 (en) * 2008-06-17 2009-12-17 University Of Ulster Artificial neural network architecture
US20100241601A1 (en) * 2009-03-20 2010-09-23 Irvine Sensors Corporation Apparatus comprising artificial neuronal assembly
CN102270504A (en) * 2010-06-01 2011-12-07 三星电子株式会社 Stacked semiconductor memory device, memory system, and method of repairing defects of through silicon vias
US20120250443A1 (en) * 2011-03-31 2012-10-04 Ruchir Saraswat Energy Efficient Power Distribution for 3D INTEGRATED CIRCUIT Stack
US20140310490A1 (en) * 2011-12-29 2014-10-16 Pete D. Vogt Heterogeneous memory die stacking for energy efficient computing
CN104701309A (en) * 2015-03-24 2015-06-10 上海新储集成电路有限公司 Three-dimensional stacked nerve cell device and preparation method thereof

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US7398259B2 (en) * 2002-03-12 2008-07-08 Knowmtech, Llc Training of a physical neural network
JP4794218B2 (en) * 2004-06-25 2011-10-19 パナソニック株式会社 Slave device, master device and stacking device
WO2010117355A1 (en) 2009-04-06 2010-10-14 Hewlett-Packard Development Company, L.P. Three dimensional multilayer circuit
US8447714B2 (en) 2009-05-21 2013-05-21 International Business Machines Corporation System for electronic learning synapse with spike-timing dependent plasticity using phase change memory
US8492195B2 (en) 2010-08-23 2013-07-23 Crossbar, Inc. Method for forming stackable non-volatile resistive switching memory devices
US8253443B2 (en) 2010-10-26 2012-08-28 Hewlett-Packard Development Company, L.P. Interconnection architectures for multilayer crossbar circuits
US8510239B2 (en) 2010-10-29 2013-08-13 International Business Machines Corporation Compact cognitive synaptic computing circuits with crossbar arrays spatially in a staggered pattern
US8569861B2 (en) * 2010-12-22 2013-10-29 Analog Devices, Inc. Vertically integrated systems
FR2978271B1 (en) * 2011-07-21 2014-03-14 Commissariat Energie Atomique DEVICE AND METHOD FOR PROCESSING DATA
WO2013048501A1 (en) * 2011-09-30 2013-04-04 Intel Corporation Interlayer communications for 3d integrated circuit stack
US9214435B2 (en) * 2012-05-21 2015-12-15 Globalfoundries Inc. Via structure for three-dimensional circuit integration
US8990130B2 (en) 2012-11-21 2015-03-24 International Business Machines Corporation Consolidating multiple neurosynaptic cores into one memory

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090313195A1 (en) * 2008-06-17 2009-12-17 University Of Ulster Artificial neural network architecture
US20100241601A1 (en) * 2009-03-20 2010-09-23 Irvine Sensors Corporation Apparatus comprising artificial neuronal assembly
CN102270504A (en) * 2010-06-01 2011-12-07 三星电子株式会社 Stacked semiconductor memory device, memory system, and method of repairing defects of through silicon vias
US20120250443A1 (en) * 2011-03-31 2012-10-04 Ruchir Saraswat Energy Efficient Power Distribution for 3D INTEGRATED CIRCUIT Stack
US20140310490A1 (en) * 2011-12-29 2014-10-16 Pete D. Vogt Heterogeneous memory die stacking for energy efficient computing
CN104701309A (en) * 2015-03-24 2015-06-10 上海新储集成电路有限公司 Three-dimensional stacked nerve cell device and preparation method thereof

Also Published As

Publication number Publication date
GB201810430D0 (en) 2018-08-08
JP2019505065A (en) 2019-02-21
DE112016003571B4 (en) 2023-11-02
US20170154257A1 (en) 2017-06-01
WO2017093848A1 (en) 2017-06-08
CN107851215A (en) 2018-03-27
DE112016003571T5 (en) 2018-04-19
GB2560480A (en) 2018-09-12
US10832127B2 (en) 2020-11-10
JP6943847B2 (en) 2021-10-06
CN107851215B (en) 2021-08-03

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