GB2548357A

GB2548357A - Pixel driver circuit

Info

Publication number: GB2548357A
Application number: GB1604335.8A
Authority: GB
Inventors: Norval Shane; Jongman Jan; Craven Marc
Original assignee: FlexEnable Ltd
Current assignee: FlexEnable Ltd
Priority date: 2016-03-14
Filing date: 2016-03-14
Publication date: 2017-09-20
Also published as: GB201604335D0; WO2017158329A1

Abstract

Each layered organic TFT transistor 21 is adjacent pixel electrode 12b having an OLED light emitting element 14. A first light shield layer 31 is positioned between the OLED and the OTFT and also over the OTFT. The first light shield may comprise a light absorbing material that defines a bank structure for the OLED. A second light shield 27 below the OTFT prevents ambient light which is incident on the display emission surface 20 reaching the semiconductor channel. The second light shield is at least as close to the emission surface as the light emitting element.

Description

Pixel Driver Circuit

TECHNICAL FIELD

This invention relates to pixel driver circuits, and in particular to pixel driver circuits for organic light-emitting diode (OLED) displays.

BACKGROUND

Organic light-emitting diodes (OLED) are commonly used to provide displays in electronic display devices. Typically, OLEDs are driven by an active matrix backplane, i.e. a matrix or array of thin film transistors (TFT) or organic TFTs (OTFT). Each pixel of the OLED display is selectively addressed by an individual TFT of the backplane to change the state of the pixel.

Typically, amorphous silicon or polycrystalline silicon TFTs are used in the pixel circuit, but OLED pixels may also be driven by OTFTs where the channel is made from an organic semiconductor. In OTFTs the channel is made from an organic semiconductor. OTFTs are light sensitive and thus, they must be shielded from light that reaches the OTFT layer. US2006/0238115 describes an active matrix organic light emitting device and method of manufacturing the same. As shown in the various embodiments, the pixel circuit includes an organic thin film transistor (TFT) located on the organic light emitting diode (OLED) and overlapping the OLED. US2006/0238115 also describes a conventional active matrix organic light emitting device in which a TFT structure is included on one side of a substrate and an OLED structure is included adjacent to the TFT structure.

The present applicant has recognised the need to provide a pixel structure which protects against light exposure.

SUMMARY

According to a first aspect of the present invention, there is provided a display comprising a display medium comprising a plurality of light emitting elements and an emission surface through which the plurality of light emitting elements emit a display as a plurality of pixels, an active matrix backplane comprising a plurality of pixel circuits each associated with a pixel of the display medium, each pixel circuit comprising: a pixel electrode; and a layered transistor structure comprising at least one transistor which is associated with said pixel electrode and which comprises a drain electrode and a source electrode separated by a semiconductor channel; wherein each layered transistor structure is positioned to one side of its associated pixel electrode and each pixel electrode has a light emitting element thereon, the display further comprising a first light shield which is positioned between said light emitting element and said layered transistor structure to prevent light from said light emitting element reaching said semiconductor channel; and a second light shield within said layered transistor structure which prevents ambient light which is incident on said emission surface reaching said semiconductor channel; wherein said second light shield is at least as close to said emission surface as said light emitting element.

The following features apply to all aspects of the invention.

The emission surface is the surface from which light is emitted by the device. The layers between the emission surface and the light emitting surface must be transparent to allow the light to be emitted and thus, it is also possible for ambient light which is incident on the emission surface to pass through the transparent layers to the transistor. In a bottom emission device, light is typically emitted through a transparent substrate and thus the emission surface may be a surface of the transparent substrate. In a top emission device, light is typically emitted through a transparent common electrode and thus the emission surface may be a surface of the common electrode. The second light shield blocks such ambient light and may thus be termed an ambient light shield - the terms may be used interchangeably. It will be appreciated that the ambient light shield does not necessarily exclusively block ambient light but may also block light emitted from the light emitting element. Similarly, the first light shield may be termed an emitted light shield. However, this may also block ambient light as well as light emitted from the light emitting element.

In the present invention, each transistor stack, including the ambient light shield, is positioned to one side of the light emitting element, which may be located within a well or trench. If the light emitting element is positioned closer to the emission surface than the ambient light shield, there is a risk that light from the light emitting element will leak around the ambient light shield to the transistor. Accordingly, the light emitting element is at least as far from the emission surface as the ambient light shield. For example, in a top emission device, the light emitting element may be at the same distance from the common electrode as the ambient light shield. In a bottom emission device, the light emitting element is typically further from the substrate than the ambient light shield.

The at least one transistor may be an organic transistor, particularly a thin film transistor. In other words, the semiconductor channel may comprise an organic semiconductor material. The organic semiconductor material may be, for example, a solution processable conjugated polymeric or oligomeric material. Such organic materials are particularly sensitive to light and thus it is important to prevent light exposure to them. In relation to the semiconductor channel, light-sensitive means that one or more characteristics of the channel are changed upon exposure to excessive amounts of light. For example, in this context, the two principle effects of light exposure are a positive threshold voltage (V‘^) shift and an Increase in ‘off-current’ (Leakage current seen when the TFT is biased Off). More information on the effect of light exposure can be found for example, in “Light-Exposure Effects on Electrical Characteristics of 6,13-Bis(triisopropylsilylethynyl)Pentacene/CdTe Composite Thin-Film Transistors” by Park et al published in the Japanese Journal of Applied Physics, Vol 52, Number 5 or in “Photoleakage Currents in Organic Thin Film Transistors published in Applied Physics Letters, Vol. 88, 071106 (2006).

To give the light shielding properties, one or both light shields may be made from a reflective material or an opaque (light absorbing) material. For example, the emitted light shield may be made from a light absorbing material, e.g. a black resist, and the ambient light shield may be made from a reflective material, e.g. metal. An advantage of using a metal layer is that it is opaque at relatively thin layers, e.g. 200nm whereas for other materials, e.g. a resist, thicker layers perhaps greater than 4μm are required. However, a metal is a reflective material and the scattering of the light can cause a problem.

The optical density of an opaque (black) material is quantified by its absorbance A which is defined as:

where I is the intensity of the light at a specific wavelength λ, that has passed through a sample and lo is the intensity of light before it enters the sample. Thus, in effect, absorbance is a function of wavelength though it is often quoted as a single figure. For example, an absorbance of 3 will block 99.9% of light giving a maximum contrast ratio of 1000:1. In one example, the opaque materials preferably have an absorbance of greater than about 2 and preferably at least 3 at all wavelengths that impair the performance of the transistor, particularly wavelengths corresponding to the HOMO-LUMO bandgap and higher energies.

The transistor stack may comprise more than one transistor each comprising a source and drain electrode separated by a semiconductor channel. For example, there may be a first transistor which is a driving transistor and a second transistor which an addressing transistor, i.e. a transistor which transfers voltage from a data line to the gate electrode of the transistor which is driving the pixel electrode (i.e. the driving transistor). The driving transistor may then convert the data voltage to a corresponding current for the pixel electrode. The ambient light shield and/or the emitted light shield may block light for one or all of the transistors. Each light shield may be continuous or may be formed from several discrete parts to block light. Where there are several discrete parts, each part may be vertically aligned with, i.e. directly above or below, an associated semiconductor channel.

The ambient light shield and/or emitted light shield may be made from a conducting material, e.g. a metal. Such a conductive light shield may be connected to either the source or drain electrode. The conductive light shield may connect to the pixel electrode. In this way, one of the ambient and/or emitted light shields may form a shield connector between the pixel electrode and the drain electrode. Accordingly, there is no need to create a separate via to connect the two electrodes. This is an efficient method of both protecting the semiconductor channel and of providing the necessary connections. The shield connector may be formed on a side surface of the well.

The at least one transistor also comprises a gate electrode. Where the ambient light shield is made from a conducting material, the ambient light shield may act as the gate electrode. For example, in a bottom emission device having a bottom gate transistor, the gate electrode may be the ambient light shield. Similarly, in a top emission device having a top gate transistor, the gate electrode may be the ambient light shield. The transistor stack may comprise more than one transistor. In such an arrangement, the ambient light shield may act as the gate electrode for more than one transistor.

The pixel electrode is preferably laterally spaced from the transistor stack. By laterally spaced it is meant that the pixel electrode is to one side and not above or below the transistor electrodes. The the first light shield may be formed from a bank layer which separates the transistor structures from the light emitting elements. In this way, the light shield performs two functions and thus the number of overall layers is reduced. For example, the pixel electrode may form the base of the well or trench within which the light emitting element is situated. The well may have sloped sides to facilitate introduction of the light emitting element and subsequent overlay of a common electrode for the light emitting elements into the well. The emitted light shield may be the layer (i.e. bank layer) which extends over the whole of the sides of the well. Moreover, the emitted light shield may be extended across the transistor stack between the transistor stack and a common electrode for the light emitting element. The emitted light shield may thus form a cover for each transistor stack and this cover may also form part of the bank layer. For a top emission device, the portion of the cover between the transistor stack and the common electrode may act as the ambient light shield. Thus, the cover is formed by both the emitted light shield which covers the sides of the transistor stack and the ambient light shield which covers the upper surface of the transistor stack.

The display medium and/or active matrix backplane may be supported on a substrate which may be flexible preferably a flexible plastic substrate. The substrate may be formed of a flexible polymer such as PVC, PET (polyethyleneterephthalate) or PEN (polyethelenenaphthalene). Each component may be flexible such that a flexible display device, such as a flexible LED/OLED display panel, can be manufactured. The substrate may be formed of a transparent material, so that the display can be adapted to bottom emission, where light exits the device through the substrate (i.e. bottom of the display). In such an arrangement, the pixel electrode may also be formed from a transparent material, e.g. indium tin oxide (ITO).

The light emitting element may be a light-emitting diode (LED) or an organic LED. The display medium may thus comprise an array of light-emitting diodes (LED) or organic LEDs (one for each pixel). The display medium may be an optically switchable medium, e.g. each pixel within the display medium may be switched by the corresponding pixel electrode. Alternatively, in embodiments the pixel comprises other current-driven light-emitting materials. They may be more than one layer of OLED, e.g. a relatively thick layer and a relatively thin layer.

The display may be formed as a layered structure. The second light shield, the source electrodes and drain electrodes may be in the same layer. Alternatively, the pixel electrode and second light shield may be formed in the same layer with the source and drain electrodes in a different layer. In any arrangement, given that the light emitting element is in the adjacent layer to the pixel electrode, in this way, the second light shield must be at least as close to the emission surface as the light emitting element. Each layer may be flexible to create a fully flexible display device. Advantageously, a flexible OLED display device, such as electronic paper or a flexible display panel, can be manufactured.

The transistor stack may comprise a planarising layer on which the source and drain electrodes are formed. The planarising layer may be made from a material to assist in light blocking. For example, the planarising layer may be made from an opaque material or a black dielectric.

The transistor stack may comprise a capacitor layer to increase capacitance in the device. The capacitor plate is preferably vertically aligned with at least one of the gate electrode and the semiconductor channel. The capacitor plate may form a third light shield.

Each transistor stack may comprise a plurality of conductive layers separated by a plurality of insulating layers. The transistor stack may comprise at least a first and a second conducting layerseparated by an insulating layer. The first conducting layermay comprise said source and drain electrodes and the second conducting layermay comprise a gate electrode. The transistor stack may comprise a third conducting layercomprising said ambient light shield. Alternatively, as set out above said ambient light shield may be said gate electrode. The third conducting layermay be below said first and second conductive layers. The third conducting layermay be separated from said first conducting layerby an insulating layer which may be a planarising layer. The pixel electrode and ambient light shield may be formed in the same conductive layer. Alternatively, the pixel electrode and the source and drain electrodes may be formed in the same conducting layer. At least one of said conductive layers may be metallic. All of the conductive layers may be made from the same material. Alternatively, components within conducting layers may be made from different materials. For example, as described above, the pixel electrode may be transparent and thus non-metallic.

In the arrangements described above, the pixel circuit has a novel structure with the pixel electrode moved from the top of the layered structure to the bottom of the layered structure when compared with known devices.

Thus, according to another aspect of the invention, there is provided a method of manufacturing a pixel circuit on a substrate, the method comprising: forming a first conducting layer over said substrate wherein said first conducting layer comprises a pixel electrode of said pixel circuit; and forming a layered transistor structure adjacent said pixel electrode by forming a first light shield; forming a layer comprising a source and a drain electrode of each transistor associated with said pixel electrode; forming a semiconductor layer over said second conducting layer to provide a semiconductor channel between said drain and source electrode of said transistor wherein said semiconductor channel is aligned with said first light shield to reduce incident light on said semiconductor channel; forming a layer comprising a gate electrode of each transistor associated with said pixel electrode; and forming a second light shield on at least a side of said layered transistor structure adjacent said pixel electrode.

According to another aspect of the invention, there is provided a pixel circuit made according to the method described above.

By forming, it is meant that any known process can be used to create the layers. For example, a complete (or substantially complete) layer of material may be deposited and subsequently patterned, e.g. using lithography, or alternatively only the required regions in the layer may be deposited. Similarly, by forming each layer over another layer, it is meant that the layer may be formed directly on the other layer or on top of one or more additional layers which already exist on the other layer.

The steps of the above method do not need to be carried out in the order listed. When forming the layered transistor structure, material may be deposited on the pixel electrode. Any material in any layers, e.g. said first insulating layer, said second conducting layer and/or said semiconductor layer which is formed above said pixel electrode may be removed to create a well or trench in which the light emitting element sits. For example, each time a layer is added, any material which is deposited over the pixel electrode may be removed so that the pixel electrode forms the base of the well. This can be done as each layer is added or in a final step to remove all material. By contrast, in a typical arrangement, bank material is typically deposited to form a trench in which the light emitting material is located. By forming the trench through the layers which form the transistor stack, these layers effectively form the bank material for the light emitting element.

The features above for the method apply equally to the display and vice versa. For example, the method may comprise forming the semiconductor channel from a light sensitive material, e.g. an organic material. As explained above, the semiconductor channel is protected from light damage by the ambient light shield which primarily protects the channel from ambient light and by the emitted light shield which primarily protects the channel from light from a light emitting element in the well. The semiconductor channel is aligned with the ambient light shield, i.e. the semiconductor channel is directly above the ambient light shield. It will be appreciated that the ambient light shield needs to cover at least the same area as the semiconductor channel to block ambient light thereto. In this method, the ambient light shield is formed beneath other layers and thus the ambient light shield must be at least as close to an emission surface of a display in which the pixel circuit is incorporated as a light emitting element within the well.

The method may comprise forming a planarisation layer over said first light shield. Said planarising layer may be an insulating material and may be an opaque material to assist in light blocking as described in more detail above.

Forming said first conducting layer may comprise forming said ambient light shield whereby said first conducting layer comprises said ambient light shield and said pixel electrode. In this way the ambient light shield is conductive and may thus be used as a gate electrode or a shield connector as described in more detail above. In other words, the first light shield may have dual functionality which reduces the overall number of components in the device. Similarly, the method may comprise forming the second light shield as the bank layer which in use separates each layered transistor structure from its corresponding light emitting element. Thus, the second light shield has two functions.

Said method may comprise forming a layered transistor stack comprising a second transistor comprising a source and drain electrode. As explained in more detail above, there may be a plurality of transistors, including for example an addressing transistor and a driving transistor. The source and drain electrodes for each transistor may be formed in the same layer, e.g. in the same conducting layer.

Said method may further comprise forming a third conducting layer over said semiconductor layer, wherein said third conducting layer comprises a gate electrode for the or each transistor. Alternatively, a third conducting layer may be omitted by forming the gate electrode from the ambient light shield. The various conducting layer may be formed from the same or different materials as described above. Additional conducting layers may optionally be present. For example, the method may further comprise forming an additional conducting layer comprising a capacitor plate for the or each transistor. Alternatively, or additionally, the method may further comprise forming an additional conducting layer comprising a third light shield.

In US2006/0238115, the light emitting element is integrated within the pixel circuit and thus it is not possible to complete the pixel circuit without the light element. By contrast, in the present invention, it is possible to complete the entire pixel circuit before adding the light emitting element.

According to a further aspect of the invention, there is provided a method of manufacturing a flexible active matrix backplane comprising manufacturing a plurality of pixel driver circuits as recited above. The plurality of pixel circuits are preferably manufactured on a common substrate which is preferably flexible. One advantage of forming the complete array in this way is that the array can be tested before adding the light emissive material which may lead to higher yields. Thus, according to a further aspect of the invention, there is provided a method of manufacturing a display comprising manufacturing a flexible active matrix backplane as described above and subsequently depositing light emissive material into each well. A common electrode may be formed over each transistor stack and light emitting element.

As explained above, it is possible to produce a top emission or a bottom emission display. For example, the substrate and pixel electrode may be transparent to form a top emission display.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is diagrammatically illustrated, by way of example, in the accompanying drawings, in which:

Fig. 1 is a schematic cross-section of a pixel drive circuit according to a first arrangement;

Fig. 2 shows a schematic cross-section of a pixel drive circuit according to different arrangements;

Figs. 3a to 3e show the various steps in forming a pixel drive circuit according to the arrangement of Fig 2;

Figs. 4a to 4d are schematic cross-sections of a pixel drive circuit according to different arrangements;

Figs. 5a to 5e show the various steps in forming a pixel drive circuit according to the arrangement of Fig 4b;

Fig. 6 is a flowchart of the steps in manufacturing various arrangement of the pixel drive circuit.

DETAILED DESCRIPTION OF THE DRAWINGS

Figure 1 is a schematic drawing of a first arrangement of a pixel drive circuit for driving a pixel, e.g. in a display medium. The pixel drive circuit comprises a pixel electrode 12 for each pixel and at least one transistor within a transistor stack. The transistor and pixel electrode are laterally spaced from each other, i.e. they are arranged side-by-side on the substrate. The pixel electrode is connected to a light emitting element which forms the pixel and as shown in this arrangement comprises a first relatively thin layer 18 of organic light emitting diodes (OLEDs) without a cathode and a second relatively thick layer 16 of organic light emitting diodes (OLEDs) also without a cathode. The light emitting element sits in a trench above the pixel electrode 12. The trench for holding the light emitting element is formed as described in more detail below and is between two adjacent transistor stacks. Typically, there is an array of pixels and thus there will be a plurality of such transistor stacks; one for each pixel. However, for convenience, only a small portion of the array is depicted in detail.

Both the transistor stack and the pixel electrode 12 and its associated light emitting element are above a substrate 20a. The substrate may be flexible, e.g. a flexible plastic substrate. In this arrangement, the device is a top-emission device and thus the substrate and the pixel electrode need not be transparent and are preferably made from a material which does not transmit light to protect the transistor as described below. There is also a barrier layer 22 between the substrate and a dielectric layer 19. The barrier layer 22 helps to protect the transistor against the ingress of moisture via the substrate. The barrier layer 22 is optionally sandwiched between two bonding layers (not shown) to assist in securing all the layers together.

Each transistor comprises a source electrode 26 and a drain electrode 28 in a single conducting layer and a gate electrode 29 in a different conducting layer. In this arrangement, the transistor is a top gate transistor with the gate electrode formed in a layer above that of the source and drain electrodes. The drain electrode 28 is connected using known connections (not shown) to the pixel electrode 12 which in this arrangement is in the same conducting layer as the source and drain electrode. The two conducting layers are separated by the standard layer(s) used in the industry. These standard layers may be termed a separation layer because they separate the conducting layers. The standard layer(s) include a semiconducting layer together with an insulating layer such as the gate dielectric layer 21. The channel formed between the source and drain electrodes 26, 28 is preferably formed from an organic semiconducting material which is light sensitive. Accordingly, it is important to prevent light transmission from the light emitting element reaching the transistor, particularly the channel.

In this arrangement, there is a dielectric layer 31 which extends above the gate electrode 31 and forms the side walls of the trench in which the OLED layers are located. Thus, the dielectric layer 31 may be termed a bank layer, i.e. forms a partition (bank) between the light emitting element and the transistor. The dielectric layer 31 is preferably formed from a light absorbing material, e.g. a black material. Light generated by the light emitting element (OLED layers) is prevented from reaching the transistor by this dielectric layer which thus forms a generated light shield (which may also be termed a first light shield). The generated light shield covers the side walls of the trench in which the light emitting element is located, i.e. the dielectric layer extends to one side of the gate dielectric layer 21. The trench is thus defined by the generated light shield and the pixel electrode 12 which forms the base of the trench. Furthermore, in this illustrated embodiment, the light shield extends to form a cover section above the transistor stack. However, this cover section may be omitted if the light shielding on the trench walls is sufficient to prevent light from the light emitting element reaching the channel of the transistor.

The surface from which light is emitted by the device may be termed an emission surface. Given that the devices are emitting light through transparent layers to the emission surface, it is also possible for ambient light which is incident on the emission surface to pass through the transparent layers to the transistor. It is important to block such ambient light which in a top emission device shown in Figure 1 is incident on an upper surface of the device. In this arrangement, shielding or screening can be provided by upper shield 32 which is generally vertically aligned with (i.e. above), the gate electrode 29. Such an upper shield 32 will assist in preventing ambient light which is incident on the upper surface of the device from reaching the light sensitive material between the source and drain electrodes. The screening provided by the shield 32 can be enhanced by the use of a passivation layer 39. The passivation layer 39 preferably is a shielding outer layer and may help in preventing light reaching the semiconductor channel but may also provide other shielding benefits such as prevent corrosion.

There is a possibility that light will travel through the substrate, even though it is not transparent and thus ambient light needs to be blocked from under the device. In Figure 1, there is a dielectric layer 19 above the substrate and a lower light shield 27 is formed on the dielectric layer 19. The lower light shield 27 is generally vertically aligned with (i.e. below) the gate electrode and/or the upper shield 32 and thus covers the semiconductor channel so that the semiconductor channel is shielded from below. There is a planarisation layer 25 between the source and drain electrode and the ambient light shield.

Figure 2 shows a variation of the pixel drive circuit shown in Figure 1 in which there are two transistors associated with each pixel. A first transistor is a driving transistor which comprises a source electrode 26a and a drain electrode 28a which is connected to the pixel electrode 12a. The second transistor is a switching transistor which comprises a source electrode 26 and a drain electrode 28. As in Figure 1, the pixel electrode 12a is on the same conductor layer as the pairs of source and drain electrodes. However, in Figure 1, the pixel electrode formed the base of the trench for the light emitting element whereas in this arrangement, the pixel electrode 12a extends beyond the base of the trench under the bank layer 31. Another difference between the two embodiments, is the presence of a capacitor 35 in the arrangement of Figure 2. The variation in Figure 2 is also a bottom emission device and thus the substrate is transparent. For example, the substrate may be formed of a flexible polymer such as PVC, PET (polyethyleneterephthalate) or PEN (polyethelenenaphthalene).

The same elements of the pixel electrode circuit have the same numbers. As in Figure 1, in Figure 2, the various layers are formed above the substrate 20. In this arrangement, the shield 27 is formed on the substrate 20. The shield 27 has a generally similar shape to, and is aligned with (i.e. under) that of the capacitor 35 and thus covers the semiconductor channels between both pairs of source and drain electrodes. A planarisation layer 25a is formed over the shield 27 and exposed surfaces of the substrate. In this bottom emission arrangement, the planarization layer 25a is transparent as is the pixel electrode 12a. The first conducting layer comprising the source and drain electrodes 26, 26a, 28, 28a and the pixel electrode 12a are formed on the planarisation layer. A separating layer comprising a semi-conducting layer and a second insulating layer (gate dielectric layer 21) are above the first conducting layer and the exposed surfaces of the planarization layer. A second conducting layer having two gate electrodes 29, 29a is above the gate dielectric layer 21. A first gate electrode 29 is aligned above the source and drain electrodes 26, 28 of the switching transistor. A second gate electrode 29a is aligned above the source and drain electrodes 26a, 28a of the driving transistor. The second gate electrode 29a is connected by a via through the gate dielectric layer to the drain electrode 28 of the switching transistor.

Another separating layer, this time a capacitance dielectric layer 33 covers the drain electrodes and exposed surface of the gate dielectric layer 31. The third conducting layer comprises a capacitor plate 35 which is vertically aligned with (i.e. above) the source, drain and gate electrodes of both transistors. A further insulating layer 37 covers the capacitor plate 35. The light emitting element 14 is located within a trench between transistor stacks and a black dielectric layer is formed over each transistor stack and into the trench to provide a light shield. Thus as in Figure 1, this black layer prevents emitted light from each light emitting element being transmitted laterally, i.e. sidewards, into the transistor stack. Similarly, as in Figure 1, the shield 27 protects the transistor from ambient light which is incident on the transparent substrate 20.

Figures 3a to 3e illustrate the method of forming a pixel drive circuit according to Figure 2. The techniques used for forming and patterning the various layers which are described in detail below are equally applicable to all arrangements. As shown in Figure 3a, a shield 27 is formed on a substrate (not shown). The shield may be formed from a metal or an opaque dielectric (e.g. black resist (photoresist)). The shield may be formed using any suitable method and may be patterned, e.g. using photolith techniques. The shield acts as a light barrier and thus is formed from a material which does not transmit light. The shield is generally square with a rectangular protrusion from one edge. A planarisation layer may then be added above the shield. The planarisation layer is formed from a suitable material using any standard technique.

As shown in Figure 3b, the pixel electrode 12a together with the source electrodes 26, 26a and drain electrodes 28, 28a are formed on the planarisation layer. The pixel electrode 12a is generally rectangular with a relative small strip which extends above the shield 27. Each source electrode 26, 26a is an elongate rectangle and each drain electrode 28, 28a is a generally shorter rectangle. The connection 30 between the pixel electrode 12a and the drain electrode 28a is also formed. The electrodes and connection could be formed in a single stage or in multiple stages, e.g. pixel electrodes can be formed at a different stage to source and drain electrodes. The pixel electrode, source electrodes and drain electrodes may be formed by using any known techniques. For example, for a bottom emission device, the pixel electrode may be formed by printing a layer of suitable transparent material such as indium tin oxide (ITO) on the barrier layer and then the layer is patterned (e.g. ablated) to form the required electrodes. The source and drain electrodes may be formed using any standard techniques, e.g. metal deposition followed by lithographic patterning techniques or direct-write printing techniques. (Precise details of the lithographic patterning and deposition techniques used in the fabrication process are not provided here but are well known in the art.)

Once the various electrodes shown in Figure 3b are present, the next step is to add a semi-conducting layer above the conducting layer. The semi-conducting layer fills the channel between each pair of source and drain electrodes. The semi-conducting layer may be formed from any suitable material, e.g. organic semi-conductor, using any known techniques. When an organic semi-conductor is used, the resulting transistor is an organic thin film transistor (OTFT). OTFTs are light sensitive and thus, they must be shielded from light emitted by the light emitting element. As explained above, this is achieved by using a shield layer on the sides of the trench above the pixel electrode. A gate dielectric layer is then formed on the semi-conducting layer to cover the source and drain electrodes, the pixel electrode and any exposed areas of the semi conducting layer. The gate dielectric layer may then be patterned, again using standard techniques such as reactive ion etching (RIE). RIE uses a chemically reactive plasma to remove material from the structure. The source and drain electrodes and pixel electrode prevent the RIE process from etching through further layers, i.e. they serve as an ‘etch stopper’. The patterning creates a via to each drain electrode for the switching transistor and also removes the material above the pixel electrode in the region of the OLED.

Figure 3c shows that the next step is to add another conducting layer, e.g. metal, to form the gate electrodes 29, 29a. The first gate electrode 29 is generally L-shaped with a relatively short rectangular portion which covers part of the source electrode 26 and the drain electrode 28 for the associated switching transistor and a relative long rectangular portion which extends alongside the pixel electrode. The second gate electrode 29a has a first generally rectangular portion which covers part of the source electrode 26a and the whole of the drain electrode 28s for the associated driving transistor. The second gate electrode 29a has a second thinner rectangular portion which protrudes from the first generally rectangular portion and extends over the via to the drain electrode 28 of the switching transistor. Each conducting layer may be formed from the same conducting metal/polymer as the first other conducting layers or from a different conductive material. The conducting layer is added by standard techniques, e.g. by deposition followed by patterning or printing using masks. The conducting layer fills the vias to create connections to each of the drain electrodes from the respective gate electrodes. A capacitor dielectric layer is then formed to cover the gate electrodes.

As shown in Figure 3d, the next step is to add another conducting layer, e.g. metal to form the capacitor 35. The capacitor 35 has a similar sized surface area to that of the shield. The capacitor also helps to prevent light transmission to the light sensitive material in the channel.

The stage shown in Figure 3e is to add a bank layer 31. This is deposited and patterned using standard techniques. It is common in OLED displays to provide a bank layer 31 to partition each light-emitting element by banks/walls formed from insulating material e.g. a dielectric material. Consequently, the bank layer 31 is patterned to provide distinct and partitioned OLED areas and in this arrangement, the patterning ensures that the bank layer 31 continues the trench over the pixel electrode 12a. Thus, the sloped edges of the bank layer trench match the slope of the edges of the other layers through which the trench extends. The final stages (not shown) are to add the light emitting element for each pixel electrode into the trench. The light emitting elements may be organic light emitting diodes (OLED). As in Figure 1, more than one layer of OLED material may be used above the pixel electrode. A common electrode (as shown in Figure 4b) is then formed as a continuous layer over the top of the stack to provide the cathode for the pixel shown (and for all other pixels).

Thus, the pixel electrode circuit comprises a substrate onto which various layers are formed. The layers include a first conducting layer having source and drain electrodes 26, 26, 28, 28a and a pixel electrode 12a; a first separating layer comprising a semiconducting layer and a first insulating layer (or gate dielectric layer); a second conducting layer comprising gate electrodes; a second separating layer comprising a capacitor dielectric layer 33; and a third conducting layer having a capacitor 35. Additional layers such as a shield 27 and a bank layer 31 may also be included. In this arrangement, there are separate pairs of source and drain electrodes; one for each of a switch transistor and a drive transistor. The drive transistor is operable to provide a drive current for said pixel electrode and the switch transistor is operable to selectively address said pixel electrode. Both transistors are laterally spaced, e.g. arranged to one side, of the pixel electrode and its associated light emissive material. However, as set out above, the present invention is directed to providing appropriate shielding to prevent light transmission to the light sensitive material in the channel and can be used with any compatible circuitry. Accordingly, there may be more or fewer transistors in each stack. A possible disadvantage of the arrangements shown in Figures 1 and 2 is that emitting light from the light emitting element may be transmitted through the planarisation layer to the shield and then reflected back into the transistor. This problem may be solved as shown in Figures 4a to 4d by moving the source and drain electrodes to a layer which is above that of the pixel electrode. In this way, the shield 27 is then on the same layer as the pixel electrode and cannot reflect emitted light into the sensitive semiconductor channel.

Figure 4a is a schematic drawing of one such arrangement in which the lower shield 27 is on the same layer as the pixel electrode. Figure 4a shows a top emission device and comprises a plurality of layers formed on a substrate 20a. This substrate 20a may be non-transparent and flexible as described above. As in Figure 1, a bonding layer 41 is formed on the substrate 20a to bond the substrate to the transistor stack which is covered by the bank layer 31 and to bond the substrate to the pixel electrode 12.

Two lower shields 27a, 27b are formed on the bonding layer. A first lower shield 27a is adjacent to and connected to the pixel electrode. The second lower shield 27b is formed in the same layer but is laterally spaced from the first lower shield 27a. As in previous arrangements, a first separating layer in the form of a planarization layer 25 is above the first and second shields.

The first conducting layer comprising the source and drain electrodes 26, 28 is on the planarization layer 25. In this Figure, both the source and drain electrodes are schematically shown as connected by vias 30a to the first lower shield 27a. In this way, the drain electrode 28 is electrically connected to the pixel electrode 12 so that the transistor can drive the pixel. It will be appreciated that the connections are merely schematic and the various conductive components are not shorted together. As in the other arrangements, a second separating layer comprising a semiconductor layer and a gate dielectric layer 21 is above the first conducting layer. The first lower shield 27a is arranged vertically below the channel between the source and drain electrodes to block light from the light emitting element passing through the substrate 20a to the semiconductor channel.

The second conducting layer which comprises the gate electrode 29 is formed above the gate dielectric layer 21. The gate electrode 29 is connected using connections 30b to the second shield 27b. These connections 30b comprise a via through the gate dielectric layer to a connection 30b in the first connecting layer and through another via 30b to the second shield 27b. As with the connections for the source and drain electrodes, these connections are merely schematically represented in this Figure.

This is a top emission device and thus the bank layer 31 is formed from a black layer to minimise the transmission of any ambient light which is incident on the device. Such incident ambient light may pass through the common electrode (not shown) to the transistor. In such a top-emission device, the common electrode would be transparent, e.g. formed from ITO or other transparent conducting material and neither the substrate nor the pixel electrode need be transparent. The gate electrode is above the semi conductive channel and may thus form the ambient light shield in such a top-gate top emission device. However, as in the arrangement of Figure 1, the light blocking can be further enhanced by the use of an upper shield 32 which is separated from the gate electrode by a dielectric layer 23. The light blocking can be further enhanced by the use of a passivation layer 39 as explained above. The upper shield 32 is conductive and as shown is connected through to the second lower shield 27b using a via 30b which connects to the connections 30b in the second conducting layer which connect to the gate electrode. Again, these connections are schematically shown and the various components are not shorted together.

The bank layer defines a sloping side wall for the trench in which the light emitting element is located. As in Figure 1, this light emitting element comprises a first relatively thick layer 16 of OLEDs and a second relatively thin layer 18 of OLEDs. The bank layer 31 prevents lateral light transmission from the OLEDs into the transistor stack.

Figure 4b is a schematic drawing of a bottom emission arrangement in which the shield and pixel electrode are on the same level. As in previous arrangements, the pixel drive circuit comprises a pixel electrode 12 for each pixel and at least one transistor 10 within a transistor stack. A common electrode 15 is formed over the tops of each transistor stack. The transistor 10 and pixel electrode are laterally spaced from each other, i.e. they are arranged side-by-side on the substrate. The at least one transistor 10 is connected to said pixel electrode and said pixel electrode is connected to a light emitting element 14 which forms the pixel. The light emitting element 14 may be any suitable element but in this arrangement comprises an organic light emitting diode (OLED). The light emitting element sits in a trench above the pixel electrode 12. As for Figure 2, for convenience, only a small portion of the array, i.e. two transistor stacks and light emitting elements are depicted in detail. The components in common have the same reference number.

Both the transistor stack and the pixel electrode 12 and its associated light emitting element 14 are on a substrate 20. The substrate may be flexible, e.g. a flexible plastic substrate. The substrate may be formed of a flexible polymer such as PVC, PET (polyethyleneterephthalate) or PEN (polyethelenenaphthalene). In this arrangement. the device is a bottom-emission device and thus the substrate and the pixel electrode are transparent to allow light generated by the light emitting element in response to being driven by the associated transistor and pixel electrode to pass through. The common electrode 15 is preferably reflective and may be made from metal.

There is also a barrier layer 22 between the substrate and the transistor stack and the pixel electrode. The barrier layer 22 helps to protect the transistor against the ingress of moisture via the substrate. The barrier layer 22 is optionally sandwiched between two bonding layers (not shown) to assist in securing all the layers together.

Each transistor 10 comprises a source electrode 26 and a drain electrode 28 in a single conducting layer and a gate electrode 29 in a different conducting layer. The drain electrode 28 is connected to the pixel electrode 12 which in this arrangement is in a separate conducting layer to the source, drain and gate electrodes. The various conducting layers are separated by the standard layer(s) used in the industry. The standard layer(s) include a semiconducting layer together with an insulating layer such as the gate dielectric layer 23. In the illustrated arrangement, there is also a dielectric layer 21 between the gate electrode and the common electrode and a planarisation layer 25 between the source and drain electrode and substrate. The channel formed between the source and drain electrodes 26, 28 is preferably formed from an organic semiconducting material which is light sensitive. Accordingly, as explained above, it is important to prevent light transmission from the light emitting element reaching the transistor, particularly the channel.

Light generated by the light emitting element is prevented from reaching the transistor by a generated light shield 31 (which may also be termed a first light shield). The generated light shield 31 is preferably formed from a light absorbing material. The generated light shield 31 covers the side walls of the trench in which the light emitting element is located and thus the trench is defined by the generated light shield 31 and the pixel electrode 12 which forms the base of the trench. Thus, the generated light shield 31 acts at least in part as a bank layer, i.e. forms a partition (bank) between the light emitting element and the transistor. Furthermore, in this illustrated embodiment, the light shield extends between the common electrode and the upper layer of the transistor stack and has a cover section above the transistor stack. However, this cover section may be omitted if the light shielding on the trench walls is sufficient to prevent light from the light emitting element reaching the channel of the transistor.

The arrangement shown in Figure 4b is a top-gate transistor. In a bottom emission device with a top gate transistor, ambient light on the transistor is blocked by an ambient light shield 27 which is located in the same conducting layer as the pixel electrode 12. The ambient light shield 27 is formed from a reflective (and/or opaque) material which reflects (and/or blocks) ambient light incident on the device. The ambient light shield may be formed of electrically conductive material such as metal. In Figure 2a, the shield protects a single transistor but if there are more transistors in the stack, the shield may form protect all the transistors, either is in a continuous layer or in discrete portions which are aligned with at least the semiconductor channel of each transistor.

The ambient light shield blocks ambient light which passes through the transparent substrate of the device. If the light emitting element is positioned in a layer which is closer to the substrate than the ambient light shield 27, light from the light emitting element may leak around the ambient light shield to the light sensitive portions of the transistor. Accordingly, the light emitting element needs to be positioned at least as far from the substrate as the ambient light shield 27, although as explained above, if the light emitting element is too far above the light shield, there is a risk of reflection back into the transistor.

Figure 4c is a variation of Figure 4b in which all the common elements have the same reference number. The main change is to replace the top gate transistor with a bottom gate transistor. In such an arrangement the shield 27c forms the gate electrode and thus one of the separate conducting layers is omitted. Again, there may be more than one transistor in the stack and the shield 27c may form the gate electrode for each transistor.

In both arrangements, the protection for the transistor stack may be further enhanced by using an opaque planarisation layer 25 between the shield and the source/drain conducting layer. For this arrangement and any of the other arrangements, any suitable material may be used for the planarisation layer and a cross-linkable polymer dielectric is one example. It will also be appreciated that the transistor stack may comprise additional layers, e.g. conductive layers. Such additional layers may be used to increase or improve the capacitive coupling to one or more elements within the stack.

Thus, the pixel electrode circuit comprises a substrate onto which various layers are formed. In the arrangements shown in Figures 4a and 4b, the layers include a first conducting layer having a shield 27 and a pixel electrode 12; a first separating layer (or planarisation layer); a second conducting layer comprising a source and drain electrode 26, 28; a second separating layer comprising a semi-conducting layer and a second insulating layer (or gate dielectric layer); and a third conducting layer having a gate electrode 29. In the arrangement shown in Figure 4a, there is a fourth conducting layer comprising a upper shield separated from the third conducting layer by a separating layer formed from a dielectric layer. In the arrangement shown in Figure 4c, the third conducting layer is omitted and the shield 27c forms the gate electrode. Additional layers such as a barrier layer 22 and further dielectric layers may also be included. In contrast to the arrangement of Figure 1, the pixel electrode 12 is below the source and drain electrodes. Furthermore, the light emitting element is located within a trench between transistor stacks and a black layer is formed over each transistor stack and into the trench to provide a light shield.

Figure 4d shows a variation of the pixel drive circuit shown in Figure 4a in which there are two transistors associated with each pixel. A first transistor is a driving transistor which comprises a source electrode 26a and a drain electrode 28a which is connected to the pixel electrode 12a. The second transistor is a switching transistor which comprises a source electrode 26 and a drain electrode 28. As in Figures 4a to 4c, the pixel electrode 12b is on the same conductor layer as the shield 27. However, in Figures 4a to 4c, the pixel electrode formed the base of the trench for the light emitting element whereas in this arrangement, the pixel electrode 12c extends beyond the base of the trench under the bank layer 31 to connect to the shield 27. Another difference is the presence of a capacitor 35 in the arrangement of Figure 4d. As in Figures 4b and 4c, the variation in Figure 4d is also a bottom emission device and thus the substrate is transparent.

The same elements of the pixel electrode circuit have the same numbers. As in Figures 4a to 4c, in Figure 4d, the various layers are formed above the substrate 20. In this arrangement, the shield 27 is formed on the substrate 20. The shield 27 has a generally similar shape to, and is aligned with (i.e. under) that of the capacitor 35 and thus covers the semiconductor channels between both pairs of source and drain electrodes. A planarisation layer 25a is formed over the shield 27 and exposed surfaces of the pixel electrode 12b. In this bottom emission arrangement, the planarization layer 25a is transparent as is the pixel electrode 12b. The second conducting layer comprising the source and drain electrodes 26, 26a, 28, 28a is formed on the planarisation layer. A separating layer comprising a semi-conducting layer and a second insulating layer (gate dielectric layer 21) are above the second conducting layer and the exposed surfaces of the planarization layer. A third conducting layer having two gate electrodes 29, 29a is above the gate dielectric layer 21. A first gate electrode 29 is aligned above the source and drain electrodes 26, 28 of the switching transistor. A second gate electrode 29a is aligned above the source and drain electrodes 26a, 28a of the driving transistor. The second gate electrode 29a is connected by a via through the gate dielectric layer to the drain electrode 28 of the switching transistor.

Figures 5a to 5e illustrate the method of forming a pixel drive circuit according to Figure 4d. The techniques used for forming and patterning the various layers which are described in detail below are equally applicable to all arrangements. As shown in Figure 5a, a shield 27 and pixel electrode 12b is formed on a substrate (not shown). The shield acts as a light barrier and thus is formed from a material which does not transmit light. The shield is generally square with a rectangular protrusion from one edge. Similarly, the pixel electrode is generally rectangular with a rectangular protrusion adjacent the rectangular protrusion of the shield. A planarisation layer may then be added above the shield. The planarisation layer is formed from a suitable material using any standard technique.

As shown in Figure 5b, the source electrodes 26, 26a and drain electrodes 28, 28a are formed on the planarisation layer. Each source electrode 26, 26a is an elongate rectangle and each drain electrode 28, 28a is a generally shorter rectangle. The connection 30 between the pixel electrode 12a and the drain electrode 28a is also formed. The electrodes and connection could be formed in a single stage or in multiple stages. The source electrodes 26, 26a and drain electrodes 28, 28a may be formed by using any known techniques.

Once the various electrodes shown in Figure 5b are present, the next step is to add a semi-conducting layer above the conducting layer. The semi-conducting layer fills the channel between each pair of source and drain electrodes. As described above, when an organic semi-conductor is used, the resulting transistor is an organic thin film transistor (OTFT). A gate dielectric layer is then formed on the semi-conducting layer to cover the source and drain electrodes, the pixel electrode and any exposed areas of the semi conducting layer. The gate dielectric layer may then be patterned, again using standard techniques such as reactive ion etching (RIE).

Figure 5c shows that the next step is to add another conducting layer, e.g. metal, to form the gate electrodes 29, 29a. These gate electrodes 29, 29a are formed in a similar manner to, and have a similar shape, to those shown in Figure 3c. Thus, the first gate electrode 29 is generally L-shaped with a relatively short rectangular portion which covers part of the source electrode 26 and the drain electrode 28 for the associated switching transistor and a relative long rectangular portion which extends alongside the pixel electrode. The second gate electrode 29a has a first generally rectangular portion which covers part of the source electrode 26a and the whole of the drain electrode 28a for the associated driving transistor. The second gate electrode 29a has a second thinner rectangular portion which protrudes from the first generally rectangular portion and extends over the via to the drain electrode 28 of the switching transistor. A capacitor dielectric layer is then formed to cover the gate electrodes.

As shown in Figure 5d, the next step is to add another conducting layer, e.g. metal to form the capacitor 35. The capacitor 35 has a similar sized surface area to that of the shield. The capacitor also helps to prevent light transmission to the light sensitive material in the channel.

The stage shown in Figure 5e is to add a light blocking bank layer 31. This is deposited and patterned using standard techniques. The final stages (not shown) are to add the light emitting element for each pixel electrode into the trench. A common electrode (as shown in Figure 4b) is then formed as a continuous layer over the top of the stack to provide the cathode for the pixel shown (and for all other pixels).

Figure 6 shows the steps in the formation of the various arrangements. The first step SI00 is to provide a substrate which may be flexible and/or transparent as otherwise described. The various layers are then built on the substrate and all layers may be flexible to provide an overall flexible device. The substrate may be transparent for a bottom emission device or may be non-transparent and light blocking for a top emission device. In an optional next step, a shield may be deposited or otherwise formed using standard techniques above the substrate (SI02). The shield may be formed direct on the substrate as in Figure 2 or there may be other layers between the shield and the substrate as in Figure 1. The planarisation layer is then formed (S104). The planarisation layer covers the whole of the shield but the pixel electrode is typically not covered except in the arrangements shown in Figure 2. Thus, the thickness of the planarisation layer at least partially defines a trench (or well) into which the light emitting element is placed over the pixel electrode. The planarisation layer may be deposited and then patterned or deposited in only the required areas. The planarisation layer is an insulating layer.

Regardless of whether or not the first two optional steps have been carried out, the first conducting layer is then formed (SI 04). The first conducting layer may be formed from a conducting material such as an inorganic metal, for example, gold, copper or silver, or from a conducting polymer such as PEDOT. In the arrangements of Figures 1 and 2, the first conducting layer comprises the pixel electrode and the source and drain electrodes. In the arrangements of Figures 4a to 4d, the first conducting layer comprises the pixel electrode and the shield which may be made from the same conducting material or different conducting materials. Two different materials are required in a bottom emission device because the pixel electrode needs to be transparent but the shield needs to be reflective. If two different materials are used, the formation of the first conducting layer may take more than one step. The conducting layer may be deposited and then patterned or deposited in only the required areas. A first separating layer is then formed at step S106. The separating layer is an insulation layer separating two conducting layers. If the planarization layer has not already been formed, the separating layer is a planarization layer as described in Step S104. Otherwise, the first separating layer comprises a semi-conducting layer which is formed using standard techniques so that a semiconductor channel is formed between the source and drain electrodes. A second insulating layer (gate dielectric) may also be formed as part of the first separating layer. A second conducting layer is then formed over the first separating layer (S110). The second conducting layer may be formed from the same conducting metal/polymer material or a different material to the first conducting layer. For example, in the arrangements of Figures 1 and 2, the second conducting layer comprises the gate electrodes for each transistor. Whereas, in the arrangements of Figures 4a to 4d, the second conducting layer comprises the source and drain electrodes of the transistor which drives the pixel electrode. A second separating layer is then formed (S112). For example, in the arrangements of Figures 1 and 2, the second separating layer is a dielectric layer which may be black to assist in light screening for the semiconductor channel and/or may be a capacitor dielectric layer. Whereas, in the arrangements of Figures 4a to 4d, the second separating layer comprises a semi-conducting layer which is formed using standard techniques so that a semiconductor channel is formed between the source and drain electrodes. A second insulating layer (gate dielectric) may also be formed as part of the first separating layer.

The optional third conducting layer is then formed (S114). The third conducting layer may be formed from the same conducting metal/polymer material or a different material to the first and second conducting layers. For example, in the arrangements of Figures 1 and 2, the third conducting layer is either a shield to assist in light blocking and/or a capacitor. Whereas, in the arrangements of Figures 4a, 4b and 4d, the third conducting layer comprises the gate electrode of each transistor. In Figure 4c, an example of an arrangement without a third conducting layer is shown.

Additional conducting and dielectric layers may also be formed over the conducting layer. For example, as shown in Figure 4d, an optional third separating layer which is a capacitor dielectric layer may be formed at Step S116 and an optional fourth conducting layer comprising a capacitor may be formed at Step S118. Alternatively, as shown in Figure 4a, an optional third separating layer which is a black dielectric layer may be formed at Step S116 to assist in light blocking and an optional fourth conducting layer comprising a upper shield may be formed at Step S118.

Finally, in all the arrangements, a covering bank layer is then formed over the transistor stack (S120). The light emitting element is added into the trench above the pixel electrode (S122).

It will be appreciated that at various steps in the process of forming the arrangements described above, the material for the next layer is deposited over the whole surface of the existing structure. However, the skilled person would understand that alternative techniques may be employed to deposit the material in the required areas only, such as by a direct-write printing process, for example, inkjet printing. In this case, patterning the material may not be required.

In the arrangements described above, the transistors may be solution-based thin film transistors (TFTs) preferably patterned by techniques such as direct-write printing, laser ablation or photolithography. Examples of such transistors can be found in the applicant's earlier patent applications, for example WO 01/47045, WO 2004/070466, WO 01/47043, WO 2006/059162, WO 2006/056808, WO 2006/061658, WO 2006/106365 and W02007/029028, all hereby incorporated by reference in their entirety. Thus, in embodiments, the TFTs comprise an organic semiconductor material, for example a solution processable conjugated polymeric or oligomeric material, and in embodiments the pixel structure is adapted to solution deposition, for example comprising solution-processed polymers and vacuum-deposited metals.

No doubt many other effective alternatives will occur to the skilled person. It will be understood that the invention is not limited to the described embodiments and encompasses modifications apparent to those skilled in the art lying within the spirit and scope of the claims appended hereto.

Claims

CLAIMS:

1. A display comprising a display medium comprising a plurality of light emitting elements and an emission surface through which the plurality of light emitting elements emit a display as a plurality of pixels, an active matrix backplane comprising a plurality of pixel circuits each associated with a pixel of the display medium, each pixel circuit comprising: a pixel electrode; and a layered transistor structure comprising at least one transistor which is associated with said pixel electrode and which comprises a drain electrode and a source electrode separated by a semiconductor channel; wherein each layered transistor structure is positioned to one side of its associated pixel electrode and each pixel electrode has a light emitting element thereon, the display further comprising a first light shield which is positioned between said light emitting element and said layered transistor structure to prevent light from said light emitting element reaching said semiconductor channel; and a second light shield within said layered transistor structure which prevents ambient light which is incident on said emission surface reaching said semiconductor channel; wherein said second light shield is at least as close to said emission surface as said light emitting element.

2. The display of claim 1, wherein the semiconductor channel comprises an organic semiconductor material.

3. The display of claim 1 or claim 2, wherein the second light shield, the source electrodes and drain electrodes are in the same layer.

4. The display of claim 1 or claim 2, wherein the second light shield and the pixel electrodes are in the same layer.

5. The display of any one of claims 1 to 4, wherein the second light shield is formed from a conducting material, e.g. metal.

6. The display of claim 5, wherein the second light shield forms a gate electrode of the at least one transistor.

7. The display of any one of claims 1 to 6, wherein the first light shield comprises a light absorbing material.

8. The display of any one of claims 1 to 7, wherein the first light shield is formed from a bank layer which separates the transistor structures from the light emitting elements.

9. The display of any one of claims 1 to 8, wherein the first light shield is formed from a dielectric material.

10. The display of any one of claims 1 to 9, wherein the first light shield is angled relative to the pixel electrode.

11. The display of any one of claims 1 to 10, wherein the first light shield forms a cover over each transistor stack.

12. The display of any one of claims 1 to 11, wherein the transistor stack comprises a plurality of transistors each having a source and drain electrode separated by a semiconducting channel and the first and second light shield reduce light incident on each of the plurality of transistors within each stack.

13. The display of any one of claims 1 to 12, comprising a planarising layer on which the source and drain electrodes are formed.

14. The display of claim 13, wherein the planarising layer is opaque.

15. The display of any one of claims 1 to 14, comprising a capacitor layer.

16. A method of manufacturing a pixel circuit on a substrate, the method comprising: forming a first conducting layer over said substrate wherein said first conducting layer comprises a pixel electrode of said pixel circuit; and forming a layered transistor structure adjacent said pixel electrode by forming a first light shield; forming a layer comprising a source and a drain electrode of each transistor associated with said pixel electrode; forming a semiconductor layer over said second conducting layer to provide a semiconductor channel between said drain and source electrode of said transistor wherein said semiconductor channel is aligned with said first light shield to reduce incident light on said semiconductor channel; forming a layer comprising a gate electrode of each transistor associated with said pixel electrode; and forming a second light shield on at least a side of said layered transistor structure adjacent said pixel electrode.

16. The method of claim 16, wherein forming said first conducting layer comprises forming said first light shield whereby said first conducting layer comprises said first light shield and said pixel electrode.

17. The method of claim 15 or claim 16, further comprising forming a planarisation layer over said first light shield.

18 The method of any one of claims 15 to 17, comprising forming a layered transistor stack comprising a second transistor having a second source electrode, a second drain electrode and a second gate electrode.

19. The method of claim 18, wherein the source and drain electrodes for both transistors are in the same layer.

20. The method of any one of claims 15 to 19, comprising forming an additional conducting layer comprising a capacitor plate for the or each transistor.

21. The method of any one of claims 15 to 20, comprising forming an additional conducting layer comprising a third light shield.

22. The method of any one of claims 15 to 21, comprising forming the second light shield as the bank layer which in use separates each layered transistor structure from its corresponding light emitting element.

23. A method of manufacturing an active matrix backplane comprising: manufacturing a plurality of pixel driver circuits according to any one of claims 15 to 22.

24. A method of manufacturing a display comprising: manufacturing an active matrix backplane according to claim 23; and subsequently depositing light emissive material above each pixel electrode.

25. The method of manufacturing a display comprising: forming a common electrode over each transistor stack and light emissive material

26. A pixel circuit made according to any one of method claims 15 to 22.

27. An active matrix backplane comprising a substrate bearing a plurality of pixel driver circuits according to claim 26.

28. A display comprising the active matrix backplane of claim 27.

29. A method substantially as described herein, with reference to and as illustrated in Figures 3a to 3e, Figures 5a to 5e and Figure 6.

30. A pixel circuit substantially as described herein, with reference to and as illustrated in Figures 1 to 2 and Figures 4a to 4d.