GB2522057B - A data processing system and method for handling multiple transactions - Google Patents

A data processing system and method for handling multiple transactions

Info

Publication number
GB2522057B
GB2522057B GB1400503.7A GB201400503A GB2522057B GB 2522057 B GB2522057 B GB 2522057B GB 201400503 A GB201400503 A GB 201400503A GB 2522057 B GB2522057 B GB 2522057B
Authority
GB
United Kingdom
Prior art keywords
data processing
processing system
multiple transactions
handling multiple
handling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
GB1400503.7A
Other versions
GB201400503D0 (en
GB2522057A (en
Inventor
James Mathewson Bruce
Croxford Daren
Parker Jason
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ARM Ltd
Original Assignee
ARM Ltd
Advanced Risc Machines Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ARM Ltd, Advanced Risc Machines Ltd filed Critical ARM Ltd
Priority to GB1400503.7A priority Critical patent/GB2522057B/en
Publication of GB201400503D0 publication Critical patent/GB201400503D0/en
Priority to US14/579,316 priority patent/US9830294B2/en
Priority to TW104100099A priority patent/TWI651620B/en
Priority to JP2016544675A priority patent/JP6574779B2/en
Priority to KR1020167021460A priority patent/KR102319809B1/en
Priority to CN201580003877.9A priority patent/CN105900076B/en
Priority to EP15700149.6A priority patent/EP3095037B1/en
Priority to PCT/GB2015/050009 priority patent/WO2015104535A1/en
Publication of GB2522057A publication Critical patent/GB2522057A/en
Priority to IL245841A priority patent/IL245841B/en
Application granted granted Critical
Publication of GB2522057B publication Critical patent/GB2522057B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0828—Cache consistency protocols using directory methods with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17306—Intercommunication techniques
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
GB1400503.7A 2014-01-13 2014-01-13 A data processing system and method for handling multiple transactions Active GB2522057B (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
GB1400503.7A GB2522057B (en) 2014-01-13 2014-01-13 A data processing system and method for handling multiple transactions
US14/579,316 US9830294B2 (en) 2014-01-13 2014-12-22 Data processing system and method for handling multiple transactions using a multi-transaction request
TW104100099A TWI651620B (en) 2014-01-13 2015-01-05 Data processing system and method for processing multiple transactions
EP15700149.6A EP3095037B1 (en) 2014-01-13 2015-01-06 A data processing system and method for handling multiple transactions
KR1020167021460A KR102319809B1 (en) 2014-01-13 2015-01-06 A data processing system and method for handling multiple transactions
CN201580003877.9A CN105900076B (en) 2014-01-13 2015-01-06 Data processing system and method for processing multiple transactions
JP2016544675A JP6574779B2 (en) 2014-01-13 2015-01-06 Data processing system and data processing method for handling a plurality of transactions
PCT/GB2015/050009 WO2015104535A1 (en) 2014-01-13 2015-01-06 A data processing system and method for handling multiple transactions
IL245841A IL245841B (en) 2014-01-13 2016-05-25 A data processing system and method for handling multiple transactions

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB1400503.7A GB2522057B (en) 2014-01-13 2014-01-13 A data processing system and method for handling multiple transactions

Publications (3)

Publication Number Publication Date
GB201400503D0 GB201400503D0 (en) 2014-02-26
GB2522057A GB2522057A (en) 2015-07-15
GB2522057B true GB2522057B (en) 2021-02-24

Family

ID=50191219

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1400503.7A Active GB2522057B (en) 2014-01-13 2014-01-13 A data processing system and method for handling multiple transactions

Country Status (9)

Country Link
US (1) US9830294B2 (en)
EP (1) EP3095037B1 (en)
JP (1) JP6574779B2 (en)
KR (1) KR102319809B1 (en)
CN (1) CN105900076B (en)
GB (1) GB2522057B (en)
IL (1) IL245841B (en)
TW (1) TWI651620B (en)
WO (1) WO2015104535A1 (en)

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US10795820B2 (en) * 2017-02-08 2020-10-06 Arm Limited Read transaction tracker lifetimes in a coherent interconnect system
WO2018170391A1 (en) * 2017-03-17 2018-09-20 Convida Wireless, Llc Distributed transaction management in a network service layer
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KR102007117B1 (en) * 2018-01-19 2019-08-02 전북대학교산학협력단 Method and system for processing transaction
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EP3644190B1 (en) * 2018-10-22 2021-06-23 Arm Ltd I/o coherent request node for data processing network with improved handling of write operations
US10783080B2 (en) * 2018-10-29 2020-09-22 Arm Limited Cache maintenance operations in a data processing system
US10657055B1 (en) * 2018-12-13 2020-05-19 Arm Limited Apparatus and method for managing snoop operations
US10936048B2 (en) * 2019-03-29 2021-03-02 Intel Corporation System, apparatus and method for bulk register accesses in a processor
US10970225B1 (en) * 2019-10-03 2021-04-06 Arm Limited Apparatus and method for handling cache maintenance operations
CN113448899A (en) * 2020-03-25 2021-09-28 瑞昱半导体股份有限公司 Method and system for controlling data response by means of attributes of transaction identification code
US11281403B2 (en) * 2020-03-26 2022-03-22 Arm Limited Circuitry and method
JP2020173852A (en) * 2020-07-10 2020-10-22 マイクロ モーション インコーポレイテッド Communicating with two or more slaves
US20240004551A1 (en) * 2020-10-26 2024-01-04 Google Llc Modulating Credit Allocations in Memory Subsystems
CN112491855B (en) * 2020-11-19 2023-04-07 中国联合网络通信集团有限公司 Method and device for determining handle identifier analysis state
KR102326892B1 (en) * 2020-11-25 2021-11-16 오픈엣지테크놀로지 주식회사 Adaptive transaction handling method and device for same
US11899607B2 (en) * 2021-06-01 2024-02-13 Arm Limited Sending a request to agents coupled to an interconnect
TWI813316B (en) * 2022-05-31 2023-08-21 瑞昱半導體股份有限公司 Method for data access control among multiple nodes and data access system
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Also Published As

Publication number Publication date
JP6574779B2 (en) 2019-09-11
US9830294B2 (en) 2017-11-28
EP3095037B1 (en) 2018-08-08
CN105900076B (en) 2019-12-06
US20150199290A1 (en) 2015-07-16
GB201400503D0 (en) 2014-02-26
WO2015104535A1 (en) 2015-07-16
KR20160107233A (en) 2016-09-13
IL245841A0 (en) 2016-07-31
TW201539196A (en) 2015-10-16
EP3095037A1 (en) 2016-11-23
GB2522057A (en) 2015-07-15
JP2017504897A (en) 2017-02-09
CN105900076A (en) 2016-08-24
TWI651620B (en) 2019-02-21
IL245841B (en) 2018-12-31
KR102319809B1 (en) 2021-11-01

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