GB2504614A

GB2504614A - Complimentary Heterojunction Field Effect Transistor

Info

Publication number: GB2504614A
Application number: GB201312673A
Authority: GB
Inventors: Quentin Diduck; Dubravko Babic
Original assignee: Element Six Technologies US Corp
Current assignee: Element Six Technologies US Corp
Priority date: 2012-07-17
Filing date: 2013-07-16
Publication date: 2014-02-05
Also published as: GB201312673D0

Abstract

A method for manufacturing a complimentary field effect transistor comprising: providing a wafer comprising at least a buffer layer 202, a second barrier layer 203 and a first barrier layer 210; removing said first barrier layer 210 in at least a first area of the wafer; and forming n-type ohmic contacts 207,209 and Schottky contacts 208 in the first area and forming p-type ohmic contacts 204,206 and Schottky contacts 205 on the first barrier layer 210. Also disclosed is the device produced by the above method, wherein the buffer layer is a first AlGaN layer with a first aluminium composition, the second barrier layer is a second AlGaN layer with a second aluminium composition and first barrier layer is a GaN layer; where a first heterojunction 213 is formed between the two AlGaN layers, a second heterojunction 212 is formed between the second AlGaN 203 and GaN 210 layers; where a hole accumulation layer is present at the second heterojunction 212 and an electron accumulation layer is present at the first heterojunction 213.

Description

GALLIUM NITRIDE-BASED COMPLIMENTARY HETEROSTRUCTURE FIELD-

EFFECT TRANSISTOR PAIR

FIELD OF THE INVENTION

This application related to monolithic integration of gallium nitride-based electronic devices. More specifically, the application relates to creating n-channel and p-channel high electron mobility transistors using gallium nitride and related materials, and methods of their integration.

BACKGROUND OF THE INVENTION

Complimentary p-channel and n-channel field-effect transistors (FETs) are essential elements of digital electronics and many analog and switching power applications, such as, high-efficiency push-pull Class B amplification and switching amplifiers. Novel solid-state high-power amplifiers and power electronics rely on gallium nitride (GaN) and related materials (AIGaN, InGaN) for high voltage and high power operation. Both n-channel and p-channel AIGaN/GaN heterostructure field-effect transistors (HFET5) can be made, but their performance is very different owing to high activation energies of p-type dopants and low whole mobility values in GaN. Furthermore, the epilayer structures used for n-channel and p-channel devices differ considerably and building complimentary pairs for circuits is not available.

The operation and practical implementation of n-channel AIGaN/GaN HFETs are well known in the art. AIGaN/GaN n-channel HFET is also commonly referred to as the high-electron mobility transistor (HEMT). The present state of the technology is available from publicly available texts such as Rudiger Quay Gallium Nitride Electronics published by Springer Verlag in 2008 and U.K. Mishra and J. Singh, Semiconductor Device Physics and Design published by Springer Verlag in 2008.

A typical gallium-nitride-based n-channel HFET structure 100 is illustrated in Figure 1. This exemplary transistor 100 comprises a substrate 101 on top of which a layered structure 110 is grown. The layered structure 110 comprises gallium nitride buffer layer 103 and a barrier layer 104 forming a two-dimensional electron gas (2DEG) 105 as is well known in the art of manufacturing high electron mobility transistors. The field-effect transistor also features electrical contacts to the source 106, drain 107, and gate 108. The gate 108 forms a Schottky barrier junction to the topmost layer 104. Inasmuch as GaN is a single crystal with a lattice constant that is d i ff e rent from the substrate, it i s necessary to grow several semiconductor layersto accommodate forthe lattice constant change and a b so r b the dislocations. These layers are collectively referred to as the transition/nucleation layers 102, and typically comprise ternary AIGaN alloys or just AIN. The electrons in the 2DEG 105 have very high mobility and carry current from the source 110 to the drain 107.

This current path is commonly referred to as the channel. The density of the electrons in the channel determines the resistance between the source and the drain and is controlled with the voltage on the gate terminal 108 relative to the source 106 and the drain 107. Finally, using a small voltage applied to the gate terminal 108 one can efficiently control the electron concentration in the 2DEG -this is the fundamental requirement for current and power amplification in electronic devices. Since in the described HEFT, the current in the channel is conducted by the electrons, it is referred to as an n-channel field-effect transistor.

Figure 2a illustrates the calculated energy band-diagram: conduction and valence band edges as a function of depth from the surface for zero bias assuming the Schottky barrier is 1 eV. Figure 2b shows the corresponding electron density and features one deep accumulation of electrons at the heterojunction between the AIGaN barrier and GaN buffer. In this example, the AIGaN barrier was 9 nm thick comprising 25% Al content in AIGaN. Applying negative voltage across the gate will repel the electrons from the gate and reduce the channel conductance.

P-type channel AIGaN/GaN field-effect transistors can be realized in a number of ways. Several examples are given in publications T. Zimmermann, et al., "P-channel InGaN-HFET structure based on polarization doping", published in IEEE Electron Device Letters, vol. 25, no. 7, P. 450 (2004), and M. S. Shur, et al., "Accumulation hole layer in p-GaN/AIGaN heterostructures", published in Applied Physics Letters, vol. 76, no. 21, p. 3061 (2000). Figure 3 (PRIOR ART) illustrates the approach of M. Shalatov, et al., "GaN/AIGaN p-channel inverted heterostructure JFET", published in IEEE Electron Device Letters., vol. 23, no. 8, p. 452 (2002). This exemplary transistor 300 comprises a substrate 301 on top of which nucleation/transition layers 302 are grown followed by layered structure 310. The layered structure 310 comprises an n-type aluminum-gallium-nitride (AIGaN) layer 303 which is relaxed, a p-type AIGaN barrier layer 309 lattice matched to the layer 303, and a GaN buffer layer 304 forming a two-dimensional hole gas (2DHG) 205 at the heterojunction between the buffer layer 304 and the barrier layer 303 as is well known in the art of manufacturing high electron mobility transistors. The field-effect transistor 300 also features electrical contacts to the source 306, drain 307, and gate 308 which are made to the buried n-type AIGaN layer (ohmic contact).

Figure 4a illustrates the calculated energy band-diagram for the structure shown in Figure 3: conduction and valence band edges as a function of depth from the surface for zero bias assuming the Schottky barrier is 1 eV. Figure 4b shows the corresponding hole density and features one deep accumulation of holes at the heterojunction between the buried AIGaN barrier and top GaN buffer. The AIGaN barrier is 20 nm thick and comprises 40% Al content. Applying a positive voltage across the gate will repel the holes from the gate and reduce the channel conductance.

It is clear that the epilayer structures needed to make n-channel and p-channel field effect transistors are sufficiently different that a single structure or parts of a single structure cannot be used to create both devices. For this reason there have not been attempts to integrate the two structures monolithically into one. It is the objective of present invention to disclose complimentary pairs based on GaN transistors that can be grown on the same substrate. In is also the objective of this invention to enable integration of p-channel and n-channel devices onto the same substrate and enable integrated circuits, including monolithic microwave integrated circuits (MMIC5) and complimentary MMICs.

SUMMARY OF THE INVENTION

This patent application discloses (a) monolithic integration of n-channel and p-channel GaN field -effect transistors, (b) methods for to r m i n g this integration, and (c) circuit configurations that take advantage of the disclosed preferred heterogeneous integration.

In the semiconductor industry, the word integration of devices means building all electronic devices of the circuit on a single semiconductor chip (monolithic integration) or placing at least one chip on a different, typically non-semiconductor, substrate and connecting the chip(s) with passive components and other chips using technology adopted for the non-semiconductor substrate, such as, alumina or FR4, referred as hybrid integration. Monolithic integration stands for device integrated on a chip where the devices are processed in sequence by processing on the same chip, rather than adding a device externally.

Monolithic integration generally means that all of the devices and passives are realized using the same semiconductor substrate (monolithic referring the lattice constant being substantially the same for all devices on the chip). When integration of devices with different crystal structure is realized on a semiconductor substrate, one speaks of heterogeneous integration. This application deals w it h monolithic integration, but the inventions can be employed for heteogenouls integration as well without departing from the spirit of the invention.

In one embodiment, monolithic integration of p-channel and n-channel AIGaN/GaN HFETs is realized by growing a specific epilayer structure that gives rise to a p-channel HFET when p-contacts and a Schottky gate are disposed on the surface of this specific epilayer structure, but when a part of the specific epilayer structure is etched away and n-contacts and an n-Schottky gate are deposited on the remaining epilayer structure, it operates as an n-channel HEET. The essential problems in designing this specific epilayer structure are adjusting the thickness, the composition, and the doping of the epilayers so that the structure indeed exhibits a hole accumulation and p-channel HFET action in the as-grown structure and n-channel action when a selected parts of the epilayer are removed. Failing to properly design this results in either lack of hole accumulation or the presence of both hole and electron accumulations in the as-grown structures, both problems will prevent the as-grown device to operate as a p-channel HFET or an n-channel HEFT. This is the reason why this approach has never been attempted.

The method for manufacturing a chip both n-channel and p-channel AIGaN/GaN HFETs comprises of etching at least a part of the surface of the chip to access the layers that area designed to provide n-channel action and leaving the rest of the areas for fabricating p-channel HEFTs. The process subsequently comprises in fabricating devices on so-etched wafer surface.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 (PRIOR ART) A conventional n-channel AIGaN/GaN field-effect transistor.

Figure 2 (PRIOR ART) (a) calculated energy band diagrams and (b) electron concentration profile for a typical n-channel HFET with structure shown in Figure 1.

Figure 3 (PRIOR ART) An example for conventional p-channel AIGaN/GaN

field-effect transistor.

Figure 4 (PRIOR ART) (a) Calculated energy band diagram and (b) hole concentration profile for a typical p-channel HFET with structure shown in Figure 3.

Figure 5 (a) An example of epilayer design that would produce a p-channel HFET. (b) Same epilayer design, but with a part of the epilayer etched off so it would produce an n-channel HFET.

Figure 6 Energy band-diagram used in the derivation of the design conditions.

Figure 7 Specific epilayer structure used in the first embodiment.

Figure 8 Electron and hole concentration versus gate voltage for several n-channel and p-channel field-effect transistors according to the first embodiment.

Figure 9 Specific epilayer structure used in the second embodiment.

Figure 10 Electron and hole concentration versus gate voltage for several n-channel and p-channel field-effect transistors according to the second embodiment.

Figure 11 (a) Calculated energy band diagram and (b) hole concentration profile for an exemplary n-channel HFET with design I from Table II.

Figure 12 (a) Calculated energy band diagram and (b) hole concentration profile for an exemplary p-channel HFET with design H from Table II. The Design H has identical n-barrier and n-buffer design as Design I with the exception of the added p-barrier layer.

Figure 13 An exemplary view of an embodiment of p-channel and n-channel HFETs monolithically integrated on a single chip.

Figure 14 Top view of an embodiment of a p-channel and an n-channel HFET monolithically integrated on a single chip.

Figure 15 Illustration of the semiconductor-device process realizing integrated p-channel and n-channel HFETs on the same wafer.

Figure 16 Block diagram of one embodiment of the semiconductor-device process realizing integrated p-channel and n-channel HFETs on the same chip.

DETAILED DESCRIPTION OF THE INVENTION

The integration of n-channel GaN HFET and a p-channel diamond HFET offers advantages to a number of circuit configurations commonly used in linear and switching circuits.

Figure 5 illustrates one embodiment of the epilayer structure 530 which after device processing gives rise to both p-channel and n-channel AIGaN/GaN field-effect transistor. The epilayer structure 530 comprises of a substrate 501 on top of which using suitable nucleation layers 511 is grown followed by an n-buffer 502. The substrate 501 may be made out of silicon, silicon carbide, aluminum nitride, diamond, or gallium nitride. The nucleation layer 511 is optional. The n-buffer 502 may be unintentionally doped or slightly n-type doped. An n-barrier layer 503 is disposed on top of the n-buffer 502, and on top of the n-barrier layer 503, there is a p-barrier layer 504. The p-barrier 504 is terminated with layers (no shown) that promote ohmic contacts and Schottky barrier 506 formation at a later stage in the process. Structure 530 illustrates a Schottky metal 506 disposed on top of the p-barrier 504. In one embodiment, a thin layer of p-type doping or so-called 6-doped layer 505 is present within the p-barrier 504 just above the heterojunction 507 between the p-barrier 504 and the n-barrier 503.

The design of structure 530 is adjusted to satisfy two conditions: the first condition is that for a useful p-HFET gate voltage range (VGS= -1 to -MV, for example) applied to a gate terminal 506 disposed on the surface of the p-barrier 504, the structure 530 exhibits a hole accumulation at the heterojunction 507, and that at the same time, no electron accumulation is present at the heterojunction 508 between the n-barrier layer 503 and the n-buffer 502. The second condition is that strong electron accumulation would be generated at the heterojunction 508 between the n-barrier layer 503 and the n-buffer 502, when the p-barrier 504 is removed and replaced with a Schottky metal 509 as it is illustrated in structure 540. Figure 5 shows that the layers 510 (in structure 540) are necessary to make an n-channel HFET, and the addition of layers 520 on top of the layers 510 (in structure 530) creates a p-channel HFET while it defeats the n-channel action in the structure 540.

These two conditions can be expressed in simple, but approximate mathematical terms with the help of Figure 6 for the two different embodiments. The design will be described for building depletion mode HFETs as enhancement mode devices can be created by localized modification of the GaN epilayer structure as is known in the art. Figure 6 shows a simplified band-diagram for the topmost layers of structure 530 where the p-barrier layer 1 is disposed on top of the n-barrier layer 2, which is then disposed on top of an n-buffer 3. A Schottky contact 11 is disposed on the top surface 10 of the p-barrier 1. In the p-FEE, the n-barrier 2 serves as a buffer, but we will refer to this layer as the n-barrier throughout the specification, understanding that is has a double function: it serves as a buffer in the p-FET (structure 530) and as a barrier in the n-FET (structure 540). In the structure shown in Figure 6, a p-channel will form around the heterojunction 12, and when the p-barrier is removed, the n-channel will form around the heterojunction 23. All of the material and physical attributes of the three layers shown in Figure 6 (1, 2, and 3) will be identified with subscripts 1, 2 and 3, where these digits refer to the p-barrier, n-barrier, and the n-buffer respectively. Each of these layers (shown in Figure 6) features a thickness d, aluminum composition x, energy bandgap EG, and dielectric permittivity £.

Depositing metals on AIGaN or GaN can produce close to ideal Schottky contacts, which means the Schottky barrier depends primarily on the work-function of the deposited metal. We quantify the contact with the barrier for electrons 0B (in this specification positive value expressed in Volts rather than Joule) as Ø E ( -X)e, where Ø, is the metal work-function and X the electron affinity of the semiconductor adjacent to the metal. When the same metal is used for a p-type semiconductor, the Schottky barrier is for holes EG -0B, where EG is the bandgap of the material next to the metal. This definition also works the case when the Schottky barrier height is determined by Fermi-level pinning.

Since the Schottky barrier on the p-type semiconductor can be calculated from in the upcoming analysis we will specify on only ø for both p-type and n-type semiconductors. In the upcoming graphs we shall use the difference VGS -ø as the independent variable describing the potential applied on the gate relative to the n-buffer (or the substrate). This is reference is selected because when VGS - = 0, the conduction band touches the Fermi level. Furthermore, in the upcoming analysis we will assume that a substantial accumulation of carriers is present if the conduction or the valence band cross or touch the Fermi level. The typical value for 08 used in this disclosure is 1 Volt.

The energy bandgap EG2 of the n-barrier layer 2 is larger than the bandgap EG1 of the p-barrier 1 and the bandgap EG3 of the n-buffer 3, but EGI and EG3 do not necessarily have to have to be equal. For the purpose of this simplified analysis, all of the layers are negligibly doped. The growth of GaN starts from the substrate (not shown) followed by the n-buffer 3 and ends with the p-barrier 1 and the surface 10. The n-buffer 3 is assumed to be relaxed, i.e., the lattice constant is defined and in one embodiment equal to the lattice constant of GaN.

The growth surface 10 is Ga-terminated, namely, the semiconductor surface below the Schottky barrier 11 is Ga-terminated. For this reason, the spontaneous and piezoelectric charges at the interfaces between GaN and AIGaN are positive (Q2s) when going from n-GaN buffer 3 to AIGaN n-barrier 2 and negative (- Q12) when going back from AIGaN n-barrier 2 to CaN p-barrier 1. When n-buffer 3 and the p-barrier 1 are made of CaN or same aluminum composition AIGaN, these two spontaneous charges will be approximately equal (Q12 = Under general conditions (composition of the AIGaN n-barrier 2, n-barrier thickness d2, and the p-barrier thickness di), the structure shown in Figure 6 may have no charge accumulation at any of the heterojunctions or may have both electron and hole accumulations at those heterojunctions. One first needs to ensure that there is a hole accumulation at the heterojunction 12 between the p-barrier 1 and the n-barrier 2 layers. This may be accomplished by adding a sheet of negative charge with charge density Q5 next to the junction 12 as shown in Figure 6. To make a depletion mode p-channel HFET, a hole accumulation is necessary when VGS = 0. This means that we need the valence band to touch the Fermi level right at the interface 12, while at the surface 10 the valence band to Fermi level separation has to be around EGI -0B' To determine the geometrical and compaition attributes, this potential relationship has to be combined with the fixed charges in the structure. It is straightforward to show that the relationship between the charges and the potentials can be written approximately as, Q5 +Q2 Q,3 »=[t BJ e [1/area] (1) Here z is the dielectric permittivity of the p-barrier, e the electron charge, EGI the bandgap of the p-barrier, d1 the thickness of the p-barrier, and Q12 and Q23 spontaneous/piezoelectrically induced charger densities at the interfaces between the p-barrier to n-barrier and between the n-barrier and the n-buffer, respectively.

The second requirement to make a p-channel FET using band-diagram shown in Figure 6 is that, while there is a hole accumulation at the interface 12, there is no electron accumulation at the interface 23. Again, using basic electrostatic relationship, one can show that when the n-buffer is made out of AIGaN with composition x3 and its bands are flat the conduction band edge satisfies the following relationship: + JiE(1-*2) -Q23d2e2/s2 -aE(3-)2) -= 0 Here (73 (energy) is the difference between the conduction band and the Fermi-level in the n-buffer, £2 is the dielectric permittivity of the n-barrier, d2 the thickness of the n-barrier. The conduction band offsets in going from layer 1 to layer is denoted by /iE(1-*2) and is taken positive if the conduction band offset increases when going from layer 1 to layer 2. The conduction band offset AE(3-2) is defined similarly. Clearly, we will have AE(1-)2) > AE(3-*2) if the band gap of n-buffer 3 is larger than then the p-barrier 1. We introduce AEC13 SE(132) -JiE(3-*2). (If offset transitivity rule applies, SEC13 = SEC(1-*3)).

We use this substitution to determine the condition on Q23 for which there will be no electron accumulation as, Q2, «=[i +A/4? [1/area] It is clear that Q23 depends on the aluminum composition in both layers 2 and 3, and that SEC13 depends on the aluminum composition of layers 1 and 3 (and possibly layer 2, if band offset transitivity rule does not hold). Finally, conditions (1) and (2) provide implicit design rules for determining physical and material parameters for realizing p-channel in structure 530. The spontaneous/piezoelectrically induced fixed charge in AIGaN (and other polar semiconductors) is related to the composition (and the resulting strain when grown on a different lattice constant). Therefore, conditions on the spontaneous and piezoelectrically induced charges Q12 and Q23 (and hence on the band offset SEC13 and £ dielectric permittivities) in equations (1) and (3) can easily be converted into constraints on aluminum composition in the n-barrier x2 and/or n-buffer x3. Optimal design satisfies equation (1) and (2) as close as possible to the equality sign simultaneously with the desired performance of the n-channel PET whose design (using structure 540) is well known in the art. The Schottky barrier height and the aluminum concentration x2 in the n-barrier are adjusted to create a high density 2DEG in structure 540 at the junction 508. The design rules are given in the publicly available textbooks listed above.

For procedure for design of the epilayers goes as follows: (i) an epilayer design is created that produces a desired n-channel HFET. (U) Then-barrier is optionally made slightly thicker to allow for some over-etching when the p-channel FET structure is being converted in the later stage of the process. Finally, (iii) p-barrier is added with appropriate delta-doping, if required. The thickness of the p-barrier is adjusted to create hole accumulation. Two embodiments describe specific approaches to this design and structures.

Accumulation or depletion of carriers refers to the phenomenon in which carriers are grouped in or repelled from an area within a device. Accumulation and depletion of carriers are phenomena associated with junctions and interfaces in semiconductors where either built or external electric fields or inter-facial atomic fields are present. We say an accumulation is present when the density of carriers at a location is higher than it would be if there was no built-in or external electric field or interfacial atomic fields. The built-in electric fields are responsible for the depletions of carriers around a pn-junction and Schottky barrier.

Externally applied field on a metal-oxide-semiconductor structure can produce either a depletion or an accumulation, depending on the potential. A discontinuity in the periodicity of the atomic fields can produce what is generally observed as a heterojunction band offset and interfacial charge, as is the case with AIGaN/GaN heterojunctions. For example, a typical straddling (Type I) isotype heterojunction between AIGaAs and GaAs will exhibit an accumulation of electrons on the GaAs side of the junction and depletion of electrons on the AIGaAs side of the junction as is well known in the art.

For the purposes of this application, accumulation (or depletion) of carriers next to an interface is present when the density of carriers over at least some region is higher (or lower) next to that interface than it would be if the interface was removed. The region in depth perpendicular to the plane of the junction over which the carriers are accumulated is referred to as the accumulation layer.

Similarly, depletion layer is the region over which the carriers are depleted. The consequence of this is that an accumulation layer is capable of conducting electrical current in the plane of the junction better than the rest of the semiconductor away from the junction, while the depletion layer is less conductive that the rest of the semiconductor in the vicinity of the interface.

First embodiment: delta-doQing In one embodiment, the n-buffer and the p-barrier are made of GaN, hence Q12 = Q23 and SEC13 = 0 in equations (1) and (2), the sheet of negative charge is realized by providing heavily doped sheet of acceptors. If the doped sheet has the width 5, the doping density NA is given with Qa = NA 5. Clearly, since the p-type doping efficiency in GaN and AIGaN is quite inefficient, the thickness of the doped layer may have to be several nanometers, but the accumulation of holes will be realized nevertheless. In one embodiment, the sheet of acceptors of width 5 is distanced from the heterojunction by a spacer of thickness d8 to reduce impurity scattering and improve the mobility of holes in the channel.

This embodiment is illustratively depicted with Figure 7 where an exemplary schematic of the epilayer structure is shown with the key parameters (thickness, doping level, and aluminum composition). The p-barrier with thickness di may include a thin p-doped layer with thickness 5 and doping NA within that layer.

This 5-doped layer is separated from the n-barrier by a spacer of thickness d.

The p-barrier is disposed on top of the AIGaN n-barrier with thickness d2 and aluminum composition equal to x2. The thickness of the n-buffer c/s below the n-barrier is sufficiently large to allow the buffer exhibit low defect density and prevent the substrate or the nucleation-layer disturbing the p-channel or the n-channel FET5 to be built. Table 1 shows several exemplary designs that were numerically solved using a Poisson solver called BangEng from UC Santa Barbara. We used EG = 3.3 eV and B = 1 V in the simulations. The designs are denoted with A though E, and the resulting electron and hole concentrations versus gate voltage are shown in Figure 8. The figure shows that control of the transfer characteristics of both the n-channel and the p-channel FETs will be possible by suitable design and the graphs show that on the same epilayer it is possible to make n-channel and p-channel FETs. Specifically, design F shows the characteristics of a p-FET and design B the n-HFET operating on the same epilayer structure once the p-barrier is etched off proving the inventive concept.

The graphs in Figure 8 are plotted versus VGS = 0B so zero bias occurs when VGS -= -1 V. Even though using equation (1) and (2) one can define the design, some amount fine tuning is necessary because Schottky barrier heights vary between metals, the doping efficiency, and spacer width (not included in equations (1) and (2)) will have an effect on the optimal epilayer structure. By fine adjustment of the available parameters, one can adjust that both transistors have similar loss values.

Design A B C D E c/i --22nm 32nm l5nm 5, NA [crif3] --2 nm, 2 nm, 2 nm, 3.8 x 1019 2.6 x 1019 5.6 x 1019 --Onm Onm 2nm 17 nm, 9nm,25% 9nm,28% 10 nm, 9nm,25% 25% 25% Q5[cm2] >5.1 x1012 >3.5x 1012 >3.8x 1019 d3 lOOnm lOOnm lOOnm lOOnm lOOnm Table I: Design examples for the first embodiment Second embodiment: AIGaN n-buffer In another embodiment, the n-buffer is made of AIGaN with aluminum composition x3>Q and the p-barrier is made of GaN (xi = 0), hence Q12 > Q23 and AEC13 > 0, the sheet of negative charge is omitted (Q5 = 0). The accumulation of holes is realized by net negative fixed charge around the junction 12 by spontaneous and piezoelectric means. In this case, the optimal aluminum composition in n-buffer is given implicitly with equations (1) and (2). The exemplary epilayer structure that implements this embodiment is shown in Figure 9 where on top of a substrate and the nucleation layer, at least an AIGaN n-buffer is grown with thickness d3 and aluminum composition x3, followed by an n-barrier of thickness d2 and aluminum composition x2, and completed with at least a GaN p-barrier with thickness d1. The growth surface (top of the p-barrier layer) is Ga-facing. Inasmuch as the n-buffer has higher aluminum composition than the p-barrier layer, there will be a net negative fixed charge layer at the heterojunction between the n-barrier and the p-barrier attracting holes and forming a hole accumulation. It is possible to use the same design principles and p-channel/n-channel HFET integration scheme to design similar epilayers on an N-facing GaN epilayer stack without departing from the invention. In that case, Q12 and Q23 charge dependence on the strain and composition will be different.

Table II illustrates two simulations of epilayer structures that take advantage of the second embodiment. Design F is p-channel HFET and design G is a n-channel HFET that uses the same two bottom layers. Similarly, designs H and I are the p-channel and n-channel HFETs on the same epilayer structures (n-channel HFET has the p-barrier removed).

Design F G H 2Onm 22 nm lOnm,46% lOnm,46% 8nm,40% 8nm,40% lOOnm,28% lOOnm,28% lOOnm,20% lOOnm,20% Table II: Design examples for the second embodiment Figure 10 shows the hole and electron surface density at the channels as a function of the gate voltage for the designs shown in Table II. Clearly, with proper design one can achieve 2DEG and 2DHG with very high carrier densities. Figure 11 illustrates calculated band-diagrams and hole density for design H with VGS -= -1 V (p-channel HFET). Figure 12 illustrates calculated band-diagrams and hole density for design with VGS -= -1 V (n-channel HFET). Design I is obtained by removing thep-barrier from design H. The above designs were performed for Ga-facing growth surfaces. In one embodiment, the growth surface may be N-facing in which case the relationship between the charges and strain will change and it is possible to exchange the growth order of the p and n channels. In this latter case, the functional layers p-barrier, n-barrier, and n-buffer change their respective roles to n-barrier, p-barrier, and p-buffer, respectively.

Figure 13 illustrates an AIGaN/GaN complimentary pair 200 comprising of at least one p-channel and one n-channel HFET monolithically integrated on a single chip.

In one embodiment, the complimentary pair 200 comprises of a substrate fl1 on top of which an optional nucleation layer 211 is grown. The working layers 214 comprise a buffer layer 202, a second barrier layer 203, and a first barrier layer 210.

On top of at least a part of the chip 200 metal contacts are deposited comprising at least ohmic contacts 204 and 206, and a gate 205 forming a HFET 220 exhibiting a carrier accumulation 212 of the first carrier kind at the heterojunction between the first barrier layer 210 and the second barrier layer 203. In at least some parts of the surface of the chip 200, the first barrier layer 210 has been removed to reveal the second barrier layer 203. In those areas, at least some ohmic contacts 207 and 209 and a gate 208 are deposited on the second barrier layer 203 forming a HFET 230 exhibiting carrier accumulation 213 of the second carrier kind at the heterojunction between the second barrier layer 203 and the buffer 202. In one embodiment, the first and second carrier kinds are electrons and holes, respectively. In yet another embodiment, the first and second carrier kinds are holes and electrons, respectively.

Figure 14 illustrates the top of exemplary chips which comprise integrated p-channel and n-channel HEELs as described with Figure 13. Figure 14(a) shows the top view of a chip 401 surface according to one embodiment in which a first barrier layer was removed in most area of the chip surface leaving at least one island 402 where the first barrier layer remained. Figure 14(c) shows the side-view cross section of the same structure shown in Figure 14(a) along a cut 405.

Figure 14(b) shows the top view of a chip 403 surface according to another embodiment in which a first barrier layer was removed in certain enclosed areas 404 of the chip surface leaving most of the area where the first barrier layer remained. Figure 14(d) shows the side-view cross section of the same structure shown in Figure 14(b) along a cut 406.

Figure 15 illustrates one embodiment of the fabrication process of fabricating n-channel/p-channel AIGaN/GaN HFET complimentary pair on a single substrate.

Starting in Step 15(a) with a wafer comprising a substrate, a buffer disposed on top of said substrate, a second barrier layer disposed on said buffer, and a first barrier layer disposed on top of said second barrier layer. In step 15(b), the wafer is masked to pattern the areas that will be etched off, and the first barrier layer is removed in at least some areas of the wafer. In step 15(c), positive liftoff is performed in which contacts top-type GaN are made at the same time as the Schottky contact to the n-channel HFET gate. In one embodiment, this simultaneous contact is accomplished using Scandium metal. In step 15(d), another liftoff process is used to form ohmic contacts to the n-GaN. In step 15(e), the photo-resist is removed and the ohmic contacts are annealed. In step 15(f), the wafer is patterned and reactive-ion etching is used to etch trenches around the devices for isolation. In step 15(g), n-channel devices may be tested. In step 15(h), using another liftoff process, p-type metallization is deposited forming both p-channel gate and the pad/interconnect metal. Finally, in step 15(i), the devices are complete.

Figure 16 illustrates the block diagram of one embodiment of the fabrication process of fabricating n-channel/p-channel AIGaN/GaN HFET complimentary pair on a single substrate. In Step 1601, a wafer comprising a substrate, a buffer disposed on top of said substrate, a second barrier layer disposed on said buffer, and a first barrier layer disposed on top of said second barrier layer is provided. In Step 1602, the wafer is masked to pattern the areas that will be etched off, and the first barrier layer is removed in at least first area of the wafer. In Steps 1603 and 1604, which may be combined or exchange order according to specific process, metal contacts forming n-type ohmic contacts and Schottky contacts to n-type material are deposited in the first area, and metal contacts forming p-type ohmic contacts and Schottky contacts to p-type material are deposited on the first barrier layer. The contact annealing steps are included in the steps 1603 and 1604 in proper order to ensure that high-quality p-type and n-type contacts are formed in respective area on the wafer, as is known in the art. In one embodiment, the first area will contain at least one n-channel HFET and the wafer will contain at least one p-channel HFET not disposed in the first area. The first barrier layer, second barrier layer, and said buffer layer are made out of AIGaN or GaN. In an embodiment, the p-channel HFET and the n-channel HFET are electrically coupled on said wafer. The p-channel HFETs and n-channel HFETs may be isolated by implantation or etching trenches as is well known in the art.

It is clear from the presented embodiments that variations on specific parameters to optimize or modify the transistors and the epilayers structures for different applications is possible without departing from the invention.

Claims

Claims 1. A method for manufacturing complimentary field-effect transistor pair comprising: providing a wafer comprising at least a buffer layer, a second barrier layer disposed on said buffer, and a first barrier layer disposed on said second barrier layer; removing said first barrier layer in at least first area of said wafer; and forming n-type ohmic contacts and Schottky contacts to n-type material in the first area, and p-type ohmic contacts and Schottky contacts top-type material on said first barrier layer.
2. A method according to claim 1, wherein said first barrier layer is made out of gallium nitride, said second barrier layer is made out of aluminum gallium nitride, and said buffer layer is made out of gallium nitride.
3. A method according to claim 1 or claim 2, wherein a layer of acceptor dopant is present within said first layer proximal to said second barrier layer.
4. A method according to any preceding claim, wherein at completion of said forming step, said first area comprises at least one n-channel field-effect transistor and said wafer comprises at least one p-channel HFET not disposed in said first area.
5. A method according to any preceding claim, wherein said n-channel field-effect transistor and said p-channel field-effect transistor are electrically coupled.
6. A method according to any preceding claim, wherein said first barrier layer is made out of gallium nitride, said second barrier layer is made out of aluminum gallium nitride having a second aluminum composition, and said buffer layer is made out of aluminum gallium nitride having a first aluminum composition.
7. A method according to claim 6, wherein said second aluminum composition is larger than said first composition.
8. A method according to any preceding claim, wherein at completion of said forming step, said first area comprises at least one n-channel field-effect transistor and said wafer comprises at least one p-channel HFET not disposed in said first area.
9. A method according to claim 8, wherein said n-channel field-effect transistor and said p-channel field-effect transistor are electrically coupled.
10. A method according to any preceding claim, wherein a layer of acceptor dopant is present in said first barrier layer proximal to said second barrier layer.
11. A method for manufacturing complimentary field-effect transistor pair comprising: providing a semiconductor wafer, said wafer having at least a first AIGaN layer, a second AIGaN layer forming a first junction with said first AIGaN layer, a GaN layer forming a second junction with said second AIGaN layer, wherein a hole accumulation layer is present at said second junction and an electron depletion layer is present at said first junction; removing said GaN layer in at least one area, said removing resulting in an electron accumulation layer forming at said first junction; fabricating at least one n-channel HFET within said at least one area; and fabricating at least one p-channel HFET devices on said surface of said semiconductor wafer, but not within said at least one area.
12. A method according to claim 11, wherein said second AIGaN layer has aluminum composition larger than said first AIGaN layer.
13. A method according to claim 11, wherein said second AIGaN layer has aluminum composition equal to zero.
14. A semiconductor layered structure comprising: a first AIGaN layer having first aluminum composition; a second AIGaN layer disposed over said first AIGaN layer and forming a first heterojunction, said AIGaN layer having a second aluminum composition; a GaN layer disposed over said second AIGaN layer forming a second heterojunctions with said second AIGaN layer; at least a gate metal contact disposed on the surface of said GaN layer; wherein a hole accumulation layer is present at said second heterojunction, and electron depletion layer is present at said first heterojunction.
15. A semiconductor layered structure according to claim 14, wherein said GaN layer comprises a layer of acceptor dopant proximal to said second AIGaN layer.
16. A semiconductor layered structure according to claim 14 or claim 15, wherein said second aluminum composition is larger than said first aluminum composition.