GB2488970A - A reconfigurable filter for TV or radio receiver ICs - Google Patents

Abstract

A configurable high gain Zero IF or low IF receiver filter circuit comprises two active filter channels which may be cross-coupled to obtain a polyphase response. The active filter channels comprise cascaded first and second order filter sections. Each filter section comprises operational amplifiers with integrating or RC feedback. Resistors and capacitors in the filters may be adjusted digitally to configure the filters for lowpass or bandpass response, with Butterworth or Chebyshev response. DC offsets may be removed by feedback (figures 6-18). The configurability of the IF filter allows a receiver IC to handle different broadcast standards without provision of a separate IF filter for each standard

Description

RECONFIGURABLE FILTER

FIELD OF INVENTION

The disclosure relates to a reconfigurable filter, a television or radio tuner chip comprising such an electronic filter and a method of configuring a filter.

BACKGROUND

Single chip television/radio tuners are increasingly implemented in set top boxes, Liquid Crystal Display (LCD) televisions, mobile communications devices and the like. They have many advantages over traditional metal can tuners. For example single chip tuners are lower cost, require fewer external components, have lower power consumption and are physically smaller than metal can equivalents.

Television and radio signals are typically modulated and converted to a higher carrier frequency (typically high MHz or GHz ranges) before being broadcast. Television/radio tuners are required to downconvert received television/radio signals from this carrier frequency to a lower frequency before the signal can be processed. After downconversion, television/radio tuners are also typically required to reject unwanted signals produced during the downconversion process. The downconverted and filtered signals are then input to baseband circuitry where they are processed into a suitable format for reproduction.

Television/radio tuners typically comprise an intermediate frequency (IF) filter to reject the unwanted signals. However, the optimal IF filter type is dependent on the particular interface architecture between the downconverter and the baseband circuitry, and on the TV/radio broadcast standard employed to modulate and convert the signals.

Different IF filters may be provided to perform the filtering process for different broadcast standards and/or interface architectures. However, it is more desirable to provide a single IF filter which can be reconfigured to provide the appropriate response depending on the standard/architecture.

In addition, IF filters with high gains can introduce significant unwanted DC offsets to the filtered/downconverted signals. These DC offsets typically need to be compensated for to ensure that the output signals from the IF filter are reliable.

SUMMARY OF INVENTION

A first aspect of the disclosure provides a reconfigurable electronic filter comprising: a first stage having a first pair of cross coupled amplifiers, each amplifier having an input and an output electrically coupled together via a respective first stage variable capacitor, the first pair of amplifiers being cross coupled via first stage variable resistors; a second stage having cascaded second and third pairs of cross coupled amplifiers, each amplifier having an input and an output electrically coupled together via a respective second stage variable capacitor, the second and third pairs of amplifiers each being cross coupled via second stage variable resistors; and a controller configurable to set the first stage capacitors to a first capacitance value and the second stage capacitors to a second capacitance value different from the first capacitance value, and to set the first stage resistors to a first resistance value and the second stage resistors to a second resistance value different from the first resistance value.

Preferably the resistance and capacitance values of the variable resistors and capacitors are independently variable by the controller. Even more preferably, the resistance and capacitance values of the variable resistors and capacitors are independently programmable.

By providing a controller configurable to set the first stage capacitors to a first capacitance value and the second stage capacitors to a second capacitance value different from the first capacitance value, and to set the first stage resistors to a first resistance value and the second stage resistors to a second resistance value different from the first resistance value, the filter can be configured to implement different poles in the first and second stages. This allows the filter to be (re)configured to provide a band-pass Chebyshev configuration which is preferred for many applications, including some TV/radio tuner applications. However, the filter may also be (re)configured in other configurations, such as band-pass Butterworth configuration.

Typically, the controller is configurable to set the product of the first resistance value and the first capacitance value to be substantially equal to the product of the second resistance value and the second capacitance value. This allows the cut-off frequencies of the first and second stages to be made substantially equal, even when they implement different poles (e.g. in a Chebyshev configuration).

In one embodiment, a feedback path is provided between an output of the third pair of amplifiers and an input of the second pair of amplifiers.

In one embodiment, each first stage variable capacitor is electrically connected in parallel with a resistor, and each second stage variable capacitor electrically coupled between an input and an output of an amplifier of the second pair is electrically connected in parallel with a resistor. These resistors may be fixed value resistors but, more preferably, they are variable resistors. In particular, it is preferable that the resistors connected in parallel with the variable capacitors of the second pair are variable resistors.

Typically, the third pair of amplifiers is electrically coupled to the second pair via one or more resistors.

The second stage may be directly electrically coupled to the first stage, but more preferably the second stage is electrically coupled to the first stage via one or more variable resistors.

In order to implement a Butterworth configuration with the reconfigurable filter, the controller may also be configurable to set the first and second stage capacitors to a third capacitance value and the first and second stage resistors to a third resistance value. By providing a configuration where the first and second stage capacitors are set to the same value, and where the first and second stage resistors are set to the same value, the filter can implement the same poles in the first and second stages (as required by a Butterworth filter implementation).

Typically, the amplifiers are operational amplifiers. For example, the amplifiers may be fully differential operational amplifiers (each having first and second inputs and first and second outputs). Alternatively, the amplifiers may be single ended operational amplifiers (having first and second inputs and only one output).

Where fully differential amplifiers are employed, the first input of each amplifier typically has a first electrical polarity and the second input of each amplifier typically has a second electrical polarity. In one embodiment, the first output of each amplifier has the second electrical polarity and the second output of each amplifier has the first electrical polarity.

In one embodiment, the first, second and third pairs of amplifiers each comprise a first amplifier and a second amplifier, the first input of the first amplifier being cross-coupled to the first output of the second amplifier, the second input of the first amplifier being cross-coupled to the second output of the second amplifier, the first input of the second amplifier being cross-coupled to the second output of the first amplifier and the second input of the second amplifier being cross-coupled to the first output of the first amplifier.

Preferably, the first input and the first output of each amplifier may be electrically coupled together via a variable capacitor and the second input and the second output of each amplifier may also be electrically coupled together via a variable capacitor. In this case, where the amplifier is in the first stage, the variable capacitor is typically a first stage variable capacitor and where the amplifier is in the second stage, the variable capacitor is typically a second stage variable capacitor.

Preferably, a first feedback path is provided between the first output of a first amplifier of the third pair and the second input of a first amplifier of the second pair; and a second feedback path is provided between the second output of the first amplifier of the third pair and the first input of the first amplifier of the second pair. Thus, the first and second feedback paths connect the outputs of the first amplifier of the third pair to the inputs of the first amplifier of the second pair of the same polarity.

Additionally or alternatively, a third feedback path is preferably provided between the first output of a second amplifier of the third pair and the second input of a second amplifier of the second pair; and a fourth feedback path is preferably provided between the second output of the second amplifier of the third pair and the first input of the second amplifier of the second pair. Thus, the third and fourth feedback paths connect the outputs of the second amplifier of the third pair to the inputs of the second amplifier of the second pair of the same polarity.

Typically, the amplifiers are implemented in CMOS.

Preferably, the controller is configurable to provide the filter with a polyphase frequency response.

Preferably, each amplifier is an inverting amplifier.

Preferably, the controller is also configurable to set the first and second stage variable resistors to an open circuit configuration. This allows the reconfigurable filter to be configured in a low pass configuration (as the open circuit configuration removes the cross coupling between the respective pairs of amplifiers).

The reconfigurable filter may comprise a plurality of second stages cascaded together. That is, the reconfigurable filter may be any desired order. For example, with one first stage and two second stages cascaded together, a fifth order filter may be implemented. Similarly, with one first stage and three second stages cascaded together, a seventh order filter may be implemented. In this case, the controller is configurable to set the third stage (and fourth and subsequent stages where applicable) variable resistors to different resistance values to the first and second stage variable resistance values and to set the third stage variable capacitors to different capacitance values to the first and second stage variable capacitance values. This allows the third stage (and subsequent stages) to implement different poles from the first and second stages (as required in a Chebyshev configuration).

Preferably, the second stages each have independently programmable Q-factors. This may be achieved by including variable resistors in parallel with the variable capacitors electrically coupled between the inputs and outputs of the amplifiers of the first and second pairs.

Preferably, the filter can be configured to provide a low pass or a band pass response.

Additionally or alternatively, the filter can be configured to provide a Butterworth type response or a Chebyshev type response.

Preferably, each first stage amplifier input is electrically connected to an external signal input via a respective variable resistor.

A second aspect of the disclosure provides a television or radio tuner integrated circuit comprising the reconfigurable electronic filter according

to the first aspect of the disclosure.

A third aspect of the disclosure provides a method of configuring a filter, the method comprising: a. providing a first stage having a first pair of amplifiers, each amplifier having an input and an output electrically coupled together via a respective first stage variable capacitor; b. electrically cross coupling the first pair of amplifiers via first stage variable resistors; c. providing a second stage having second and third pairs of amplifiers, each amplifier having an input and an output electrically coupled together via a respective second stage variable capacitor; d. electrically cross coupling the second and third pairs of amplifiers via second stage variable resistors; e. cascading the second and third pairs of amplifiers; f. setting the first stage capacitors to a first capacitor value and setting the second stage capacitors to a second capacitor value different from the first capacitor value; and g. setting the first stage variable resistors to a first resistance value and the second stage variable resistors to a second resistance value different from the first resistance value.

It will be understood that third and subsequent stages may be cascaded to the first and second stages.

BRIEF DESCRIPTION OF FIGURES

An embodiment of the disclosure will now be described, by way of example only, with reference to the drawings, in which: Figure 1 is a schematic block diagram of a television or radio tuner chip; Figure 2 is a circuit diagram of a third order reconfigurable electronic filter; Figures 3 and 4 are schematic circuit diagrams of programmable resistor and capacitor blocks; Figure 5 is a schematic circuit diagram of a seventh order reconfigurable filter; Figure 6 is a schematic diagram of the seventh order filter of Figure 5 with additional DC offset compensation circuitry; Figure 7 is a schematic circuit diagram of the filter of Figure 6; Figure 8 is a flow diagram of a DC offset reduction algorithm for the filter of Figures 6 and 7 in its low-pass configuration (Butterworth or Chebyshev); Figure 9 illustrates a successive approximation method; Figure 10 illustrates a long term DC offset tracking method; Figures ha to lid show the responses of the I and 0-channel output voltages of the filter of Figures 6 and 7 in the low-pass configuration (Butterworth or Chebyshev) to increasing values of the first and second correction signals; Figures 12a-12d show the responses of the I and 0-channel output voltages of the filter of Figures 6 and 7 in the band-pass Butterworth configuration to increasing values of the first and second correction signals; Figure 13 is a flow diagram of a DC offset reduction algorithm for the filter of Figures 6 and 7 in its band-pass Butterworth configuration; Figure 14 is a flow diagram of an alternative DC offset reduction algorithm for the filter of Figures 6 and 7 in its band-pass Butterworth configuration; Figures 15a-15d show the responses of the I and 0-channel output voltages of the filter of Figures 6 and 7 in the band-pass Chebyshev configuration to increasing values of the first and second correction signals; Figure 16 is a flow diagram of a DC offset reduction algorithm for the filter of Figures 6 and 7 in its band-pass Chebyshev configuration; Figure 17 is a schematic diagram of the filter of Figures 6 and 7 showing the switching circuitry between the outputs of the first and second filter channels and the offset reduction controller; and Figure 18 is a schematic circuit diagram of the switching circuitry of Figure 17.

DESCRIPTION OF SPECIFIC EMBODIMENTS

Figure 1 shows a television/radio tuner chip I comprising a low noise amplifier 5, a downconverter 10 and a reconfigurable electronic filter 100.

Baseband circuitry 20 is also provided, typically as a separate chip but optionally as part of the tuner chip 1. The reconfigurable filter 100 is connected between the downconverter 10 and the baseband circuitry 20.

The low noise amplifier 5 amplifies the detected signals 12 before the downconverter 10 downconverts the amplified television/radio signals 12.

The baseband circuitry 20 processes the downconverted signals into a suitable format for reproducing the payload of the television/radio signal.

The reconfigurable filter 100 is required to transmit wanted signals, while blocking unwanted signals.

The downconverter 10 may downconvert the received signal down to a near DC level. In this case, the reconfigurable filter is required to perform a low pass filtering function, transmitting low frequency (close to DC) signals and substantially blocking signals having frequencies significantly above DC. However, this downconversion mode is not suitable for all broadcast standards and many baseband demodulator chips require a higher input frequency. To comply with these requirements, the downconverter may alternatively downconvert the received signal to a frequency which is above DC (e.g. SM Hz). However, in this case, as well as producing the wanted signal, an unwanted image signal' is typically produced by the downconverter at a negative frequency value (e.g. - 5MHz). The filter 100 is therefore required to perform a band-pass filtering function, transmitting the wanted signal (at 5MHz) but blocking signals of other frequencies, including the image signal'.

Figure 2 is a schematic circuit diagram of the reconfigurable electronic filter 100. The filter 100 comprises a first order first stage 102 and a second order second stage 104 cascaded together to form a third order reconfigurable low-pass or band-pass filter. The reconfigurable filter 100 has (at least) four configurations: two low-pass configurations; and two band-pass configurations. More specifically, the filter may be configured to provide: a low-pass Butterworth response; a low-pass Chebyshev response; a band-pass Butterworth response; or a band-pass Chebyshev response. The low-pass configurations are optimised for (close to) DC downconversion, while the band-pass configurations are optimised for above DC downconversion. The appropriate filter type can be selected according to the optimal filtering requirements of the broadcast standard, and the interface architecture between the downconverter and baseband circuitry.

The first stage 102 comprises first and second substantially identical fully differential inverting operational amplifiers 106, 108 electrically coupled between upper and lower voltage rails. The outputs of each inverting amplifier are of the opposite polarity to the respective inputs. The first amplifier 106 has first (positive -which will be shortened to F' in the following description) and second (negative -which will be shortened to N' in the following description) inputs 110, 112 and first (N) and second (F) outputs 118, 120. The first (P) input 110 is electrically coupled to the first (N) output 118 via a first stage variable capacitor 126, while the second (N) input 112 is electrically coupled to the second (F) output 120 via another first stage variable capacitor 130. Similarly, the second amplifier 108 has first and second (F, N) inputs 114, 116 and first and second (N, F) outputs 122, 124. Again, the first (F) input 114 is electrically coupled to the first (N) output 122 via a first stage variable capacitor 128, while the second (N) input 116 is electrically coupled to the second (F) output 124 via another first stage variable capacitor 132. Identical fixed value resistors 133 are connected in parallel with the first stage variable capacitors 126, 128, 130, 132. It is noted that the capacitors are either connected between the positive (F) input and the negative (N) output or between the negative (N) input and the positive (F) output in each case.

The first and second differential amplifiers 106, 108 are cross coupled via four respective first stage variable resistors 134-140. In addition, two of the four cross-coupling paths are inverted. That is, there are two inverting cross-coupling paths: the first (P) input 110 of the first amplifier 106 is electrically connected to the first (N) output 122 of the second amplifier 108 via the first variable resistor 134, the second (N) input 112 of the first amplifier 106 is electrically connected to the second (P) output 124 of the second amplifier 108 via the second variable resistor 136; and two non-inverting cross-coupling paths: the first (P) input 114 of the second amplifier 108 is electrically connected to the second (F) output 120 of the first amplifier 106 via the third variable resistor 138 and the second (N) input 116 of the second amplifier 108 is electrically connected to the first (N) output 118 of the first amplifier 106 via the fourth variable resistor 140.

The cross-coupling is illustrated schematically in Figure 2 between the first and second amplifiers 106, 108.

Variable resistors 141 are provided at the first and second differential inputs 110-116 of the first and second amplifiers 106, 108.

The second stage 104 comprises third, fourth, fifth and sixth fully differential inverting amplifiers 150-156 electrically coupled between the upper and lower voltage rails. Again, the outputs of each inverting amplifier 150-1 56 are of the opposite polarity to the inputs. The amplifiers 150-156 each have first and second (F, N) inputs 158-172 and first and second (N, P) outputs 174-1 88 respectively. The first (F) inputs 158, 162 of the third and fourth amplifiers 150, 152 are electrically coupled to the first (N) outputs 174, 178 of said amplifiers via respective second stage variable capacitors 190, 192, while the second (N) inputs 160, 164 are also electrically coupled to the second (F) outputs 176, 180 via respective second stage variable capacitors 198, 200. Similarly, the first (F) inputs 166, 170 of the fifth and sixth amplifiers 154, 156 are electrically coupled to the first (N) outputs 182, 186 of said amplifiers via respective second stage variable capacitors 194, 196 while the second (N) inputs 168, 172 are also electrically coupled to the second (P) outputs 184, 188 via respective second stage variable capacitors 202, 204. Variable resistors 205 are connected in parallel with the second stage variable capacitors 190, 192, 198, 200 of the third and fourth amplifiers 150, 152. The fifth and sixth amplifiers act as integrators as no resistors are connected in parallel with their capacitors. It is again noted that the capacitors are either connected between the positive (P) input and the negative (N) output or between the negative (N) input and the positive (P) output in each case.

The third and fourth amplifiers 150, 152 are cross coupled via four respective second stage variable resistors 206-212. Again, two of the four cross-coupling paths are inverted. That is, there are two inverting cross-coupling paths: the first (F) input 158 of the third amplifier 150 is electrically connected to the first (N) output 178 of the fourth amplifier 152 via the first variable resistor 206, the second (N) input 160 of the third amplifier 150 is electrically connected to the second (P) output 180 of the fourth amplifier 152 via the second variable resistor 208; and two non-inverting cross-coupling paths: the first (F) input 162 of the fourth amplifier 152 is electrically connected to the second (P) output 176 of the third amplifier 150 via the third variable resistor 210 and the second (N) input 164 of the fourth amplifier 152 is electrically connected to the first (N) output 174 of the third amplifier 150 via the fourth variable resistor 212.

The cross-coupling is again illustrated schematically in Figure 2 between the third and fourth amplifiers.

Similarly, the fifth and sixth amplifiers 154, 156 are cross-coupled via four respective second stage variable resistors 214-220. Again, two of the four cross-coupling paths are inverted as above. The cross-coupling is once again illustrated schematically in Figure 2 between the fifth and sixth amplifiers.

The cross-coupled pairs of amplifiers 150, 152 and 154, 156 of the second stage are cascaded together to form a second order stage. The first (N) and second (P) outputs 174, 176 of the third amplifier 150 are connected to the first (P) and second (N) inputs 166, 168 respectively of the fifth amplifier 154 via identical fixed value resistors 221. Similarly, the first (N) and second (P) outputs 178, 180 of the fourth amplifier 152 are also connected to the first (F) and second (N) inputs 170, 172 respectively of the sixth amplifier 156 via fixed value resistors 221.

Respective identical fixed value resistors 223 are connected: in a first feedback path between the first (N) output 182 of the fifth amplifier 154 and the second (N) input 160 of the third amplifier 150; in a second feedback path between the second (F) output 184 of the fifth amplifier 154 and the first (F) input 158 of the third amplifier 150; in a third feedback path between the first (N) output 186 of the sixth amplifier 156 and the second (N) input 164 of the fourth amplifier 152; and in a fourth feedback path between the second (F) output 188 of the sixth amplifier 156 and the first (F) input 162 of the fourth amplifier 152.

The first and second stages are cascaded together by electrically coupling the first (N) and second (F) outputs 118, 120, 122, 124 of the first and second amplifiers 106, 108 to the first (F) and second (N) inputs 158, 160, 162, 164 of the third and fourth amplifiers 150, 152 via variable coupling resistors 222. The first, third and fifth amplifiers 106, 150, 1 54 form an in-phase channel ("I-channel") and the second, fourth and sixth amplifiers 108, 152, 156 form a quadrature channel ("Q-channel") of the filter 100.

The downconverter 10 provides the filter 100 with a first downconversion signal at the inputs 110, 112 of the first amplifier 106 (which forms the first amplifier of the I-channel) and a second downconverted signal 90° out of phase with the first downconverted signal at the inputs 114, 116 of the second amplifier 108 (which forms the first amplifier of the 0-channel).

It will be understood that the variable capacitors 126-132, 190-204 and resistors 134-141, 205-220, 222 described above are each independently variable/programmable (i.e. they can be varied/programmed such that they have different values).

The variable resistors 134-141, 205, 206-220, 222 and capacitors 126- 132, 198-204 described above are preferably implemented as programmable resistors and capacitors. This is illustrated in Figures 3 and 4. Taking each in turn, Figure 3 illustrates a programmable resistor block 300 comprising a controller 302 and a plurality of discrete resistors 304, the resistors being selectably connected in parallel between input and output rails 306, 308. The controller 302 can toggle each discrete resistor 304 between a connected position where said resistor is connected between the input and output rails 306, 308 and a disconnected position where said resistor is disconnected from the input and/or output rails 306, 308. The overall resistance of the resistor block 300 depends on how many resistors 304 are in their connected positions and how many are in their disconnected positions. It will be understood that any suitable variable resistor may be used in place of the programmable resistor blocks, such as, for example but not exclusively, triode region MOSFETs.

However, the programmable resistor blocks are preferred as the gains of the amplifier stages are typically determined by ratios of resistor values (see below). These ratios can be tightly controlled in the silicon manufacturing process used to form the programmable blocks.

Figure 4 illustrates a programmable capacitor block 400 comprising the same controller 302 as that used to control the programmable resistor block 300 (or optionally a separate controller), and a plurality of discrete capacitors 404, the capacitors 404 being selectably connected in parallel between input and output rails 406, 408. The controller 302 can toggle each discrete capacitor 404 between a connected position where said capacitor is connected between the input and output rails 406, 408 and a disconnected position where said capacitor is disconnected from the input and/or output rails 406, 408. The overall capacitance of the capacitor block 400 depends on how many capacitors 404 are in their connected positions and how many are in their disconnected positions.

The controller 302 can be used to reconfigure the filter between the four configurations mentioned above (low-pass/band-pass; Butterworth/Chebyshev).

Transfer Functions The low-pass and band-pass Butterworth and Chebyshev filter configurations can be designed starting from the same normalised transfer functions.

The normalised transfer function of the (first order) first stage 102 is as follows: G(s) = 1/(1+s) where s=jw; w = 2irf; and f is the frequency of the input signal.

The normalised transfer function of the (second order) second stage 104 is as follows: G(s) = 1/(1+(1/Q)sis2) where s=jw; w = 2irf; f is the frequency of the input signal; and Q is the 0 factor of the second order stage.

The normalised transfer function of the third order filter (formed by cascading the first and second stages 102, 104) is as follows: C(s) = 1I[(1 +s)(1 +(1/Q)s+s2)] where the parameters are as defined above.

These normalised transfer functions can be manipulated in different ways to implement the four filter configurations mentioned above using the reconfigurable filter 100. Each configuration is described individually in more detail below.

It is noted that, in each configuration, the fixed value resistors 133, 221, 223 are typically provided with identical resistance values.

Low Pass Configurations In both low pass configurations (Butterworth and Chebyshev), the controller 302 sets all cross-coupling resistor values Rxcoupiei and R couple_2 to open circuit. That is, all resistors 304 are disconnected from the input and/or output rails 306, 308. In this case, the I-channel and the 0-channel are decoupled from each other.

To achieve a low pass filter function, the parameter s' in the normalised transfer functions provided above is replaced with s=jw, where w can be scaled to achieve the required cut-off frequency. The resistance and capacitance values of the reconfigurable filter 100 required to achieve this cut-off frequency can be determined by a relationship derived from the transfer functions (see below for example). The parameter Q of a second order stage may be determined by the resistance relationship shown below (in equation 4).

As an example, the following equations may apply to the first order stage 102: Wcut-off = l/Rfb c_i (1) = -Rfb1/R11 (2) where, Wcutoff is the cut-off frequency of the filter A1 is thegain of thefirst stage; C_i is the capacitance of each of the variable capacitors 126-132 (which are provided with identical values in the Butterworth configuration); Rfbl is the resistance of the fixed resistors 133 connected in parallel with the variable capacitors; and R1 is the resistance value of the variable resistors 141 provided at the first and second inputs of the amplifiers 106, 108.

The gain of the first stage of the filter can be set by choosing appropriate values of the fixed resistors 133 (Rfbl) and variable resistors 141 (R1) in accordance with the above equations.

Similarly, as the resistors 221, 223 have fixed resistance values, the properties of the second stage can be (re)configu red by altering the values of the capacitors 190-204, the variable resistors 205 in parallel with the second stage variable capacitors 190, 192, 198, 200 of the third and fourth amplifiers 150, 152, and the variable coupling resistors 222 between the first and second cross-coupled amplifier pairs of the second stage. More specifically, the following equations apply: Wcuj-off = I /Rfb2 C_2 (3) Q = Rq/Rfb2 (4) = -Rfb2/R1p2 (5) where, Wcut-off is the cut-off frequency of the filter (which will be up-shifted in accordance with the centre frequency wcentre); A2 is the gain of the second stage; C_2 is the capacitance of the variable capacitors 190-204 (which are provided with identical values in the Butterworth configuration); o is the 0 factor of the second stage; Rq is the resistance of the variable resistor 205 connected in parallel with the variable capacitors 190, 192, 198, 200 of the third and fourth amplifiers; Rfb2 is the resistance of the fixed resistors 223 connected between the outputs of the fifth and sixth amplifiers and the inputs of the third and fourth amplifiers respectively; and R2 is the resistance value of the variable resistors 222 provided between the first and second stages.

Butterworth implementation (low-pass) Butterworth filters typically require different filter stages to implement the same poles (and the same centre frequency), but each second order stage should have a different Q factor. It will be understood that, in this embodiment, there is only one second order stage 104 so the Q factor criterion is not relevant. However, when implementing higher order filters, this needs to be taken into consideration.

In order to implement the same poles in the first and second stages 102, 104, the controller sets all of the variable capacitors of the first and second stages C_i, C_2 to the same value, which is determined by the desired cut-off frequency and the above equations.

It is noted that the Butterworth filter is more area efficient than a Chebyshev filter, so it is possible to achieve a narrower BW with the Butterworth configuration of the reconfigurable filter. This makes the Butterworth implementation more suitable than the Chebyshev for some applications.

Chebyshev implementation 00w-pass) Chebyshev filters require each filter stage to implement different poles, and each second order stage should have a different Q-factor. Again, it will be understood that, in this embodiment, there is only one second order stage 104 so the Q factor criterion is not relevant. However, when implementing higher order filters, this needs to be taken into consideration.

In order to implement different poles in the first and second stages 102, 104, the controller 302 sets all the variable capacitors 126-1 32 of the first stage to a first capacitance value C_I and all the variable capacitors 190- 204 of the second stage to a second capacitance value C_2 different from the first capacitance value C_2.

It will be understood that the Chebyshev filter typically has a sharper roll-off than the Butterworth filter and so is more suited to some applications.

Filter programmability In order to implement a reconfigurable Butterworth/Chebyshev low-pass filter, the following capacitance and resistance values should therefore be variable/programmable (assuming that the feedback resistance values Rfbl & Rfb2 remain fixed): C_I, C_2, Rq, R1 & R_2.

In both Butterworth and Chebyshev implementations of the low-pass filter, the filter transmits DC signals and substantially blocks all signals above the cut-off frequency. The filtered output signals of the I and Q channels are then taken from the differential outputs 182, 184 of the fifth amplifier and 186, 188 of the sixth amplifier and passed to the baseband circuitry 20.

As indicated above, the low pass configuration is used where the downconverter fully downconverts the received television/radio signals to around DC (and where there are thus no image signals to be suppressed).

Band Pass Configurations In order to achieve a band-pass (polyphase) response, it is necessary to cross-couple the I and Q channels of the filter 100. That is, the cross-coupling resistors are set to non-open circuit configurations (at least one resistor in each programmable block being connected between the respective input and output rails).

The band-pass filter can be designed using the normalised transfer functions provided above. As the band-pass filter being implemented is complex (i.e. a complex filter as opposed to a real filter) the band-pass response is achieved by shifting the poles of a low-pass filter design upwards on the imaginary axis of the pole diagram. To achieve this complex band pass filter function, the parameter s' in the normalised transfer functions for the first and second stages 102, 104 is replaced with 5j(WWcen) where Wcen is the centre frequency of the band-pass filter. By substituting s=J(co-cocen), the low-pass filter response is shifted up in frequency by the centre frequency.

As above, the centre and cut-off frequencies may be determined by relationships between capacitance and resistance values (see below).

Similarly, the parameter 0 of the second order stage 104 may be determined by a relationship of resistance values (see below).

The required pole positions (and 0 values for higher order filters) of the band-pass filter are determined by the filter type (Butterworth or Chebyshev) and the desired cut-off and centre frequencies.

Butterworth Implementation (Band-pass) The properties of the filter 100 can be (re)configu red by the controller 302 by altering the values of the variable capacitors and the variable resistors.

In the band-pass Butterworth configuration, the variable capacitors 126- 132 and 190-204 are all provided with identical values. Also, the variable cross-coupling resistors 134-140 and 206-220 are all provided with identical values. This is explained in more detail below.

As the resistors 133 have fixed resistance values, the properties of the first stage 102 are reconfigured by altering the values of the variable capacitors 126-1 32, the variable cross-coupling resistors 134-1 40 and the variable resistors 141.

More specifically, the following equations apply to the first stage 102: Wcentre = I /Rx-cou pie_i c_I (6) Wcut-off = I/Rfb c_i (7) Ai = -Rfb1/RI1 (8) where, Wcentre is the centre frequency of the filter; Wcutoff is the cut-off frequency of the filter; A1 is the gain of the first stage; Rxcoupiei is the resistance of the variable cross coupling resistors 134-i 40 (which are provided with identical values in the Butterworth configuration) of the first stage; c_i is the capacitance of each of the variable capacitors i26-i32 (which are provided with identical values in the Butterworth configuration); Rfbl is the resistance of the fixed resistors 133 connected in parallel with the variable capacitors; and R1 is the resistance value of the variable resistors 141 provided at the first and second inputs of the amplifiers 106, 108.

The gain of the first stage of the Butterworth filter can be set by choosing appropriate values of fixed resistors 133 (Rfbl) and variable resistors 141 (R1) in accordance with the above equations.

Similarly, as the resistors 221, 223 have fixed resistance values, the properties of the second stage can be (re)configu red by altering the values of the capacitors 190-204, the variable cross-coupling resistors 206-220, the variable resistors 205 in parallel with the second stage variable capacitors 190, 192, 198, 200 of the third and fourth amplifiers 150, 152, and the variable coupling resistors 222 between the first and second cross-coupled amplifier pairs of the second stage. More specifically, the following equations apply: = I IRx-coupje 2 C_2 (9) Wcut-off = I IRi C2 (1 0) Q = Rq/Rfb_2 (11) = -Rfb2/R2 (1 2) where, Wcentre is the centre frequency of the filter; Wcutoff is the cut-off frequency of the filter (which will be up-shifted in accordance with the centre frequency wcentre); A2 is the gain of the second stage; Rxcouple2 is the resistance of the variable cross coupling resistors 206-220 (which are provided with identical values in the Butterworth configuration); C_2 is the capacitance of the variable capacitors 190-204 (which are provided with identical values in the Butterworth configuration); Q is the Q factor of the second stage; Rq is the resistance of the variable resistor 205 connected in parallel with the variable capacitors 190, 192, 198, 200 of the third and fourth amplifiers; Rfb2 is the resistance of the fixed resistors 223 connected between the outputs of the fifth and sixth amplifiers and the inputs of the third and fourth amplifiers respectively; and R2 is the resistance value of the variable resistors 222 provided between the first and second stages.

The passband of the upshifted Butterworth filter is above DC, and so blocks negative frequency signals. It is therefore suitable for suppressing the image signals' created in above-DC downconversion. It is also noted that the Butterworth filter is more area efficient than a Chebyshev filter, so it is possible to achieve a narrower BW with the Butterworth configuration of the reconfigurable filter. This makes the Butterworth implementation more suitable for some applications.

As mentioned above, Butterworth filters typically require different filter stages to implement the same poles (and the same centre frequency), but each second order stage should have a different Q factor (it will be understood that this applies to higher order Butterworth filters but, in this embodiment, the first stage is a first order stage so does not have a Q factor). Therefore, in order to implement the same poles in the first and second stages, the controller sets all of the variable capacitors of the first and second stages C_i, C_2 and all of the variable cross-coupling resistors Rx..coupiei and RxcoupIe_2 of the first and second stages to the same capacitance and resistance values respectively, thus providing each stage with the same poles and identical centre frequencies. These capacitance and resistance values are determined by the desired centre and cut-off frequencies of the filter and the equations given above.

In addition, the Q factor of the second stage is set appropriately by controlling the values of Rq (the resistance of the variable resistor connected in parallel with the variable capacitors 190, 192, 198, 200 of the third and fourth amplifiers 150, 152) and the resistance value of the fixed resistors 223 (Rfb2).

The gain of the second stage can be set by choosing appropriate values of fixed resistors 223 (RIb 2) and variable resistors 222 (R12) in accordance with the above equations.

Both the first and second stages should also implement the same cut-off frequency values, Wcutoff and so Rfbl and Rfb2 should be chosen accordingly.

In an exemplary embodiment, for a cut-off frequency of 3.8MHz and a centre frequency of 4.57MHz, the following values can be selected: Rx-coupiei and Rx-couple2 = 8.1 3kC) C_I and C_2 =4.188pF; Rfbl, Rq, Rfb2 10k0 = lOkO; R2 = lOkO; R1 and R12 can be scaled in accordance with the desired gain.

The Q factor of the second stage is 1 as Rq = Rfb_2.

Bandpass Configuration: Chebyshev The above equations (6) to (12) also apply to the first and second stages of the Chebyshev configuration. Chebyshev filters typically require each filter stage to implement different poles and different Q factors (it will be understood that this applies to higher order Chebyshev filters but, in this embodiment, the first stage is a first order stage so does not have a 0 factor). Therefore, to implement the Chebyshev configuration of the reconfigurable filter 100, the controller 302 sets all the variable capacitors 126-132 of the first stage to a first capacitance value C_i and all the variable capacitors 190-204 of the second stage to a second capacitance value C_2 different from the first capacitance value C_2. Although the capacitance values C_i and C_2 are different, it is necessary for each stage of the filter to implement the same centre frequency value Wcentre.

Therefore, the values of the variable cross-coupling resistors 134-i40 of the first stage and the variable cross-coupling resistors 206-220 of the iO second stage (on which the centre frequency Wcentre also depends -see equations (i) and (4) above) must also be different. That is, the controller sets the first variable cross-coupling resistors 134-140 to a first resistance value Rxcoupiei and the second variable cross-coupling resistors 206-220 to a second resistance value Rx-coupie2 different from the first resistance iS value Rxcoupiei. The product of the first capacitance value C_i and the first resistance Rx-coupiei should equal the product of the second capacitance value C_2 and the second resistance Rxcoup1e2 so that both stages implement the same centre frequency Wcentre.

Both the first and second stages should also implement the same cut-off frequency values, Wcutoff, and so Rfbl and Rfb2 should be chosen accordingly.

The passband of the upshifted Chebyshev filter is above DC, and so blocks negative frequency signals. It is therefore suitable for suppressing the image signals' created in above-DC downconversion. However, the Chebyshev filter typically has a sharper roll-off than the Butterworth filter and so is more suited to some applications.

In an exemplary embodiment, for a cut-off frequency of 3.8MHz, a centre frequency of 4.57MHz and a 0.1dB ripple, the following values can be selected: Rx-coupie_i = 8.06k0 c_I = 4.32pF Rx-coupie_2 = 10.81 kO c _2 =3.22pF; Rfb2 lOkO; Rfbl = lOkO; Rq10.81k0; = lOkO; = lOkO; R1 and R12 can be scaled in accordance with the desired gain and equations (3) and (7) above.

The Q factor of the second stage is 1 as Rq = Rfb_2.

Filter programmability As can be seen from the equations above, in order to implement a reconfigurable Butterworth or chebyshev bandpass filter, the following parameters should be programmable (assuming that the feedback resistance values, Rfbl& Rfb2 remain fixed): Rx-coupie_i, c_i, Rx-couple_2, _2, Rq, R1 & In particular, to implement a Chebyshev configuration using different pole frequencies in each stage, C_I and C_2 must be allowed to take different values and as a result the resistors Rx-coupie 1 & Rx-couple2 must be allowed to take different values in order to maintain the required centre frequency in each stage.

Seventh Order Filter It will be understood that the above design may be scaled up to any order of filter. For example, Figure 5 shows a seventh order, four stage filter 500. The four stage filter 500 comprises the first and second stages 102, 104 described above and a further two second order second stages 502, 503 cascaded to the output of the original second stage 104. The four stage filter 500 works in substantially the same way as the two stage filter described above. In the Butterworth implementation, the controller sets the variable capacitors in all four stages to identical capacitance values (determined by the second order stage equations 4-7 provided above) and the cross-coupling variable resistors to identical resistance values. This provides each stage with the same poles and the same centre frequencies. However, the controller sets each second order stage 104, 502, 503 to have different values for Rq so that each stage has a different Q factor.

In the Chebyshev implementation of the four stage filter 500, the controller sets the variable capacitors of the four stages 102, 104, 502 and 503 to first, second, third and fourth capacitance values respectively. The first, second, third and fourth capacitance values are different from each other so that each stage implements a different filter pole. The controller also sets the variable cross-coupling resistors of second stages 102, 104, 502, 503 to first, second, third and fourth resistance values respectively. The first, second, third and fourth resistance values are different from each other such that the product of the first resistance value and the first capacitance value substantially equals the product of the second resistance value and the second capacitance value, the product of the third capacitance value and the third resistance value and the product of the fourth capacitance value and the fourth resistance value (to implement the same centre frequency with each stage). In addition, the controller 302 sets the values of Rq to different values for the three second stages to give them different Q factors as required.

Thus, the fact that the resistors 134-140, 206-220 and the capacitors 126- 132, 190-204 have resistance and capacitance values which are independently variable (in this case independently programmable) allows different poles to be implemented in each stage as required by the Chebyshev configuration. The variable (programmable) resistors 205 also allow the Q-factors of each second order stage to be independently varied as required.

It will be understood that the filters 100, 500 described above have frequency responses which can be varied in each configuration. That is, the frequency responses can be altered by varying the capacitance values of the programmable capacitors. It is advantageous to vary the capacitance values and keep the resistance values fixed to vary the frequency response of a particular design to keep the noise figure constant.

It will also be understood that, although the filters described above are implemented with fully differential operational amplifiers, the filters could equally be implemented with single ended operational amplifiers.

However, in this case, an additional inverting amplifier stage may be necessary at the output of each second order stage. This is because, as single ended operational amplifiers only have a single output node, it is not possible to cross over the feedback connections as is done in the fully differential implementations described above. Taking the second order stage 104 in Figure 2 as an illustrative example, it is possible to connect the first (N) output 182 of the fully differential amplifier 154 to the second (N) input of the fully differential of the fully differential amplifier 150 and to connect the second (P) output 184 of the fully differential amplifier 154 to the first (F) input of the fully differential amplifier 150. Thus, the outputs of amplifier 154 are connected to the inputs of amplifier 150 of the same polarity. However, it is not possible to "cross over" the feedback connections in this way when the filter is implemented with single ended operational amplifiers. As such, an extra inverting stage is necessary for each second order stage implemented with single ended operational amplifiers. The additional inverting stage allows the outputs of the third pair of amplifiers 154, 156 and the inputs of the second pair of amplifiers 150, 152 (to which they are connected) to be electrically coupled with signals of the same polarity.

Finally, it will be understood that, in the fully differential implementations described above, all of the P and N inputs and outputs could be implemented with opposite polarities to achieve the same effect.

DC Offset Compensation Typically the amplifiers 106-1 08, 150-1 56 are implemented in CMOS. Due to mismatches in the internal transistors of the amplifiers caused by manufacturing tolerances, each amplifier typically provides an unwanted input DC offset. In addition, a DC offset may be expected at the output of the downconverter stage, which must be removed. If, for example in the seventh order four stage embodiment of Figure 5, the overall gain of the filter is high (e.g. 60dB), a lmV input DC offset at the input to the first stage will lead to a large (e.g. IV) output offset. In one embodiment, the voltage difference between the upper and lower voltage rails may be I.5V.

A IV output offset may therefore tie the filter output voltage to the upper (or lower) supply voltage rail, which would make the filter unusable.

Here, two complementary approaches are described which can be applied to correct the DC offset: * Initial DC offset correction. Here, the received signal (e.g. TV/radio signal) is disconnected (disabled) from the downconverter (typically by disabling the signal path through the low noise amplifier) so that no varying signal is present. An initial calibration algorithm is then applied to correct the DC offset on the I and Q-channel outputs caused by the individual amplifier input offsets. The output from the downconverter should remain connected to the filter inputs so that the downconverter output offset can also be accounted for; * Ongoing DC offset correction (long term tracking) which operates in Is the presence of received signals downconverted by the downconverter (i.e. the received TV/radio signals are reconnected to the downconverter inputs). Here, the offset correction input signals calculated during the initial DC offset correction are incremented and/or decremented to compensate for changes in gain and offset through the filter 100 (which may for example be caused by temperature variations).

Each of these approaches will be explained with reference to the seventh order filter 500 shown in Figures 5, 6 and 7 (and Figures 17 and 18 -see below). However, it will be understood that they are equally applicable to other orders of filter (in particular 3 order and above).

Figure 6 is a schematic diagram of the 7th order filter of Figure 5. Each stage 102, 104, 502, 503 is represented by a pair of amplifier symbols, one for each I-channel stage and one for each Q-channel stage. It will be understood that, even though each stage is represented by the same symbol, the first stage is a first order stage and the second, third and fourth stages are second order stages (as shown in Figures 5 and 7) in this example. Also shown in Figure 6 is respective I-channel and 0-channel DC offset reduction circuitry.

As also shown in Figure 7, the I and 0-channel DC offset reduction circuitry comprises I and 0-channel comparators 554, 556, a digital controller 557 comprising I and 0-channel digital control circuitry 558, 560, and I and 0-channel 10-bit Digital to Analogue Converters 562, 564 (IDAC and ODAC). Note that higher or lower resolution DACs may alternatively be employed. Note also that the cross-coupling paths, resistors and capacitors have been omitted from Figure 6 for clarity.

The I-channel output is taken from the differential outputs of the furthest right amplifier 570 in that channel (i.e. the outputs of the second I-channel amplifier 570 of the fourth stage 503). Similarly, the 0-channel output is taken from the differential outputs of the furthest right amplifier 572 in that channel (i.e. the outputs of the second Q-channel amplifier 572 of the fourth stage 503). The differential I-channel outputs are input to the respective inputs of the I-channel comparator 554, while the differential 0-channel outputs are input to the respective inputs of the 0-channel comparator 556. The I-channel comparator 554 compares the P and N outputs of the I-channel, outputting a digital 1' if the P output is greater and a digital 0' if the N output is greater. Hysteresis is applied within the comparator to prevent the output of the comparator from toggling between 0' and 1' when the inputs are close in value. The 0-channel comparator 556 compares the P and N outputs of the 0-channel, again outputting a digital 1' if the P output is greater and a digital 0' if the N output is greater.

Hysteresis is again applied. The outputs of the I and 0-channel comparators 554, 556 are electrically connected to inputs of the respective I and 0-channel digital control circuitry 558, 560 of the controller 557.

An output of the I-channel digital control circuitry 558 is electrically connected to an input of the IDAC 562, while an output of the 0-channel digital control circuitry 560 is electrically connected to an input of the QDAC 564. The IDAC 562 and QDAC 564 each have two outputs of opposite polarity. The two outputs of the IDAC 562 are connected to two respective I-channel DC offset correction inputs 574, 576 (see Figure 7) which are electrically connected to the respective inputs of the first I-channel amplifier 150 of the second stage 104. Similarly, the two outputs of the ODAC 564 are electrically connected to the two 0-channel DC offset correction inputs 580, 582 respectively, which are in turn electrically connected to the respective inputs of the first 0-channel amplifier 152 of the second stage 104. The controller 557 and the DACs 562, 564 are provided to inject correction signals to the offset correction inputs of I and O channels.

As shown in Figure 7, fixed value resistors 594-597 are provided between the DACs 562, 564 and the respective inputs 574, 576, 580, 582.

Optionally a wide swing amplifier may be provided between the outputs of the amplifiers 570, 572 and the comparators 554, 556.

The initial DC offset correction is applied when the chip is switched on (or awoken from a sleep' mode, or optionally at the user's request). Different compensation algorithms may be implemented depending on which of the (at least) four configurations the filter 100 is in. Each compensation algorithm is described in detail below.

Low pass filter (Butterworth and Chebvshev) When the filter is configured in the low pass filter configuration (in either the Butterworth or Chebyshev configuration), the cross-coupling between the I and 0-channels is open circuited (i.e. disconnected). Therefore, DC offsets in the I and 0-channels can be corrected separately. As the procedures used for the I and 0-channels are substantially identical, only the procedure for the I-channel will be described here. However, it will be understood that an equivalent procedure may be applied to the Q-channel.

The low pass filter DC offset compensation algorithm is summarised in the flow diagram of Figure 8. Firstly, in step 600, the filter is put into calibration mode by disabling the received (input) signal to the low noise amplifier (note that the output of the downconverter remains connected to the filter channel inputs). Next, in step 602, an initial DC offset compensation algorithm is applied. Note that the initial DC offset compensation algorithm can be applied to the I and 0-channels simultaneously as the cross coupling between them is disabled. Following the initial DC offset compensation, an ongoing longer term DC offset compensation algorithm is applied in step 604. Finally, while the longer term DC offset compensation algorithm is being applied, the input signal to the low noise amplifier 5 is enabled in step 606. This is explained in more detail below, starting with the initial DC offset compensation algorithm applied in step 602.

Initially, the controller 557 sets the output currents of the IDAC 562 (and the ODAC 564 whose output does not affect the I-channel DC offset compensation in this configuration) to zero. With no input DC offset signal applied to the I-channel, the outputs of the amplifier 570 depend only on the DC offsets of the amplifiers in the I-channel and the output offset of the downconverter. The offsets of each amplifier will be amplified to different levels, depending on the number of amplifiers between said each amplifier and the I-channel output (and the respective gains of the I-channel amplifiers). The input offsets of earlier amplifiers will be amplified more than the input offsets of later amplifiers in the channel.

As explained above, the comparator 554 compares the P and N outputs of the differential amplifier 570. If the P output is greater than the N output, the comparator outputs a digital 1', but if the N output is greater than the N output, the comparator outputs a digital 0'. This digital 1' or 0' is input to the I-channel control circuitry 558 of the controller 557. A control loop inside the controller 557 integrates the signal output by the comparator 554 over an adjustable measurement window to average out hysteresis and noise. Once the measurement window has expired, a decision is made to either increment or decrement the offset correction current signal output by the IDAC 562 into the DC offset correction inputs 574, 576.

Each 10-bit DAC 562, 564 has 16 possible coarse current ranges, each coarse current range being spanned by 64 fine resolution current steps.

The coarse current range is determined by a coarse current code comprising the first four most significant bits of the respective DAC and the fine current steps are determined by a fine tuning code comprising the six least significant bits of the DAC. The DAC outputs an analogue DC signal whose amplitude is dependent on the values of these 10 bits. The most significant bit (MSB) of each DAC determines the polarity of the coarse current range, while the sixth most significant bit determines the polarity of the fine current steps. It will be assumed that binary 0' means a negative polarity, while a binary 1' means positive polarity. However, any other suitable convention may be employed. It will be appreciated that the exact distribution and resolution of the binary control is not essential and that the proposed approach may be adapted to suit the DAC resolution employed/required.

The DC offset correction current signal required to cancel out the effects of the amplifier DC offsets in the I-channel is calculated by employing a binary search algorithm (although it will be appreciated that a non-binary search algorithm could alternatively be employed). Firstly, the IDAC bits are all set to digital 0'. This sets the output of the IDAC to the smallest (negative) coarse current range. This causes the IDAC to generate a (negative) current which is injected to the offset correction inputs 574, 576 of the amplifier 150 (the first amplifier of the second amplifier stage 104).

The injection of this DC offset correction signal causes the effect of the I-channel DC offsets to either be reduced or increased at the outputs of the I-channel (i.e. the outputs of amplifier 570). The I-channel DC offset correction signal is then varied in accordance with the output voltages of the I-channel. More specifically, if the application of the DC offset correction signal causes the output signal of the comparator to change sign, the correct coarse current range has been found and the fine tuning code is varied in accordance with a successive approximation algorithm (see below). If the application of the DC offset correction signal does not cause the output signal of the comparator to change sign, the fine tuning code is switched from its minimum value (all U's) to its maximum value (all l's) while keeping the coarse current code constant. If the injection of this new DC offset correction signal causes the output signal of the comparator to change sign, the correct coarse current range has been found.

If neither DC offset correction signal causes the output signal of the comparator to change sign, the controller cycles through the 16 coarse ranges by incrementing the coarse current code and repeating the above process until the correct coarse current range has been found.

Once the correct coarse current range has been found, the controller employs a suitable algorithm to determine a fine tuning code which minimises the effects of the I-channel amplifier DC offsets on the I-channel output (i.e. brings the I-channel output voltage within an acceptable range of the mid-rail voltage). For example, the controller may cycle through the 64 possible values of the fine tuning code until the output of the comparator changes sign again. However, more preferably, the controller implements a successive approximation algorithm. That is, the most significant bit of the fine tuning code is toggled between 1' and 0' and the rest of the fine tuning code bits are set to 0'. If the comparator output changes sign when that bit is set to 1', then that bit is set to 1'; otherwise, that bit is set to 0'. Next, the second most significant bit of the fine tuning code is toggled between 1' and 0'. If the comparator output changes sign when that bit is set to 1', that bit is set to 1'; otherwise that bit is set to 0'.

This process is continued until all the bits are set to 1' or 0', and the output voltage of the I-channel is within a predetermined acceptable voltage range of the mid-rail (common mode) level. Alternatively, the successive approximation method may be halted when the I-channel output is brought within the predetermined acceptable range from the common mode level, the remaining bits being set to 0'. The successive approximation method is much quicker and less power hungry than cycling through all 64 possible combinations of the fine tuning code as fewer combinations need to be tested.

The successive approximation method is illustrated by Figure 9, which shows how the output voltages 590, 592 of the P and N outputs of the I-channel vary as the least significant six bits are set. Each transition in output voltage value in Figure 9 occurs when one of the least significant six bits is set to 1'. As shown, as a result of the initial DC offset correction, the output voltages 590, 592 of the I-channel converge on the mid-rail common mode level to provide a maximum possible voltage swing for the filtered, downconverted signals.

As indicated above, after the above initiation algorithm has been completed, the longer term ongoing DC offset correction is implemented in step 604. This is run when the filter 500 is being used to filter signals output by the downconverter 10. In this case, the output of the comparator 554 is input to a control loop comprising an averaging filter, provided as part of the I-channel offset reduction circuitry 558. The averaging filter, which is typically implemented using digital signal processing, has a large time constant so that the signals being decoded are averaged out, the output of the averaging filter showing only the effect of any remaining DC offset which has not yet been corrected (e.g. due to temperature effects).

If a DC offset appears in the averaged signal, the controller instructs the IDAC to increment or decrement the fine tuning code so as to reduce the effects of the DC offsets. This is illustrated in Figure 10 which shows how the output voltages 590, 592 of the I-channel vary with time under the influence of the longer term ongoing DC offset correction. As shown, the output voltages converge at the mid-rail common mode level. This ensures that the correct DC offset correction signal is maintained in the long term and that it is not subject to drift (which may be caused by temperature changes for example).

It is noted that, if the DC offset is larger than the range of the fine tuning code, the control algorithm will allow the offset correction to move to the adjacent range. Alternatively, the initiation sequence can be re-run to recalculate the DC offset correction signal.

Finally, while the longer term DC offset compensation algorithm is running, the input signal to the low noise amplifier 5 is enabled as explained above.

It will be understood that, as the cross coupling between the I and Q-channels is disconnected in the low-pass configurations, a change in the offset correction current applied by the IDAC 562 does not affect the output of the Q-channel and vice versa. This is shown graphically in Figures lIb and lic, where the output levels remain flat despite an increase in the I and Q-channel offset correction signals respectively.

As also shown in Figures 11 a and 11 d for completeness (and as explained above), an increase in the I-channel correction current output by the IDAC causes the I-channel output DC level to increase and similarly the Q-channel output DC level increases with an increase in the Q-channel correction current output by the QDAC.

It is noted that, for the low pass configuration, even if no initial DC offset correction is run, the long term DC offset tracking will eventually correct for the DC offsets present -however this would take much longer without the (faster) successive approximation routine.

Band-pass (NZIF) Conficjurations: DC offset compensation Unlike the low pass configuration, the I and Q-channels are cross coupled in the band-pass configurations (in both Butterworth and Chebyshev configurations). Therefore, in order to correct for the DC offsets, at least one channel must be calibrated while considering the effects of the other channel. As explained below, this means that modified DC offset compensation algorithms are required.

It is noted that, when the filter 500 is configured in one of the band-pass modes (Butterworth or Chebyshev), it will inherently filter out a portion of the DC offset signal (since DC signals will fall into the stop-band of the filter). This means that at the output of the filter, the DC offsets may appear small, but at the earlier stages of the filter its impact may still be significant.

In addition, unlike the low pass filter case, the long term DC offset tracking will not compensate for DC offsets unless the initial DC offset compensation algorithm has been run. Without this initial calibration, the long term tracking may diverge from the required setting, making the filter unusable.

It has also been found that different DC offset compensation algorithms may be required for the Butterworth and Chebyshev band-pass configurations. These are explained below.

Butterworth configuration (NZIF) As in the low pass configuration, the I-channel output signal is directly proportional to the I-channel DC offset correction signal and the 0-channel output signal is directly proportional to the 0-channel DC offset correction signal (see Figures 12a and 12d respectively) for the Butterworth configuration. However, due to the cross coupling between the I and 0 channels, the I-channel amplifier offsets affect the 0-channel outputs and vice versa. More specifically, as shown in Figure 12b, the 0-channel output is inversely proportional to the I-channel offset correction signal input to the I-channel offset correction inputs. In addition, as shown in Figure 12c, the I-channel output is directly proportional to the 0-channel offset correction signal input to the 0-channel offset correction inputs.

This interdependence means that it is not possible to run the initial DC offset correction algorithm on the I and 0-channels simultaneously with full cross-coupling enabled, as the two correction algorithms will conflict with each other (potentially causing oscillation). Instead, the initial DC offset correction algorithm may be applied to the I and 0-channels in separate operations.

Two alternative DC offset compensation algorithms are presented for the band-pass Butterworth configuration. Figure 13 summarises the first of these. First, in step 610, the filter is put into calibration mode by disabling the input signal to the low noise amplifier as above. Next, in step 612, initial DC offset correction is applied to the 0-channel with the I-channel correction signal output by the IDAC kept constant (at zero, typically, or alternatively at a non-zero value) by the controller 557. The initial DC offset correction algorithm applied is substantially identical to that described above with respect to the low pass configuration -that is, the 0-channel correction signal output by the ODAC is varied by the controller 557 (in accordance with the binary search and successive approximation algorithms) until the output voltage of the 0-channel is within a predetermined acceptable range of the mid-rail (common mode) level.

When the required offset is determined, bringing the 0-channel output voltage to within an acceptable voltage range from the mid-rail common mode level, the 0-channel offset correction setting is stored. Then, in step 614, the initial DC offset correction is applied to the I-channel with the 0-channel correction signal kept constant at the stored value determined during the 0-channel initial correction -that is, the I-channel correction signal output by the IDAC is varied by the controller 557 until the output voltage of the I-channel is within a predetermined acceptable range of the mid-rail (common mode) level. Long term tracking is then enabled in step 616 before the input signal to the low noise amplifier 5 is enabled in step 618.

It is noted that, for the band-pass configurations, the long term tracking typically involves inputting the outputs of both comparators 554, 556 into an averaging filter (typically implemented using digital signal processing), having a large time constant. As above, the signals being decoded are averaged out, the outputs of the averaging filter showing only the effects of any remaining DC offsets which have not yet been corrected (e.g. due to temperature effects). If DC offsets appear in the averaged signals, the controller instructs the IDAC and the ODAC to increment or decrement the fine tuning codes so as to reduce the effects of the DC offsets. Again, if the DC offsets are larger than the range of the fine tuning code, the control algorithm will allow the offset corrections to move to the adjacent ranges.

Alternatively, the initiation sequence can be re-run to recalculate the DC offset correction signal.

This algorithm assumes that both cross-coupling paths are enabled in each amplifier stage before the algorithm is implemented (i.e. the outputs of the 0-channel amplifiers are electrically coupled to the inputs of the I-channel amplifiers and vice versa). If the cross-coupling paths are not enabled, then this should be done before the above algorithm is implemented.

By comparing Figure 12a with Figure 12c and Figure 12b with 12d, the interdependence of the I and 0-channel outputs on the 0 and I channel offset correction signals respectively is weaker than each channel's dependence on its own correction signal. Therefore, although the 0-channel output will change in response to the I-channel correction signal during the initial DC offset correction, its variation is small enough to be adequately and reliably reduced by the longer term DC offset tracking.

Figure 14 describes the second (alternative) DC offset compensation algorithm for the Butterworth configuration. In this case, the filter is initially put into calibration mode by disabling the input signal to the low noise amplifier 5 in step 620 as above. Next, in step 622, the outputs of the I- channel amplifiers are electrically decoupled from the inputs of the 0-channel amplifiers (i.e. the cross-coupling resistors are set to their open circuit configurations by controller 302). The cross-coupling paths from the outputs of the 0-channel amplifiers to the inputs of the I-channel amplifiers may optionally be left enabled (or alternatively, these cross coupling paths may also be electrically decoupled). Then, in step 624, the initial DC offset compensation is applied to the 0-channel with the I-channel correction signal optionally kept constant (at zero). Note that, as the cross-coupling from the outputs of the I-channel amplifiers to the inputs of the 0-channel amplifiers has been electrically decoupled, the I-channel correction signal does not necessarily have to be kept constant in this case.

The initial DC offset correction algorithm applied is again substantially identical to that described above. When the 0-channel output voltage is brought to within an acceptable voltage range from the mid-rail common mode level, the required 0-channel offset correction signal is stored. In a next step 626, the cross-coupling paths from the outputs of the I-channel amplifiers to the inputs of the 0-channel amplifiers are enabled (and, if the cross-coupling paths from the outputs of the 0-channel amplifiers to the corresponding inputs of the I-channel amplifiers are not already enabled, these are also enabled in this step 626). Then, in step 628, the initial DC offset correction is applied to the I-channel with the 0-channel correction signal kept constant at the stored value determined during the Q-channel initial correction. Long term tracking is then enabled in step 630 before the input signal to the low noise amplifier 5 is enabled in step 632.

It will be understood that the above description assumes that the cross coupling paths are both enabled before the DC offset correction algorithm of Figure 14 is applied. However, if they are not enabled, the outputs of the 0-channel amplifiers may optionally be cross-coupled to the corresponding inputs of the I-channel amplifiers before running the algorithm of Figure 14. In this case, it will not be necessary to disable the cross-coupling between the outputs of the I-channel amplifiers and the inputs of the 0-channel amplifiers as this has not yet been enabled.

During the I-channel initial DC offset correction, a small DC offset may develop on the output of the 0-channel. However, as above, this will typically be within acceptable limits and can be reliably minimised by the long term DC offset tracking. It is further noted that, in band-pass mode, only the I-channel output is forwarded on to the baseband circuitry from the filter, so an offset on the 0-output is of less importance.

It has been found that this alternative correction algorithm can be employed on the 0-channel with at least one of the cross-coupling paths being disabled because, as indicated above, the interdependence of the I and 0-channel outputs and the correction signals applied to the 0 and I channels respectively is weaker than the dependence of the I and 0 channel outputs on their own correction signals.

Chebyshev configuration (NZIF) As in the low pass and Butterworth configurations, the I-channel output signal is directly proportional to the I-channel DC offset correction signal and the Q-channel output signal is directly proportional to the 0-channel DC offset correction signal for the Chebyshev configuration (see Figures iSa and lSd respectively). However, as shown in Figure lSb, the I-channel output voltage strongly depends on the 0-channel offset correction signal. In addition, as shown in Figure lSc, the 0-channel output voltage has a strong inverse dependence on the I-channel offset correction signal. Indeed, the interdependence of the I and 0-channel output voltages on the 0 and I-channel offset correction signals dominates the dependence of the output voltage of each channel on its own offset correction signal. This interdependence again means that it is not possible to run initial DC offset correction on the I and 0-channels simultaneously as the algorithms will conflict. Instead, the initial DC offset correction algorithm should again be applied to the I and 0-channels in separate operations.

The Chebyshev DC offset correction algorithm is summarised in Figure 16.

As in the first DC offset correction algorithm described above for the Butterworth case, full cross coupling between the I and 0-channels is enabled for all stages of the Chebyshev DC offset compensation algorithm (that is, the outputs of the 0-channel amplifiers are cross-coupled to the inputs of the I-channel amplifiers and vice versa). However, as the inverse dependence of the I-channel output voltage on the 0-channel offset correction signal dominates the effects of the I-channel offset correction signal on the I-channel output voltage, this effect must be accounted for.

This is done in the Chebyshev offset correction algorithm by exchanging the paths between the comparators 554, 556 the offset correction circuitry 557, 562, 564 in step 642, and applying an inversion to the I-channel comparator output in step 640. This is illustrated in Figure 17 by an inverter 700 coupled to the output of the I-channel comparator 554 when the filter is in Chebyshev mode and reconfigurable switching circuitry 710 electrically coupled between the outputs of the comparators 554, 556 and the I and 0-channel DC offset correction circuitry of the controller 557.

The switching circuitry has two configurations: a first configuration in which the output of the I-channel comparator 554 is coupled to the I-channel DC offset correction circuitry 558 in the controller 557 and the output from the 0-channel comparator 556 is coupled to the 0-channel DC offset correction circuitry 560; and a second configuration in which the output of the 0-channel comparator 556 is coupled to the I-channel DC offset correction circuitry 558 and the output of the I-channel comparator 554 is coupled to the 0-channel DC offset correction circuitry 560. Thus, in the first configuration, the controller is configured to vary the I and 0-channel correction signals in accordance with the I and 0-channel outputs respectively (as required in the Butterworth algorithms described above); and in the second configuration the controller is configured to vary the I and Q-channel correction signals in accordance with the 0 and I-channel outputs respectively (as required in the Chebyshev algorithm described below). The switching circuitry 710 allows the same controller 557 to be used for the Butterworth and Chebyshev algorithms.

Referring again to Figure 16, after the paths have been exchanged (i.e. the switching circuitry 710 is in its second configuration) and the I-channel comparator output has been inverted, the filter is put into initial calibration mode by disabling the input signal to the low noise amplifier in step 644.

Next, in step 646 the initial DC offset correction algorithm is applied to the Q-channel. In this case, the Q-channel DC offset correction signal is kept constant (typically at zero, but optionally at a non-zero value), while the dominant I-channel DC offset correction signal is varied. That is, the binary search and successive approximation algorithms are applied to the I-channel DC offset correction signal until the Q-channel output is within an acceptable range of the common mode level. Once the Q-channel output is within the acceptable range, the I-channel DC offset correction signal is stored. Next, in step 648, the initial DC offset correction algorithm is applied to the I-channel. In this case, the I-channel DC offset correction signal is kept constant at the value determined in the previous step 646, while the dominant Q-channel DC offset correction signal is varied, That is, the binary search and successive approximation algorithms are applied to the Q-channel DC offset correction signal until the I-channel output is within an acceptable range of the common mode level. Long term tracking is then enabled in step 650 before the input signal to the low noise amplifier 5 is enabled in step 652.

By exchanging the paths between the comparators 554, 556 and the offset correction circuitry, when the initial DC offset correction algorithm is applied to one of the I or Q-channels, the correction algorithm now responds to the DC offset correction signal generated in the other channel through the cross coupling resistors. By doing this, the offset correction algorithm responds to the strongest dependence. In addition, the inverse dependence of the I-channel output voltage on the Q-channel offset correction signal is corrected by the inverter 700. This enables the same control circuitry to be used for the low pass, Butterworth and Chebyshev configurations.

There still remains a dependence of the Q-channel output on the Q-channel correction signal (and similarly for the I-channel). Therefore, as in the Butterworth configuration, a small DC offset may develop on the output of the 0-channel during the I-channel DC offset correction. However, this will typically be within acceptable limits and can be adequately and reliably removed by the longer term DC offset tracking. It is further noted that only the I-channel output is forwarded on to the baseband device from the tuner, so an offset on the 0-output is of less importance than if it was on the I-channel.

It is noted that, in the Butterworth case, there is also an inverse relationship between the 0-channel output voltage and the I-channel offset correction current. However, since the dependence of the 0-channel output on the 0-channel offset correction current dominates in the Butterworth case, this inverse relationship does not need to be accounted for by inversion as is required in the Chebyshev case.

Figure 18 illustrates one method of implementing the switching circuitry 710. The outputs from the I-channel comparator 554 and the 0-channel comparator 556 are fed into first and second 2:1 multiplexers 800, 802.

More specifically, the outputs of the I and 0-channel comparators 554, 556 are input to the first and second inputs of the first multiplexer 800 respectively, while the output of the 0-channel comparator 556 is input to a first input of the second multiplexer 802 and the output of the I-channel comparator 554 is input to the second input of the second multiplexer 802 via an inverter 803.

Each multiplexer has a select input line connected to the output of an AND gate 806. The AND gate has two inputs, NZIF' and CHEBY'. When the band-pass Chebyshev or Butterworth configurations are in use, the NZIF input is set to 1'. The CHEBY input is only set to 1' when the filter is in the Chebyshev configuration. The AND gate only outputs a 1' when both the NZIF and CHEBY variables are set to 1'.

Thus, when the filter is not in the Chebyshev configuration, the I-channel output is output from the first multiplexer 800 (uninverted), while the Q-channel output is output from the second multiplexer 802. However, when the filter is in the Chebyshev configuration, the Q-channel output is output from the first multiplexer, while the inverted I-channel is output from the second multiplexer. Thus, the I and Q-channel outputs have been switched as required, while the I-channel output has also been inverted for the Chebyshev configuration.

Although the comparator outputs are inverted in the above description, the I-channel outputs themselves may alternatively be inverted before being input to the comparators 554, 556. In another alternative embodiment, separate control circuitry may be provided for the Chebyshev and Butterworth configurations. However, this is not a preferred option due to the increase in expense and footprint caused by increasing the amount of circuitry.

Although the DC offset correction signal is injected between the first and second stages 102, 104, the amplifier offsets in the first stage 102 are cancelled out by the offset correction signal. It is also noted that the DC offset correction signals are only injected into the input of one stage of the filter. The inventor has found that, surprisingly, injecting DC offset correction into the input of only one (early) stage of the filter is sufficient to minimise the impact of the amplifier input DC offsets and to keep the output voltage at a mid-rail value.

Although the DC offset correction algorithms have been described with reference to a filter comprising fully differential operational amplifiers, it will be understood that they are equally applicable to filters comprising single ended operational amplifiers. In this case, the comparators 554, 556 may be replaced with window comparators which compare the single ended outputs with mid-rail reference signals. If the single ended outputs are greater than the mid-rail reference signals, a digital 1' is output by the comparator, while if the single ended outputs are less than the mid-rail reference signals, a digital 0' is output by the comparator. The rest of the DC offset correction algorithms function as described above.

It is also noted that, although the signals above may be referred to as voltages or electrical currents, the voltage signals may alternatively be electrical current signals and the electrical current signals may alternatively be voltages where appropriate.

Although in the DC offset compensation algorithms described above with reference to the band-pass configurations the Q-channel is calibrated before the I-channel, it will be understood that the I-channel may alternatively be calibrated before the Q-channel.

While this detailed description has set forth some embodiments of the present disclosure, the appended claims cover other embodiments of the present disclosure which may differ from the described embodiments according to various modifications and improvements.

Claims (26)

1. CLAIMS1. A reconfigurable electronic filter comprising: a first stage having a first pair of cross coupled amplifiers, each amplifier having an input and an output electrically coupled together via a respective first stage variable capacitor, the first pair of amplifiers being cross coupled via first stage variable resistors; a second stage having cascaded second and third pairs of cross coupled amplifiers, each amplifier having an input and an output electrically coupled together via a respective second stage variable capacitor, the second and third pairs of amplifiers each being cross coupled via second stage variable resistors; and a controller configurable to set the first stage capacitors to a first capacitance value and the second stage capacitors to a second capacitance value different from the first capacitance value, and to set the first stage resistors to a first resistance value and the second stage resistors to a second resistance value different from the first resistance value.
2. 2. The reconfigurable filter of claim 1 wherein the product of the first resistance value and the first capacitance value is substantially equal to the product of the second resistance value and the second capacitance value.
3. 3. The reconfigurable filter of claim 1 or 2 further comprising a feedback path between an output from the third pair of amplifiers and an input of the second pair of amplifiers.
4. 4. The reconfigurable filter of any preceding claim wherein each first stage variable capacitor is electrically connected in parallel with a resistor, and each second stage variable capacitor electrically coupled between an input and an output of an amplifier of the second pair is electrically connected in parallel with a resistor.
5. 5. The reconfigurable filter of claim 4 wherein the resistors connected in parallel with the variable capacitors of the second pair are variable resistors.
6. 6. The reconfigurable filter of any preceding claim wherein the third pair of amplifiers is electrically coupled to the second pair via one or more resistors.
7. 7. The reconfigurable filter of any preceding claim wherein the second stage is electrically coupled to the first stage via one or more variable resistors.
8. 8. The reconfigurable electronic filter of any preceding claim wherein the controller is also configurable to set the first and second stage capacitors to a third capacitance value and the first and second stage resistors to a third resistance value.
9. 9. The reconfigurable electronic filter of any preceding claim wherein the amplifiers are operational amplifiers.
10. 10. The reconfigurable electronic filter of claim 9 wherein the operational amplifiers are differential operational amplifiers, each having first and second inputs and first and second outputs.
11. 11. The reconfigurable filter of claim 10 wherein the first input of each amplifier has a first electrical polarity, the second input of each amplifier has a second electrical polarity, the first output of each amplifier has the second electrical polarity and the second output of each amplifier has the first electrical polarity.
12. 12. The reconfigurable filter of claim 11 wherein the first, second and third pairs of amplifiers each comprise a first amplifier and a second amplifier, the first input of the first amplifier being cross-coupled to the first output of the second amplifier, the second input of the first amplifier being cross-coupled to the second output of the second amplifier, the first input of the second amplifier being cross-coupled to the second output of the first amplifier and the second input of the second amplifier being cross-coupled to the first output of the first amplifier.
13. 13. The reconfigurable electronic filter of any of claims 10 to 12 wherein the first input and the first output of each amplifier are electrically coupled together via a variable capacitor and the second input and the second output of each amplifier are electrically coupled together via a variable capacitor.
14. 14. The reconfigurable filter of any of claims 10 to 13 as dependent on claim 3 comprising: a first feedback path between the first output of a first amplifier of the third pair and the second input of a first amplifier of the second pair; and a second feedback path between the second output of the first amplifier of the third pair and the first input of the first amplifier of the second pair.
15. 15. The reconfigurable filter of claim 14 further comprising: a third feedback path between the first output of a second amplifier of the third pair and the second input of a second amplifier of the second pair; and a fourth feedback path between the second output of the second amplifier of the third pair and the first input of the second amplifier of the second pair.
16. 16. The reconfigurable electronic filter of any preceding claim wherein the amplifiers are implemented in CMOS.
17. 17. The reconfigurable filter of any preceding claim wherein each amplifier is an inverting amplifier.
18. 18. The reconfigurable electronic filter of any preceding claim wherein the controller is configurable to provide the filter with a polyphase frequency response.
19. 19. The reconfigurable electronic filter of any preceding claim wherein the controller is configurable to set the first and second stage variable resistors to an open circuit configuration.
20. 20. The reconfigurable electronic filter of any preceding claim further comprising a plurality of second stages cascaded together.
21. 21. The reconfigurable electronic filter of claim 20 wherein the second stages each have independently programmable 0-factors.
22. 22. The reconfigurable electronic filter of any preceding claim wherein the filter can be configured to provide a low pass or a band pass response.
23. 23. The reconfigurable electronic filter of any preceding claim wherein the filter can be configured to provide a Butterworth type response or a Chebyshev type response.
24. 24. The reconfigurable electronic filter of any preceding claim wherein each first stage amplifier input is electrically connected to an external signal input via a respective variable resistor.
25. 25. A television or radio tuner integrated circuit comprising the reconfigurable electronic filter of any of claims I to 24.
26. 26. A method of configuring a filter, the method comprising: a. providing a first stage having a first pair of amplifiers, each amplifier having an input and an output electrically coupled together via a respective first stage variable capacitor; b. electrically cross coupling the first pair of amplifiers via first stage variable resistors; c. providing a second stage having second and third pairs of amplifiers, each amplifier having an input and an output electrically coupled together via a respective second stage variable capacitor; d. electrically cross coupling the second and third pairs of amplifiers via second stage variable resistors; e. cascading the second and third pairs of amplifiers; f. setting the first stage capacitors to a first capacitor value and setting the second stage capacitors to a second capacitor value different from the first capacitor value; and g. setting the first stage variable resistors to a first resistance value and the second stage variable resistors to a second resistance value different from the first resistance value.