GB2484704A - Patch antenna structure formed with an air gap in a flip-chip assembly - Google Patents
Patch antenna structure formed with an air gap in a flip-chip assembly Download PDFInfo
- Publication number
- GB2484704A GB2484704A GB1017737.6A GB201017737A GB2484704A GB 2484704 A GB2484704 A GB 2484704A GB 201017737 A GB201017737 A GB 201017737A GB 2484704 A GB2484704 A GB 2484704A
- Authority
- GB
- United Kingdom
- Prior art keywords
- patch antenna
- layer
- ground plane
- solder
- component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q9/00—Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
- H01Q9/04—Resonant antennas
- H01Q9/0407—Substantially flat resonant element parallel to ground plane, e.g. patch antenna
- H01Q9/045—Substantially flat resonant element parallel to ground plane, e.g. patch antenna with particular feeding means
- H01Q9/0457—Substantially flat resonant element parallel to ground plane, e.g. patch antenna with particular feeding means electromagnetically coupled to the feed line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
- H01Q1/38—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q9/00—Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
- H01Q9/04—Resonant antennas
- H01Q9/0407—Substantially flat resonant element parallel to ground plane, e.g. patch antenna
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
Landscapes
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Waveguide Aerials (AREA)
Abstract
A patch antenna structure, or a method of manufacturing a patch antenna, comprises two dielectric material layers 608, 614 with a plurality of height controlled structures 622. A patch antenna 616 is formed on one surface of a first dielectric layer 614 and a ground layer 610 with an aperture 611 is formed on a surface of a second dielectric layer 608. The patch 616 and aperture 611 are aligned with each other with their respective surfaces facing one another when the dielectric layers 608, 614 are secured to and separated from one another by the plurality of height controlled structures 622. The said height controlled structures 622 comprise solder balls and connection pads, where the solder balls have a core material with a higher melting temperature than that of the surrounding solder material. The solder balls serve to control the separation of the first and second layers 608, 614, thereby determining the height of a void between those layers. A feed line 606 may be arranged on or adjacent to the first or second surface of the second dielectric layer 608. Conventional flip-chip assembly may provide an a patch antenna with a suitable air gap, accurate alignment and spacing of the components.
Description
PATCH ANTENNA STRUCTURES
The present invention relates to patch antenna structures.
BACKGROUND OF THE INVENTION
One of the significant challenges for creating wireless telecommunications devices in a highly integrated manner in a single package is being able to integrate the antenna into the package. One antenna structure which is suitable for integrating into a single package is the so-called patch antenna structure, such as that shown in Figure 1 of the accompanying drawings.
A first planar dielectric layer 104 has first and second substantially planar sides which define first and second surfaces. A conductive ground plane layer 102 is located on the first surface of the first dielectric layer 104. A conductive feed line layer 106 is located on the second surface of the first dielectric layer 104, and a second dielectric layer 108 is located on the feed line layer 106. A conductive ground plane layer 110 is located on the second dielectric layer 108, and defines a slot or void 111. The slot 111 is surrounded by the ground plane layer 110. The feed line layer 106 is arranged such that a signal feed area is substantially aligned with the slot 111.
A third dielectric layer 114 is located on the ground plane layer 110. A patch antenna 116 is located on the third dielectric layer 114, on a side of the layer 114 opposite to that which is adjacent the ground plane layer 110.
In a transmit mode, radio frequency signals are input to the feed line layer 106, and directed from the signal feed area towards the ground plane layer 110 At least a portion of the radio-frequency energy is transmitted through the slot 111 to the patch antenna 116 for transmission therefrom. In a receive mode, radio-frequency energy received at the patch antenna 116 from outside of the device is directed to the signal feed area of the feed line layer 106 via the ground plane slot 111.
A second known patch antenna structure is shown in Figure 2, and is sometimes referred to as a "coplanar waveguide fed patch antenna". A first dielectric layer 204 has first and second substantially planar sides which define first and second surfaces. A conductive ground plane layer 202 is located on the first surface of the first dielectric layer 204. A conductive ground plane 210, which defines a slot 211, and a conductive feed line 206 are located on the second surface of the first dielectric layer 204, and a second dielectric layer 208 is located on the ground plane 210 and feed line 206. The feed line 206 has a signal feed area 207 which is located in the slot 211 of the ground plane 210. The feed line 206 and the ground plane 210 are co-planar. Figure 3 illustrates, in plan view, one possible example of the relative positioning of the ground plane 210, the slot 211, and the feed line 206. It will be appreciated that the choice of shape of the components shown in Figure 3 is arbitrary, and that the components can be of any appropriate shape.
The second dielectric layer 208 has a first substantially planar surface which is arranged adjacent the ground plane 210 and feed line 206, and has a second substantially planar surface which carries a planar conductive patch antenna 216 thereon. The patch antenna 216 is arranged so as to be substantially aligned with the slot 211 and feed area 207 of the feed line 206.
Although patch antenna such as those shown in Figures 1, 2, and 3 are relatively compact, the structures lead to an antenna with low bandwidth because of the relatively high permittivity of the dielectric layer located between the slot and the patch antenna.
For improved bandwidth characteristics, a material having a lower permittivity could be utilised for the dielectric layer between the patch antenna and the slot. However, such material generally does not have the required characteristics to be processed according to standard manufacturing techniques, and so leads to increased processing steps and expense.
Another option is to provide an air gap between the ground plane and the patch antenna, as illustrated by a second previously considered structure shown in Figure 4.
The structure shown in Figure 4 has a basic configuration similar to that of the structure of Figure 1, although the principles are applicable to the structure of Figures 2 and 3 as well. A first dielectric layer 404 has first and second substantially planar surfaces, and a conductive ground plane layer 402 is located on the first surface of the first dielectric layer 404. A conductive feed line layer 406 is located on the second surface of the first dielectric layer 404, and a second dielectric layer 408 is located on the feed line layer 406. A conductive ground plane layer 410 is located on an upper surface of the second dielectric layer 408, and defines a slot or void 411. The slot 411 is surrounded by the ground plane layer 410, as before.
In the example shown in Figure 4, a spacing dielectric layer 412 is provided on the upper surface of the second dielectric layer 408, outside of the ground plane layer 410. It will be readily appreciated that the spacing dielectric layer could be located on the ground plane layer 410. A third dielectric layer 414 is located on an upper surface or surfaces of the spacing layer 412, so asto define a void 413 between the second layer 408, the spacing layer 412, and the third layer 414. The third layer 414 has a surface 415 that bounds the void 413. The ground plane layer 410 bounds at least partially the void 413, on the upper surface of the second dielectric layer 410.
A planar patch antenna 416 is provided on the surface 415 of the third layer 414, such that the patch antenna 416 is opposite the ground plane layer 410 and slot 411 across the void 413. The patch antenna 316 is arranged to be substantially coaxial with the slot 411.
Such a structure overcomes the problems regarding the permittivity of the material between the patch antenna 416 and the slot 411, but has some disadvantages. In particular, the width of the spacing layer 412 is relatively large in order to maintain the integrity of the device, and to allow the device to be produced in a standard process such as a LTCC process. This width is necessary to enable the spacing layer 412 to be successfully and reliably bonded to the second and third layers 410 and 414, leads to the overall package being undesirably large.
A fourth previously considered patch antenna structure is illustrated in Figure 5 of the accompanying drawings, and is similar in basic construction to the structure of Figure 4.
A first dielectric layer 504 has first and second substantially planar surfaces, and a conductive ground plane layer 502 is located on the first surface of the first dielectric layer 504. A conductive feed line layer 506 is located on the second surface of the first dielectric layer 504, and a second dielectric layer 508 is located on the feed line layer 506. A conductive ground plane layer 510 is located on an upper surface of the second dielectric layer 508, and defines a slot or void 511. The slot 511 is surrounded by the ground plane layer 510, as before.
As in the example shown in Figure 4, a spacing dielectric layer 512 is provided on the upper surface of the second dielectric layer 508, outside of the ground plane layer 510. It will be readily appreciated that the spacing dielectric layer could be located on the ground plane layer 510. A third dielectric layer 514 is located on an upper surface or surfaces of the spacing layer 512, 50 as to define a void 513 between the second layer 508, the spacing layer 512, and the third layer 514. The third layer 514 has a surface 515 that bounds the void 513. The ground plane layer 510 bounds at least partially the void 513, on the upper surface of the second dielectric layer 510.
A planar patch antenna 516 is provided on the surface 515 of the third layer 514, such that the patch antenna 516 is opposite the ground plane layer 510 and slot 511 across the void 513. The patch antenna 516 is arranged to be substantially aligned with the slot 511.
In the example of Figure 5, the third layer 514 is attached to the spacing layer 512 by way of attachment pads 518, 519. These attachment pads may be of a metallic material, such that they can be brazed or soldered to one another in order to hold the third layer 514 in place on the spacing layer 512. Alternatively, the attachment pads 518, 519 may be glued to one another using a suitable adhesive material.
Such a structure has the advantage that a void can be formed in a device even if the process used to fabricate the rest of the structure does not allow voids. However, the example of Figure 5 does have the significant disadvantage that an extra processing step and technique is required in order to attach the antenna-carrying third layer. In addition, the third layer must be very accurately positioned and aligned.
It is, therefore, desirable to provide a patch antenna structure which can be manufactured using existing manufacturing techniques, whilst providing a suitable air gap and accurate alignment and spacing of the components.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, there is provided a patch antenna structure comprising a first component of a dielectric material, the first component defining a first substantially planar surface; a plurality of controlled height structures located on the first surface; a second component of a dielectric material, the second component defining a second substantially planar surface, and being located on the controlled height structures such that the second surface faces the first surface across a void defined between the first and second surfaces and the controlled height structures, the second surface being separated from the first surface by a distance determined by the controlled height structures; a ground plane layer located on the second surface, and having an aperture therethrough; and a patch antenna located on the second surface substantially aligned with the aperture of the ground plane layer, wherein each controlled height structure includes first and second capture pads located on the first and second surfaces respectively, a solder ball located between, and attached to, such first and second capture pads, each solder ball having a core of a base material surrounded by a solder material, the base material having a melting temperature higher than that of the solder material.
According to a second aspect of the present invention there is provided a method of fabricating a patch antenna structure, the method comprising the steps of providing a first component of a dielectric material, the first component defining a first substantially planar surface; depositing a ground plane layer onto the first surface, the ground plane layer defining an aperture thereth rough; depositing a plurality of first capture pads onto the first surface; locating a plurality of solder balls onto respective first capture pads, each solder ball having a core of a base material surrounded by a solder material, the base material having a melting temperature higher than that of the solder material; providing a second component of a dielectric material, the second component defining a second substantially planar surface; depositing a patch antenna onto the second surface; depositing a plurality of second capture pads onto the second surface; locating the second capture pads on respective ones of the solder balls, such that the second surface faces the first surface across a void defined between the first and second surfaces, the second surface being separated from the first surface by a distance determined by the solder balls, such that the patch antenna is substantially aligned with the aperture of the ground plane layer; melting the solder material of the solder balls, without melting the base material of the solder balls; and cooling the solder material of the solder balls, such that the first and second capture pads are affixed to the solder ball, so as to align the second capture pads with respect to the first capture pads.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 illustrates a first previously considered patch antenna structure; Figures 2 and 3 illustrate a second previously considered patch antenna structure; Figure 4 illustrates a third previously considered patch antenna structure; Figure 5 illustrates a fourth previously considered patch antenna structure; Figure 6 illustrates a patch antenna structure embodying one aspect of the present invention; Figure 7 illustrates the patch antenna structure of Figure 6 in plan view; Figure 8 illustrates an alternative to the patch antenna structure of Figure 6 in plan view; Figure 9 illustrates parts of the antenna structure of Figure 6 in more detail; Figure 10 is a flow chart illustrating steps in a method embodying another aspect of the present invention; and Figure 11 illustrates fabrication of the structure of Figure 6, according to the method of Figure 10.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Figure 6 of the accompanying drawings illustrates a first embodiment of one aspect of the present invention. A first dielectric layer 604 has first and second substantially planar surfaces, and a conductive ground plane layer 602 is located on the first surface of the first dielectric layer 604. A conductive feed line layer 606 is located on the second surface of the first dielectric layer 604, and a second dielectric layer 608 is located on the feed line layer 606.
A semiconductor device 607 is mounted on the feed line layer 606 adjacent the second dielectric layer 608, but will not be described in detail here. A conductive ground plane layer 610 is located on an upper surface of the second dielectric layer 608, and defines a slot or void 611. The slot 611 is surrounded by the ground plane layer 610.
A plurality of controlled height structures 622 are provided on the upper surface of the second dielectric layer, and carry a third dielectric layer 614 thereon. The controlled height structures space the third layer 614 away from the second layer 610 by a predetermined amount. One of the controlled height structures is shown in more detail in Figure 8, and will be described in more detail below. The controlled height structures 622 serve to provide an air gap 613 between the second and third layers 610 and 614. The third layer 614 carries a patch antenna 616 on a surface 616 thereof, such that the patch antenna 616 and ground plane 610/slot 611 face one another across the air gap 613. A high viscosity epoxy seal 626 is located around the edge of the third layer 614, and serves to seal the air gap 613 between the third layer 614 and the second layer 608, in order to prevent ingress of contaminants, such as dust. The seal can be of any suitable material.
Figure 7 illustrates the structure of Figure 6 in partial plan view. The plan view is taken through the air gap 613, and the patch antenna is shown in dotted lines to illustrate its positioning relative to the other components. The ground plane layer 610 defines the slot 611, through which the second dielectric layer can be seen. The plurality of controlled height structures 622 are arranged on the second layer 608, around the ground plane layer 610.
The patch antenna 616, shown in dotted lines, is aligned substantially coaxially with the slot 611.
It will be readily appreciated that the shapes of the component shown in Figure 7 are merely exemplary, and that the ground plane 610, slot 611, and patch antenna 616 could be of any shape as required by a particular application. For example, the slot 611 and patch antenna 616 could be square, rectangular, circular, elliptical, irregular in shape, or patterned, in plan view. It will also be appreciated that there can be provided any suitable number of controlled height structures.
Figure 8 illustrates how the structure of figures 6 and 7 can be adjusted for use with a co-planar feed line device. The ground plane 610, and feed line layer 606 are both located on the same surface of the second dielectric layer 608. The ground plane 610 is shaped so that the feed line layer 606 can run into the slot 611. In the example of Figure 8, one of the controlled height structures 622 has been removed in order to allow the feed line layer 606 to run into the slot 611. It will be appreciated that any number of controlled height structures could be removed in order to allow the use of the coplanar feed line layer. Alternatively, the feed line layer could be routed between adjacent controlled height structures such that no structures need to be removed.
Figure 9 illustrates one of the controlled height structures 622 of the embodiment of Figure 6.
The controlled height structure 622 comprises a first capture pad 623 attached to the second dielectric layer 608, and a second capture pad 624 attached to the third dielectric layer 614.
A non-collapsible solder alloy ball 625 is provided between the capture pads 620 and 624, and comprises a core 622a, surrounded by a solder alloy material 622b. As will be described in more detail below, the solder alloy ball 622 is subjected to heating, such that the solder alloy material 622b melts, and thereby bonds with the capture pads 620 and 624.
As the solder alloy material 622b melts, surface tension of the resulting liquid causes the capture pads 620 and 624 (and hence the second and third layers 608 and 614) to align.
The core 622a is of a material that has a higher melting point than that of the solder alloy material 622b, so that the height of the controlled height structure is accurately controlled.
When the molten solder alloy material 622b cools, the first and second capture pads 620 and 624 are joined together by the solder alloy material 622b, at a spacing controlled by the core 622a and the solder alloy material 622b.
Figure 10 is a flowchart showing steps in a method of fabricating a structure a shown in Figures 6 to 9, and Figure 11 illustrates these steps. Figures 10 and 11 will be described together.
S
At step A, the first dielectric layer 604 is provided and the ground plane layer 602 deposited onto a first (lower) surface thereof. At step B the feed line layer 606 is deposited onto a second (upper) surface of the first dielectric layer 604. At step C, the second dielectric layer 408 is attached to the feed line layer 606.
The ground plane layer 610, and a plurality of first capture pads 623 are then deposited onto an upper surface of the second dielectric layer 608 (step D). Respective solder alloy balls 625 are located on the first capture pads 623 (Step E). At Step F, the third dielectric layer 614 is prepared by depositing the patch antenna 616 and a plurality of second capture pads 624 on the same surface thereof.
The third dielectric layer 614 is then positioned over the second dielectric layer 608 such that the second capture pads 624 come into contact with respective solder alloy balls 625 located on the first capture pads 623 (Step G). The assembly is heated such that the solder alloy material 625b melts, thereby bonding the first capture pads 623 to respective second capture pads 624. Surface tension of the molten solder alloy material 625b causes the capture pads, and hence the second and third dielectric layers, to align with one another.
The central core material 625a of the solder alloy balls 625 does not melt, and so controls the height of the gap 613.
A sealing material 626 can then be located around the outside of the controlled height structures in order to prevent ingress of dust or foreign matter into the air gap 613.
Such a fabrication technique allows an air gap to be provided between the ground plane and the patch antenna, whilst making use of existing substrate or laminate fabrication techniques.
Claims (11)
- CLAIMS: 1. A patch antenna structure comprising: a first component of a dielectric material, the first component defining a first substantially planar surface; a plurality of controlled height structures located on the first surface; a second component of a dielectric material, the second component defining a second substantially planar surface, and being located on the controlled height structures such that the second surface faces the first surface across a void defined between the first and second surfaces and the controlled height structures, the second surface being separated from the first surface by a distance determined by the controlled height structures; a ground plane layer located on the second surface, and having an aperture therethrough; and a patch antenna located on the second surface substantially aligned with the aperture of the ground plane layer, wherein each controlled height structure includes first and second capture pads located on the first and second surfaces respectively, a solder ball located between, and attached to, such first and second capture pads, each solder ball having a core of a base material surrounded by a solder material, the base material having a melting temperature higher than that of the solder material.
- 2. A patch antenna structure as claimed in clam 1, further comprising a feed line layer attached to a further surface of the first component, which further surface is to an opposite side of the first component to the first surface.
- 3. A patch antenna device as claimed in claim 1, further comprising a feed line layer located on the first surface, the feed line layer being separate to the ground plane layer, and extending into the aperture through the ground plane layer.
- 4. A radio frequency device comprising a patch antenna as claimed in any one of the preceding claims.
- 5. A method of fabricating a patch antenna structure, the method comprising the steps of: providing a first component of a dielectric material, the first component defining a first substantially planar surface; depositing a ground plane layer onto the first surface, the ground plane layer defining an aperture therethrough; depositing a plurality of first capture pads onto the first surface; locating a plurality of solder balls onto respective first capture pads, each solder ball having a core of a base material surrounded by a solder material, the base material having a melting temperature higher than that of the solder material; providing a second component of a dielectric material, the second component defining a second substantially planar surface, depositing a patch antenna onto the second surface; depositing a plurality of second capture pads onto the second surface; locating the second capture pads on respective ones of the solder balls, such that the second surface faces the first surface across a void defined between the first and second surfaces, the second surface being separated from the first surface by a distance determined by the solder balls, such that the patch antenna is substantially aligned with the aperture of the ground plane layer; melting the solder material of the solder balls, without melting the base material of the solder balls; and cooling the solder material of the solder balls, such that the first and second capture pads are affixed to the solder ball, so as to align the second capture pads with respect to the first capture pads.
- 6. A method as claimed in claim 5, further comprising the step of: depositing a feed line layer onto a further surface of the first component, which further surface is to an opposite side of the first component to the first surface.
- 7. A method as claimed in clam 5, further comprising the step of: depositing a feed line layer located on the first surface, the feed line layer being separate to the ground plane layer, and extending into the aperture through the ground plane layer.
- 8. A method of manufacturing a radio frequency device comprising providing a patch antenna structure as claimed in any of claims 1 to 4.
- 9. A method of manufacturing a radio frequency device comprising steps in a method as claimed in any one of claims 5 to 7.
- 10. A patch antenna structure substantially as hereinbefore described with reference to, and as shown in, Figures 6 to 9 of the accompanying drawings.
- 11. A method of manufacturing a patch antenna structure substantially as hereiribefore described with reference to, and as shown in, Figure 10 and 11 of the accompanying drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB1017737.6A GB2484704A (en) | 2010-10-21 | 2010-10-21 | Patch antenna structure formed with an air gap in a flip-chip assembly |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB1017737.6A GB2484704A (en) | 2010-10-21 | 2010-10-21 | Patch antenna structure formed with an air gap in a flip-chip assembly |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB201017737D0 GB201017737D0 (en) | 2010-12-01 |
| GB2484704A true GB2484704A (en) | 2012-04-25 |
Family
ID=43334125
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB1017737.6A Withdrawn GB2484704A (en) | 2010-10-21 | 2010-10-21 | Patch antenna structure formed with an air gap in a flip-chip assembly |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2484704A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2992103A1 (en) * | 2012-06-19 | 2013-12-20 | St Microelectronics Sa | INTEGRATED THREE-DIMENSIONAL STRUCTURE COMPRISING AN ANTENNA |
| WO2015023299A1 (en) | 2013-08-16 | 2015-02-19 | Intel Corporation | Millimeter wave antenna structures with air-gap layer or cavity |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000077886A1 (en) * | 1999-06-10 | 2000-12-21 | Siemens Aktiengesellschaft | Antenna |
| US20080316106A1 (en) * | 2004-12-30 | 2008-12-25 | Klaus Voigtlaender | Antenna System for a Radar Transceiver |
| US20090168367A1 (en) * | 2007-12-27 | 2009-07-02 | Shinko Electric Industries Co., Ltd. | Electronic apparatus |
| EP2144329A1 (en) * | 2008-07-07 | 2010-01-13 | International Business Machines Corporation | Radio frequency integrated circuit packages |
| WO2010058337A1 (en) * | 2008-11-19 | 2010-05-27 | Nxp B.V. | Millimetre-wave radio antenna module |
-
2010
- 2010-10-21 GB GB1017737.6A patent/GB2484704A/en not_active Withdrawn
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000077886A1 (en) * | 1999-06-10 | 2000-12-21 | Siemens Aktiengesellschaft | Antenna |
| US20080316106A1 (en) * | 2004-12-30 | 2008-12-25 | Klaus Voigtlaender | Antenna System for a Radar Transceiver |
| US20090168367A1 (en) * | 2007-12-27 | 2009-07-02 | Shinko Electric Industries Co., Ltd. | Electronic apparatus |
| EP2144329A1 (en) * | 2008-07-07 | 2010-01-13 | International Business Machines Corporation | Radio frequency integrated circuit packages |
| WO2010058337A1 (en) * | 2008-11-19 | 2010-05-27 | Nxp B.V. | Millimetre-wave radio antenna module |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2992103A1 (en) * | 2012-06-19 | 2013-12-20 | St Microelectronics Sa | INTEGRATED THREE-DIMENSIONAL STRUCTURE COMPRISING AN ANTENNA |
| US9385424B2 (en) | 2012-06-19 | 2016-07-05 | Stmicroelectronics Sa | Three-dimensional integrated structure comprising an antenna |
| WO2015023299A1 (en) | 2013-08-16 | 2015-02-19 | Intel Corporation | Millimeter wave antenna structures with air-gap layer or cavity |
| CN105379007A (en) * | 2013-08-16 | 2016-03-02 | 英特尔公司 | Millimeter wave antenna structures with air-gap layer or cavity |
| EP3033804A4 (en) * | 2013-08-16 | 2017-03-08 | Intel Corporation | Millimeter wave antenna structures with air-gap layer or cavity |
Also Published As
| Publication number | Publication date |
|---|---|
| GB201017737D0 (en) | 2010-12-01 |
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