GB2457113A

GB2457113A - CMOS negative resistance circuits

Info

Publication number: GB2457113A
Application number: GB0809754A
Authority: GB
Inventors: Yong Khim Swee
Original assignee: Individual
Current assignee: Individual
Priority date: 2008-01-31
Filing date: 2008-05-29
Publication date: 2009-08-05
Also published as: SG154366A1; GB0809754D0

Abstract

A three-transistor CMOS negative resistance circuit has a good frequency response and low current consumption. The drain current of Q3 is mirrored by Q2 and Q1 to the gate node of Q3 so that the current drawn by Q1 falls as the input voltage rises. The circuit may be used as an amplifier or oscillator, or to simulate a tunnel diode. The circuit may also be used to increase Q factor or resistance. The circuit, and its dual using transistors of inverted polarity, may be used to provide small-signal negative resistance in any current-voltage quadrant (figures 5,6,9 and 10). A large-signal negative resistance with a volt-ampere curve passing through the origin may be implemented (figure 15).

Description

CIRCUITS WITH NEGATIVE DIFFERENTIAL RESISTANCE CHARACTERISTICS

Technical Field

This invention relates to circuits with negative differential resistance characteristics and refers particularly, though not exclusively, to a semiconductor device including circuits with negative differential resistance characteristics.

Background

As shown in Fig 1 it is know to use an operational amplifier ("opamp") 101 to produce negative resistance characteristics where Rin= -RNF (R1/R2). An opamp is an analog device having a low leakage in the range of about 5.4 to 2OpA. The offset from the ground is 4 to 2OmV and has a quiescent current of about 5-8mA. The frequency response is normally about 200MHz. An opamp has a number of stages and a relatively high number of transistors. This limits the frequency response. Also, there is input leakage, and an offset voltage is created on the inputs and the vertical ground.

The quiescent current is relatively high.

Summary

According to an exemplary aspect there is provided a circuit with negative differential resistances characteristics. The circuit comprises a first transistor with a first transistor gate, a first transistor source and a first transistor drain; a second transistor with a second transistor gate, a second transistor source and a second transistor drain; and a third transistor with a third transistor gate, a third transistor source and a third transistor drain. The first transistor gate and the second transistor gate are operatively connected to form a current mirror pair. The third transistor drain is operatively connected to the first transistor gate and the second transistor gate. The third transistor is operatively connected to the first transistor.

The operative connection of the third transistor to the first transistor gate and the second transistor gate may be by the third transistor drain. The operative connection of the third transistor to the first transistor may be by the third transistor gate to the first transistor drain. The operative connection of the third transistor to the first transistor may be by one of: the first transistor source, and the first transistor drain.

An operative connection may be provided to ground at one of: the first transistor source and the second transistor source. The circuit may be able to operate in one of: the first quadrant, the second quadrant, the third quadrant, and the fourth quadrant, depending on the operative connection of the third transistor and the first transistor, the operative connection of the third transistor to the first transistor gate and the second transistor gate, the terminal to which the input voltage is to be applied, and the operative connection to ground.

The circuit may further comprise a current sink operatively connected to a terminal selected from: the third transistor gate, the first transistor gate and the second transistor gate, a connection between the third transistor drain and the second transistor source, and a connection between the third transistor gate and the first transistor source.

The circuit may further comprise a current source operatively connected to a terminal selected from: the third transistor gate, the first transistor gate and the second transistor gate, a connection between the third transistor drain and the second transistor drain, and a connection between the third transistor gate and the first transistor drain.

The first transistor and the second transistor may be substantially the same.

The circuit may further comprise a biasing power supply for providing a biasing voltage to the third transistor source.

The circuit may further comprise an input operatively connected to the operative connection between the third transistor and the first transistor, the input having operatively connectable thereto an input power source for providing an input voltage to the operative connection between the third transistor and the first transistor. At least one biasing resistor may be provided in the input. At least one second biasing resistor may be operatively connected between the input and the biasing power supply.

The circuit may further comprise an output for voltage. The output may comprise an output transistor and a load resistor operatively connected to the output transistor. The output for voltage may be operatively connected across the third transistor.

The circuit may further comprise a fourth transistor with a fourth transistor gate, a fourth transistor source and a fourth transistor drain; a fifth transistor with a fifth transistor gate, a fifth transistor source and a fifth transistor drain; and a sixth transistor with a sixth transistor gate, a sixth transistor source and a sixth transistor drain. The fourth transistor gate and the fifth transistor gate may be operatively connected for form a second current mirror pair. The third transistor source may be operatively connected to the sixth transistor source. The sixth transistor drain may be operatively connected to the fourth transistor gate and the fifth transistor gate.

The sources of the fourth and fifth transistors may be operatively connected. The sixth transistor drain may be operatively connected to the fourth transistor gate and the fifth transistor gate. The third transistor source and the sixth transistor source may be operatively connected to ground. The third transistor gate may be operatively connected to the sixth transistor gate. The first transistor source and the second transistor source may be connected to a first terminal of a source of electrical energy.

The fourth transistor drain and the fifth transistor drain may be operatively connected to a second terminal of the source of electrical energy. The first terminal may be a positive terminal and the second terminal may be a negative terminal. The source of electrical energy may be a floating power supply to force any loop current back into the circuit..

The first transistor and the second transistor may be PMOS transistors. The third transistor may be an NMOS transistor. The sixth transistor may be a PMOS transistor.

The fourth and fifth transistors may be NMOS transistors.

The circuit may be used in a manner selected from: an amplifier, a tunnel diode, to cancel resistance in LC oscillators, to cancel real positive resistance, as a resistive element, and added in parallel to a real resistance to increase the impedance of another circuit.

According to a further exemplary aspect there is provided a semiconductor device comprising the circuit described above.

Brief Description of the Drawings

In order that the invention may be better understood and readily put into practical effect, exemplary embodiments shall now be described by way of non-limitative example only, the description being with reference to the accompanying illustrative drawings.

In the drawings: Figure 1 is a circuit diagram of a prior art operational amplifier with negative differential resistance characteristics; Figure 2 is (a) a circuit diagram of a prior art PMOS transistor and (b) a graph of its current vs gate voltage, more commonly called its loadline characteristics; Figure 3 is (a) a circuit diagram of an exemplary embodiment and (b) a graph of its current vs input voltage; Figure 4 is a graph of current vs input voltage for transistor Qi of the exemplary embodiment of Figure 3; Figure 5 is (a) a circuit of another exemplary embodiment being a combination of the circuits of Figures 2 and 3, (b) a graph of its current vs input voltage, (c) a computer simulated circuit corresponding to (a), and (d) a graph of the current vs voltage of the circuit of (c); Figure 6 is an illustration of a quadrant 2 circuit similar to the quadrant 1 circuit of Figure 5; Figure 7 is (a) a graph of the current vs input voltage for the circuit of Figure 6; Figure 8 is (a) a modified form of the circuit of Figure 6 with tunnel diode characteristics, (b) a graph of its current vs input voltage, (c) a computer simulated circuit corresponding to (a), and (d) a graph of the current vs voltage of the circuit of (c); Figure 9 is (a) an illustration of a quadrant 3 circuit similar to the quadrant 2 circuit of Figure 6(a) quadrant 2 circuit of Figure 6, (b) a graph of its current vs input voltage, (c) a computer simulated circuit corresponding to (a), and (d) a graph of the current vs voltage of the circuit of (c); Figure 10 is (a) an illustration of a quadrant 4 circuit similar to the quadrants 1, 2 and 3 circuits of Figures 5, 6 and 9 respectively, (b) a graph of its current vs input voltage, (c) a computer simulated circuit corresponding to (a), and (d) a graph of the current vs voltage of the circuit of (c); Figure 11 is (a) an illustration of the circuit of Figure 5 modified with a current sink, (b) a first graph of its current vs input voltage, (c) a second graph of its current vs input voltage, (d) a computer simulated circuit corresponding to (a), (e) a graph corresponding to (b) of the current vs voltage of the circuit of (d), and (f) is a graph corresponding to (c) of the current vs voltage of the circuit of (d); Figure 12 is (a) an illustration of a circuit that is a variant of that of Figure 11, (b) a graph of its current vs input voltage, (c) a computer simulated circuit corresponding to (a), and (d) a graph of the current vs voltage of the circuit of (c); Figure 13 is (a) an illustration of the circuit of Figure 5 modified with a current source, a graph of its current vs input voltage, (c) a computer simulated circuit corresponding to (a), and (d) a graph of the current vs voltage of the circuit of (c); Figure 14 is (a) an illustration of a circuit that is a variant of that of Figure 13,(b) a graph of its current vs voltage, (c) a computer simulated circuit corresponding to (a), and (d) a graph of the current vs voltage of the circuit of (c); Figure 15 is (a) an illustration of a circuit being a combination of the circuits of Figures and 9, (b) a graph of its current vs input voltage, (c) a computer simulated circuit corresponding to (a), and (d) a graph of the current vs voltage of the circuit of (c); Figure 16 is (a) an illustration of a modified circuit of Figure 15, (b) a graph of its current vs input voltage, (c) a second graph of its current vs voltage, (d) a computer simulated circuit corresponding to (a), and (e) two graphs of the current vs voltage of the circuit of (d); Figure 17 is (a) an illustration of an exemplary quadrant 1 circuit, (b) a graph of its current vs voltage, and (c) a graph of its current and voltage vs time; Figure 18 is a graph of the current in transistors Qi and Q2 of Figure 5 vs input voltage where the curve on the left is and on the right is 1Q2; Figure 19 is a graph of the transconductance gain Gm in transistor Qi of Figure 5 vs frequency; and Figure 20 is (a) a circuit that is a variant of that of Figure 5, with (b) and (c) being graphs of current vs voltage, and (d) being a graph of VOUT vs VIN.

Detailed Description of Exemplary Embodiments

In Figure 2 there is shown a PMOS transistor 03 operating in quadrant 1. The input is to the gate of 03. When the input voltage VIN is low, the transistor Q3 is strongly on with high source/drain current. When the input voltage VIN is high, the transistor Q3 is shut off and the source/drain current is zero. As such transistor Q3 exhibits a strong negative differential resistance characteristic as the current decreases with increasing voltage.

For Figure 3(a), there are two NMOS transistors -01 and 02 with the input voltage VGS(Q2) being applied to the gate of both transistors Qi and 02, the gates also being operatively connected. The output is shown in Figure 3(b) and Figure 4. When VIN 0 or small, the current is linearly dependent on VIN for a fixed gate/source voltage, VGS curve. The VGS curve is controlled to a certain extent by a high value of the currents 1Q2 or The values of 102 and l do not change significantly in the initial portion of the curve -that portion starting from VIN = 0 (Figure 4).

Figures 5 (a) and (c) are a combination of the circuits of Figures 2 and 3. In Figure 5(c) Ml is Qi, M3 is 02 and M4 is Q3. As can be seen, the VIN is now applied to the drain of transistor 01 and the gate of transistor 03. The output from transistor Q3 is the input to the gates of transistors 01 and 02, and to the drain of transistor 02. The output current is shown in Figure 5 (b). By having the input to the gate of transistor 03 (i.e. no DC current) and using the drain current of transistor 03 to provide feedback to generate the impact response current 11N, IN rises from zero to a peak and then falls to zero again as VIN rises from Ov to Vcc, when transistor Q3 switches to off. The nature of the feedback allows a rapid response. It also provides both positive and negative differential resistance characteristics over part of the input voltage range. By using P type CMOS transistor for 03 and N type for Qi and 02 the circuit of Figure 5 can be integrated into CMOS designs during the fabrication process.

In general, current only flows out and therefore the circuit operates in quadrant 1 only.

Transistors 01 and 02 form a current mirror pair. The current in transistor 01 (l) is the same as the current in transistor Q2 (102) except when the input voltage is low.

When VIN is OV, IIN is OA as VIN = VDS of 01 = 0. When VIN Vcc, 03 is off and is zero. Therefore, Q2 = = 0.

In the positive resistance region A (the increasing portion of the graph), when VIN is low �= 102 because the current in Qi is limited by the drain/source voltage VDS of 01.

However, the gate/source voltage VGS of 01 and Q2 are the same. Q2 is relatively high and so the VGS of 02 is on a fixed curve and 101 varies directly with VDS of 01.

Transistor 03 is strongly on.

In the negative resistance region B (lIN decreases with increasing VIN) when VIN is high, 101 = 102 as VGS is the same. VDS of 01 is no longer limiting the current IN as its being limited by V0 of 01.

Due to the rapid response, a high frequency response is possible. The response frequency may be in the RF range of about 500 KHz to 300 GHz. This will be about the process transistor unity gain (01, 02 and 03) frequency. It is also noticeable that the quiescent current is lower as the lower input transistor Qi is off.

The circuit of Figure 5 may be used as one or more of a tunnel diode, an amplifier, to cancel resistance in LC (Inductance and Capacitance or Colpits) type oscillators, to achieve a high 0, and to cancel a real positive resistances as well as having the resistance grounded thus being equivalent to a virtual ground with zero offset. When connected to a real resistance in parallel it can be used to increase the resistance to a value approaching infinity.

The circuit of Figures 5(a) and (c) has the advantages that there is a power supply Vcc to provide bias so as to be able to control the I vs V curve, and an additional terminal or terminals to derive related signals.

As shown in Figures 20 (a) and (d) the use of the current mirror pair 01 and 02 allows for a separate output V01-. The graph of VOUT vs VIN is shown in Figure 20(d). R3 is a load resistor for the output transistor 04, the resistor R3 and transistor 04 being operatively connected across transistor Q3. The amplifier of output transistor Q4 and R3 is the simplest way to have the output VOUT. If the transistors are sized such that the width of transistor 04 is, for example, five times that of transistor 02 then there is five times the current gain. So it is possible to have both current gain and, through 041R3, voltage amplification.

Furthermore, and as shown in Figure 20, resistive bias may be added to modify the behaviour of the circuit. This may be by adding Ri and/or R2. Ri may be used to adjust the characteristics of the I vs V curve as shown in Figure 20(a) and (b), with Figure 20 (b) showing the curve with Ri added. This shows that the curve is a superposition of the curves of RI, and that of the circuit of Figure 5(a). If R2 is of the correct value, R2 together with the circuit of Figure 5(a) under the source excitation VIN will be a negative resistance amplifier. That amplification is able to be captured by the Q4/R3 amplifier. This may be with Ri removed.

The use of the current mirror pair Qi and 02 also allows for scaling up. It also provides the mirrored current on the negative resistance side that can be scaled up or down. As will be clear from the following description, by using current sources and/or drains it is possible to modify the I vs V curve. The current sources and/or drains can be integrated on the same IC.

The three transistors 01, 02 and Q3 may be NMOS, PMOS, or both N or P MOS i.e. CMOS device combinations.

Figure 6 shows a circuit similar to that of Figure 5 but operating in the second quadrant.

As can be seen transistors 01 and 02 have their gates connected with the drain of 01 being connected to the input IN, the input is also connected to the gate of transistor Q3.

The drain of transistor Q2 is connected to the drain of transistor 03. Input voltage V is applied to the drain of transistor 01. The resultant current IN vs voltage is shown in Figure 6 (b). It is, essentially, the same as for Figure 5 but in the second quadrant.

There is no offset from ground; leakage is low at about lOnA, the quiescent current is about lOnA, and the frequency response is about that of the transistors unity gain -in the range of about 500 KHz to 300 GHz.

In general, current IN only flows out of 01. As such the circuit is operating in the second quadrant. Again, transistors Qi and 02 form a current mirror pair. In general, 101 = 102 except when VIN is high -the end conditions. When VIN = OV, Q3 is off and = 0. Also, 102 = = 0. When VIN = VCC, 01 is off and 0.

As shown in Figure 7(a), the positive resistance area A, when VIN is high, �= lQ2 because the current in Qi is limited by the drain/source voltage VDS of 01. The gate/source voltages VGS of Qi and Q2 are the same. 102 is relatively high and so VGS of Q2 is relatively constant. 102 is on a "fixed" VGS curve and 101 varies according to VDS of 01. Transistor 03 is strongly on.

Area B is negative resistance so when VIN is low, = 102 as VGS is the same for 01 and Q2. Transistors 01 and 02 are the same and they are operating as a current mirror. VDS of 01 is no longer limiting the current IN as VGS of Qi is limiting lIN.

In Figures 8(a) and (c) the circuit of Figure 6 is modified by the addition of a current sink 800 between the input, and the gate of transistor 03. In Figure 8(c) M2 is 01, M4 is 02 and M3 is T3. The current 12 able to be carried by current sink 800 should be greater than the maximum current B of IN.

This will move the I vs V curve from quadrant 2 to quadrant 1, and the I vs V characteristics match those of a tunnel diode. When VIN = OV, the drain current ID of Qi is 0 as VIN=0 and 03 is off, and IIN equals 12. As VIN increases, the 01 drain current also increases so that IN + 101 = 12. As the circuit continues to operate as before for Figure 6, the I vs V curve is moved upwardly by the value of 12.

As shown in Figures 9(a) and (c), the circuit of Figure 6 can be modified to operate in the third quadrant. In Figure 9(c) M2 is 01, M4 is 02 and M3 is 03. The input VIN is a negative voltage -VIN applied to the gate of transistor 03 and the ground connection is from the source of both 01 and 02. The operation of the circuit remains as for Figures 6 and 7 and the relative voltages at the terminals are the same. The curve of I vs V is shifted to the left on the Y (i.e. I) axis.

Figures 10(a) and (c) the circuit of Figure 6 is modified as shown with the connections of Vc and ground being interchanged when compared with the circuit of Figure 9 so that it operates in the fourth quadrant. In Figure 10(c) Ml is 01, M3 is 02 and M4 is Q3. The circuit operates as before with the relative voltages at the terminals not changing. The curve has, in effect, been shifted leftwards on the Y (I) axis.

In Figures 11 and 12 the circuit of Figure 5 (quadrant 1) is modified by the addition of current sinks 1100 and 1200 respectively. In Figures 11(a) and (d) the current sink 1100 is operatively connect to the gates of transistors 01 and 02. In Figure 11(d) Ml is 01, M3 is Q2 and M4 is Q3. The current sink 1100 has a current of 12 where 12 is less than the maximum value of IN. When VIN is low, the drain/source voltage VDS of 01 is controlled by lQ3 -12. The curve is higher as the gain through VDS of 01 is greater than the effect of a lower VGS. By increasing the transistor channel width W this effect may be reversed (Figures 11(c) and 11(f)). The cut-off point V is now lower as previously (Figures 5 to 10) the cut-off was when VIN = Vcc and l 0. With the current sink 1100, when lQ3 = 12, the circuit cuts off as there is no current to feed the gates of 01 and 02.

In Figure 12 (c) Ml is 01, M3 is 02 and M4 is 03. By operatively connecting the current sink 1200 (Figure 12) to the operative connection between the gate of 03 and the drain of 01, the curve is moved up by the value of 12 (Figure 12(b)). In that way current 12 is always flowing over the full range of VIN.

As show in Figures 13 and 14, the circuit of Figure 5 may be modified by the addition of a current source 1302 and 1402 respectively. In Figure 13 the current source 1302 is operatively connected to the gates of 01 and 02. In Figure 13(c), Ml is 01, M3 is 02 and M4 is 03. When VIN is low, the gate/source voltage VGS is higher due to 12.

Although VDS of 01 controls the current lIN the gain is higher due to a higher VGS of 01 and 02. The slope of the I vs V curve can be lowered by adjusting the transistor channel length L of 01. When VIN is high, 03 cuts off. But 02 will still have current 12 and this is mirrored in 01. This sets the current flowing in Qi to match that of 02 at 12.

In Figure 14 the current source 1402 is operatively connected to the operative connection between the gate of 03 and the drain of 01. In Figure 14(c), Ml is 01, M3 is 02 and M4 is 03. This shifts the response curve of Figures 13(b) and (d) downwardly by the value of 12.

In Figure 15, the circuits of Figures 6 and 10 are combined as a single circuit with the upper portion being that of Figure 6 and the lower portion being that of Figure 10. In Figure 15(c) Ml is 04, M2 is Q3, M3 is 05, M4 is Q6, M5 is Q2, and M6 is 01. The source of Q3 is operatively connected to the source of Q6, and both are operatively connected to ground. When VIN < OV, the quadrant 2 circuit is off as VGS of 03 is negative and = 0. However, 06 is on and the quadrant 4 circuit is operating. To have a linear response as shown, the negative resistances of the two circuits will need to be substantially the same. This may be done by adjusting the size ratio WIL of 01 and 04.

Figure 16 the circuits of Figures 6 and 10 are combined in series. In Figure 16(d) Ml is 04, M2 is 03, M3 is 05, M4 is 06, M5 is 02, and M6 is 01. Also, VGS(Q2) is applied to the source of both 01 and 02, and VGS(Q5) applied to the drains of 04 and 05. The ground connections are all removed. The power supply 1604 is a floating power supply to force the loop current back into the circuit. This allows the negative resistance to be used, even though it is two negative resistances in series. However, it will behave like a real negative, two-terminal resistor as it forces the same current in and out of the two-terminal, negative resistor. The graphs show that the currents are in opposite directions, and negative resistance is shown in the second quadrant.

As the power supply is floating, the two circuits can work together as the terminal voltages will maintain their relative potentials.

Figure 17 shows a simulated circuit (a) corresponding to that of Figure 5. Ml and M2 form the current mirror pair Qi and 02, with M3 being 03. The graph of (b) is the I vs V curve, and (c) shows current I and V vs Time.

Figure 18 is a graph showing the curves of I vs V for and 102, and Figure 19 is a graph showing gm or self transconductance gain (delta lIN/deltaViN) vs frequency in GHz. This shows excellent frequency response from 0 to 100 GHz.

The circuit may be used in the manner of: an amplifier, a tunnel diode, to cancel resistance in LC oscillators, to cancel real positive resistance, as a resistive element, and added in parallel to a real resistance to increase the impedance of another circuit.

For the last of these 1/RT = 1/R1+1/R(-) if R1=R(-) then the RHS=O and RT approaches infinity.

Whilst there has been described in the foregoing description exemplary embodiments it will be understood by those skilled in the technology concerned that many variations or modifications in details of design, construction and operation may be made without departing from the invention as defined in the following claims.

Claims

CLAIMS: 1. A circuit with negative differential resistances characteristics, the circuit comprising: a first transistor with a first transistor gate, a first transistor source and a first transistor drain; a second transistor with a second transistor gate, a second transistor source and a second transistor drain; a third transistor with a third transistor gate, a third transistor source and a third transistor drain; the first transistor gate and the second transistor gate being operatively connected to form a current mirror pair; the third transistor drain being operatively connected to the first transistor gate and the second transistor gate; the third transistor being operatively connected to the first transistor.
2. A circuit as claimed in claim 1, wherein the operative connection of the third transistor to the first transistor gate and the second transistor gate is by the third transistor drain.
3. A circuit as claimed in claim 1 or claim 2, wherein the operative connection of the third transistor to the first transistor is by the third transistor gate to the first transistor drain.
4. A circuit as claimed in any one of claims 1 to 3, wherein the operative connection of the third transistor to the first transistor is by one of: the first transistor source, and the first transistor drain.
5. A circuit as claimed in any one of claims 1 to 4, wherein an operative connection is provided to ground at one of: the first transistor source and the second transistor source.
6. A circuit as claimed in claim 5, wherein the circuit is able to operate in one of: the first quadrant, the second quadrant, the third quadrant, and the fourth quadrant, depending on the operative connection of the third transistor and the first transistor, the operative connection of the third transistor to the first transistor gate and the second transistor gate, the terminal to which the input voltage is to be applied, and the operative connection to ground.
7. A circuit as claimed in any one of claims 1 to 6 further comprising a current sink operatively connected to a terminal selected from the group consisting of: the third transistor gate, the first transistor gate and the second transistor gate, a connection between the third transistor drain and the second transistor source, and a connection between the third transistor gate and the first transistor source.
8. A circuit as claimed in any one of claims 1 to 6 further comprising a current source operatively connected to a terminal selected from the group consisting of: the third transistor gate, the first transistor gate and the second transistor gate, a connection between the third transistor drain and the second transistor drain, and a connection between the third transistor gate and the first transistor drain.
9. A circuit as claimed in any one of claims 1 to 7, wherein the first transistor and the second transistor are substantially the same.
10. A circuit as claimed in any one of claims 1 to 9 further comprising a biasing power supply for providing a biasing voltage to the third transistor source.
11. A circuit as claimed in any one of claims 1 to 10 further comprising an input operatively connected to the operative connection between the third transistor and the first transistor, the input having operatively connectable thereto an input power supply for providing an input voltage to the operative connection between the third transistor and the first transistor.
12. A circuit as claimed in any one of claims ito 11, wherein at least one biasing resistor is provided in the input.
13. A circuit as claimed in claim 11 when dependent on claim 10, wherein at least one second biasing resistor is operatively connected between the input and the biasing power supply.
14. A circuit as claimed in any one of claims ito 13 further comprising an output for voltage, the output comprising an output transistor and a load resistor operatively connected to the output transistor, the output for voltage being operatively connected across the third transistor.
15. A circuit as claimed in any one of claims 1 to 14 further comprising: a fourth transistor with a fourth transistor gate, a fourth transistor source and a fourth transistor drain; a fifth transistor with a fifth transistor gate, a fifth transistor source and a fifth transistor drain; a sixth transistor with a sixth transistor gate, a sixth transistor source and a sixth transistor drain; the fourth transistor gate and the fifth transistor gate being operatively connected for form a second current mirror pair; the third transistor source being operatively connected to the sixth transistor source; the sixth transistor drain being operatively connected to the fourth transistor gate and the fifth transistor gate.
16. A circuit as claimed in claim 15, wherein the sources of the fourth and fifth transistors are operatively connected.
17. A circuit as claimed in claim 15 or claim 16, wherein the sixth transistor drain is operatively connected to the fourth transistor gate and the fifth transistor gate.
18. A circuit as claimed in any one of claims 15 to 17, wherein the third transistor source and the sixth transistor source are operatively connected to ground.
19. A circuit as claimed in any one of claims 15 to 18, wherein the third transistor gate is operatively connected to the sixth transistor gate.
20. A circuit as claimed in and one of claims 15 to 18, wherein the first transistor source and the second transistor source are connected to a first terminal of a source of electrical energy, and the fourth transistor drain and the fifth transistor drain are operatively connected to a second terminal of the source of electrical energy.
21. A circuit as claimed in claim 20, wherein the first terminal is a positive terminal and the second terminal is a negative terminal.
22. A circuit as claimed in claim 20 or claim 21, wherein the source of electrical energy is a floating power supply to force any loop current back into the circuit..
23. A circuit as claimed in any one of claims 1 to 22, wherein the first transistor and the second transistor are PMOS transistors.
24. A circuit as claimed in any one of claims 1 to 23, wherein the third transistor is an NMOS transistor.
25. A circuit as claimed in any one of claims 15 to 23, wherein the sixth transistor is a PMOS transistor.
26. A circuit as claimed in any one of claims 15 to 23 or claim 25, wherein the fourth and fifth transistors are NMOS transistors.
27. A circuit as claimed in any one of claims 1 to 26, wherein the circuit is used in a manner selected from the group consisting of: an amplifier, a tunnel diode, to cancel resistance in LC oscillators, to cancel real positive resistance, as a resistive element, and added in parallel to a real resistance to increase the impedance of another circuit.
28. A semiconductor device comprising the circuit of any one of claims 1 to 27.
29. A circuit as herein described with reference to the accompanying drawings.
30. A semiconductor device as herein described with reference to the accompanying drawings.