GB2435334A

GB2435334A - Compression and decompression of data stream using a linear feedback shift register

Info

Publication number: GB2435334A
Application number: GB0603313A
Authority: GB
Inventors: Graeme Roy Smith
Original assignee: Individual
Current assignee: Individual
Priority date: 2006-02-20
Filing date: 2006-02-20
Publication date: 2007-08-22
Also published as: GB2449375B; GB0619381D0; WO2007096587A3; GB2449375A; GB0603313D0; GB0813537D0; WO2007096587A2

Abstract

A method and apparatus for compressing and decompressing a data stream comprises selecting a number of samples of the data, using a linear feedback shift register (LFSR) to calculate a feedback polynomial and initial value for the LFSR, generate a signature for each sample, concatenate the generated signature with the next sample and reprocess it using the LFSR until all samples in the data stream have been processed, the final signature being the compressed data. The data signature includes a plurality of data fields preferably including at least the polynomial data, initial LFSR value, polynomial size, cycle count, signature type, DRM type, sample coding type and signature bit length. The synthesis method used by the LFSR may include the Berlekamp-Massey algorithm. In an alternative embodiment signatures from each sample may be stored in a memory. Once the final sample has been processed the stored signatures may be concatenated and the final signature generated by processing the concatenated signatures.

Description

METHOD AND APPARATUS FOR COMPRESSING AND DECOMPRESSING DATA

This invention relates to method and apparatus for compressing and decompressing data.

Data compression methods and their decompression counterparts have been around for several decades. The need for data compression arose in digital systems due to the limited bandwidth of communication channels and the limited storage capacity of memory technologies. For example, the number of luminance picture elements (pixels) per active picture line is usually 720 for conventional television and each frame consists of 575 lines.

With a required sampling frequency of 27 Million Samples per second this equates to a total bit rate of 216 Mbits per second. For High Definition Television (HDTV) systems, the number of pixels per line can be 1440 or 1920 and each frame contains 1152 lines, which only exacerbates the bandwidth and storage problems.

The use of compression technologies enables many digital channels to be transmitted simultaneously over channels that previously carried just one.

Data compression methods or algorithms can be divided into two main categories, namely lossless and lossy compression algorithms. With lossless compression algorithms, no data is lost when the resulting compressed data stream is decompressed. The output from the decompression apparatus is identical to the data stream input to the compression apparatus.

In lossy compression, some of the information is lost. Consequently, the decompressed data is not identical to the original before it was compressed. One method used in lossy compression is to perform coarse quantization of the samples. Lossless compression would be required in applications where corruption in the resulting decompressed data would cause a catastrophic failure or failure for a system to operate correctly. These applications include software programs, source code or text documents. Entropy coding is one method for implementing lossless compression. A commonly used entropy coding method is Huffman coding, which exploits the fact that allowed symbols with a high probability of occurring are allocated or transformed in to a symbol with a low bit width. Whereas, symbols with a low probability of occurring are transformed into a new symbol with a larger number of bits. For example, in text document, the probability of the symbol "e" occurring would be far greater than the probability of the symbol "z" occurring. Consequently, the Huffman symbol for the letter "e" would be say, 3-bits. Whereas, the Huffman symbol for the letter "z" would have say, 16-bits. Other lossless compression methods include Run Length Encoding (RLE) and Lempel-ZivWelch or LZW compression.

Unfortunately, audio signals such as speech or voice cannot be compressed efficiently using entropy-coding techniques. Due to the limitations of the human auditory system user tests have shown that it is not crucial to retain all the audio information when compressing audio data. It is only sufficient that the reproduced or decompressed audio data sounds similar to the listener. This technique is referred to as perceptual audio coding. In this technique, the coder circuits analyse the spectral components of the original audio signal by calculating a filterbank or transform. It then applies a psychoacoustic model to estimate the just noticeable noise-level. In its quantization and coding stage, the encoder tries to allocate the available number of data bits in a way to meet both the bit rate and masking requirements. This results in audio components being reduced in accuracy or being completely removed altogether.

The decompression circuitry is much less complex. It is responsible for synthesizing and outputting an audio signal from the code spectral components.

Likewise, due to the large amount of data produced or required per frame of video many methods have been developed to both compress and decompress video and graphic data. In fact, current prior art systems employ several techniques to reduce the overall bit rate. These include spatial and temporal compression techniques. Spatial compression is sometime referred to as intra-frame compression and temporal compression is referred to as inter-frame compression. The latter relies on coding the differences between consecutive frames.

In many cases the difference between consecutive frames is very small. For example, in a still shot, the background tends to remain the same. Consequently, only data representing the differences is coded and transmitted.

Spatial compression relies on spatial redundancy, unnecessary information, which could be removed before transmission. For example, a small area of blue sky in scene would contain almost identical luminance and chrominance sample values. A Discrete Cosine Transform (DCT) is used to convert the time domain samples to frequency domain samples. The DCT tends to be employed on a block of 8 x 8 samples, though this is not always the case. The resulting matrix block contains the coefficients of the frequency components, where each coefficient effectively represents the amplitude of a specific pattern. Where there is a high spatial redundancy many of the coefficients will be zero.

In other image compression systems a Discrete Wavelet Transform (DWT) or fractal compression techniques are used.

The greater image resolution provided by HDTV also means there will be a greater amount of data to process and transmit. This inevitably requires more sophisticated compression and or modulation techniques, which in turn leads to more complex circuits to implement and process these functions. In many cases, this means adopting smaller dimensioned integrated circuit technology to allow for the instantiation of more processing elements on a single piece of silicon. Adopting such an approach is more expensive and leads to longer time to market as new tools and verification techniques are required to design, simulate and fabricate these silicon devices.

One of the main disadvantages of these compression methods is that though they all provide a high degree of data compression, the level of compression is directly proportional to the size of the original data stream or file. Consequently, the larger the original data file the larger the resulting compressed file. This is exemplified in the data storage requirements of digital audio files and Digital Versatile Disc (DVDs) required to store motion pictures and films. The data storage capacity of a typical DVD is 17 Giga bytes. In fact, many portable digital audio and or video players are priced and graded on the size of their internal memories. These devices employ either semiconductor memories, such as FLASH memory, or magnetic hard disk drives as a storage medium. The greater the memory storage capacity of the device, the more songs and or video clips the device can store for future play back.

Another disadvantage of magnetic and optical memory, such as DVDs, is that they require mechanical apparatus to spin and access the disks. These are cumbersome, increase amount power consumption and make for larger and heavier equipment. They are also prone to access errors if nudged and moved suddenly. This is especially true for portable apparatus.

To overcome these problems anti-knock circuitry can be employed. However, this increases the bill of materials, increases manufacturing time and ultimately the overall system cost. It is a goal of the present invention to implement multimedia apparatus with a smaller volume, a reduced bill of materials and reduced power consumption.

Due to the large file size of recorded video, these files need to be transmitted in real time by a broadcasting organization. This process can take several hours and consequently results in full occupation of the available allocated spectrum. In a similar fashion, the Internet is used by many people to transfer and gain access to large documents. Even though available word processing and desktop publishing systems provide a certain degree of data compression, the resulting files can still be very large. To avoid long download times, new modulation I demodulation methods have been developed to allow better use of the available bandwidth of telephone lines. These modulation -demodulation methods include the so called Asymmetrical Digital Subscriber Line (ADSL) modems, which allow data transfer rates of up to and in excess of 8 Megabits per second over a single Internet connection. Newer version of the ADSL modem technology (ADSL2+) can increase the data transfer rates. In an Asynchronous Transfer Mode (ATM) broadband system traffic is graded and allocated to channels based on the nature of the data to be transferred. This is referred to as the Quality of Service (QoS) for a particular traffic channel. For example, real time voice data will require a high priority channel with a low cell delay variation and cell delays for each link in an end-to-end communication system. Otherwise, data would be lost and this would be unacceptable to the users. Likewise, electronic mail messages doesn't require such stringent traffic parameters and can be transmitted as low priority cells and or channels.

However, as more and more data is transferred across a communication network the allocation of channels and network resources can affect the transition of real time traffic and result in dropped calls or temporary loss of data. If large data files could be compressed in such a way that the resulting compressed files were much smaller, then the transfer of these file across the Internet or other communication channel would take less time and be less of a burden on the communication network resources. These network resources include digital switches, servers, routers, bridges, modems and transmission links.

Prior art attempts to implement data compression tend to be application specific and depend on the data type. For example, compression methods for audio are different to those for video. They also tend to be based on transforming time domain samples into frequency domain samples. This is the case for Discrete Cosine Transform (DCT) or the Discrete Wavelet Transform. Sperschneider, et al. (6,975,254) describes methods and devices for coding or decoding an audio signal or bit stream in which a block of discrete-time samples of the audio signal is transformed into the frequency domain. Shirouzu, et al. (6,510,251) describes a method for implementing wavelet compression and decompression. Brown (6,687,4 10) presents a compression system that employs quantization codes that are proportional to the logarithm of the magnitude of the range quantized and is therefore a lossy compression system. The above-mentioned prior art are relatively new, but they still rely on time to frequency transformation, provide lossy method of compression and still result in large compressed files.

As a consequence, a need remains for a new form or type of data compression and decompression, which effectively and efficiently compresses data in such a way that the resulting compressed file only requires a small amount of data. This can be achieved by representing a particular data stream using a mathematical function or functions.

In view of the forgoing, it is a goal of the present invention is to provide a universal compression and decompression method that can be applied to a range of data types, such as text documents, audio data and video data.

Another goal of the present invention is to reduce the memory storage requirement needed to store a compressed data file. In doing so, this goal would include removing the need for employing magnetic and or optical memory storage means and replace them with solid-state compression and decompression means. This would reduce system size, the bill of materials, manufacturing time, testing time, packaging costs, transportation costs and overall system costs. As a result, systems employing the solid-state compression and or decompression means would be more reliable and less prone to errors.

Yet another goal of the present invention is to reduce the memory storage requirements of computer systems and provide quicker control program caching times.

SUMMARY

One way to represent a mathematical function is to use a polynomial. There are several ways to achieve this using digital logic circuitry. A convenient logic circuit for implementing a polynomial is a configuration known as a Liner Feedback Shift Register (LFSR). A basic LFSR consists of 3 components, namely the input sequence (initialization vector), the feedback polynomial (tap sequence) and the output. The feedback generally provides a linear relationship between the input and the output. The term characteristic polynomial is also used mean the tap sequence for a particular linear feedback shift register configuration. The tap sequence of an LFSR can be represented as a polynomial modulo 2 called a feedback polynomial. The terms feedback polynomial and characteristic polynomial are freely interchangeable in this document.

Linear feedback shift registers can be implemented in two ways. The Fibonacci implementation consists of a simple shift register in which a binary-weighted modulo-2 sum of the taps is fed back to the input. The Galois implementation consists of a shift register, the contents of which are modified at every step by a binary-weighted value of the output stage. When implemented in hardware, modulo-2 addition is performed with exclusive-OR (XOR) gates. An advantage of the Galois implementation is that it is generally faster than the Fibonacci in hardware due to the reduced number of gates in the feedback loop.

A Linear Feedback Shift Register has several properties that make ideal for generating data sequences. They are simple and make efficient use of logic hardware, have large periods, they have good statistical properties and allow easy analysis using algebraic techniques. The algebraic techniques or shift-register synthesis techniques used by the present invention for the Recursive Data Folding Encoder (RDFE) include the Berlekamp-Massey Linear Feedback Shift Register (LFSR) shift register synthesis Algorithm, convolution attack methods, the Chinese Remainder Theorem, Maximum Likelihood (ML) Decoding on the insertion channel, Edit Distance on the Alternating Step Generator, Euclid's algorithm and the LFSR algorithm. The Berlekamp-Massey Linear Feedback Shift Register (LFSR) shift register synthesis Algorithm was disclosed by J.L. Massey in "Shift Register Synthesis and BCH Decoding", IEEE Transactions of Information Theory, Vol. IT-15, page 122, 1969, and can be used in conjunction with bit stream. F.G. Gustavson, "Analysis of the Berlekamp-Massey Linear Feedback Shift Register Synthesis Algorithm, IBM Journal of Research and Development, 20:204-12, May 1976", describes the "LFSR Algorithm" approach to LFSR Synthesis. This algorithm is similar to the Berlekamp Iterative Algorithm described in E. Berlekamp, Algebraic Coding Theory, McGraw-Hill Book Co., Inc., New York, 1968 chapter 7. These analytical techniques however are used in crypto-analysis.

The Berlekamp-Massey Linear Feedback Shift Register (LFSR) shift register synthesis Algorithm is an efficient algorithm that produces one of the shortest linear feedback shift registers (LFSR) that will generate a given input bit sequence. This is also known as determining the linear complexity of a finite binary sequence fl of length n. It is also referred to as taking a sequence of elements from a field and finds the shortest linear recurrence (or linear feedback shift register) that can generate the sequence.

For example, for the short binary sequence fl 0, 0, 1, 1, 0, 1, 1, 1, 0 of length n = 9 is found by the Ber1ekamp-Massey Algorithm to have a linear complexity of 5 and an LFSR that generates it being (5, 1 + D + D5). The term 1 + D3 + D5 is also referred to herein as the feedback polynomial.

Before progressing any further several terms need to be defined in relation to LFSRs and polynomials. We define the characteristic polynomial of an LFSR as the polynomial, f (x) = cO + clx + + cn-1 x + x n IxI where cn = 1 by definition. From the characteristic polynomial, the period of the LFSR can be determined even without knowledge of the input sequence. An irreducible polynomial of degree n has a period, which divides 2 -1. In particular, an irreducible polynomial of degree n whose period is 2 -1 is a primitive polynomial. The linear complexity of a sequence is the length of the shortest LFSR, which can produce that sequence. The measure therefore indicates the difficulty of generating, and analyzing, a particular sequence. We denote Lk({si}i >=o) to be the linear complexity of the sequence So, Si, ., Sk-1, and c(x) to be the characteristic polynomial of an Lk-stage LFSR that generates S1, 0

All input sequences are assumed to be binary sequences. Let S denote an infinite sequence whose terms are So; S1; S2; ; S' denotes a finite sequence of length n whose terms are So; S; .... ; An LFSR is said to generate a sequence S if there is some initial state for which the output sequence of the LFSR is S. Similarly, an LFSR is said to generate a finite sequence 5fl if there is some initial state for which the output sequence of the LFSR has S" as its first n terms. The linear complexity of an infinite binary sequence S, denoted L(S), is defined as follows; (i) if S is the zero sequence S 0, 0, 0, then L(S) 0; (ii) if no LFSR generates s, then L(S) = (iii) otherwise, L(S) is the length of the shortest LFSR that generates S. The linear complexity of a finite binary sequence s, denoted L(S), is the length of the shortest LFSR that generates a sequence having s as its first n terms. If the polynomial C(D) C Z2[D] is irreducible over Z2 and has degree L, then each of the 2L non-zero initial states of the non-singular LFSR (L,C(D)) produces an output sequence with linear complexity L. If the binary input stream or sequence is S0, S1 S_1, then the feedback is a linear function F(So, S1 S-1) or F(S)= CI.SI where C0, C1 C, are constants. Consequently, the output of the corresponding LFSR is determined by the initial values of S0, S1 S_1 and the linear recursion relationship Sk+1 (C1. Si+k), K >= 0.

The Recursive Data Folding Encoder (RDFE) of the present invention employs algebraic techniques, such as linear feedback shift register synthesis analytical methods, to extract the characteristic polynomial, feedback polynomial, linear complexity and initial value for an input data stream or a group of consecutive sample from a larger data stream. The consecutive data samples are concatenated bit-wise to form an input data stream. The bit-wise concatenation of the data samples can be formatted as big endian or little endian. This data is then formatted to form what is now referred to as a signature and appended to the next consecutive group of samples. In addition to the polynomial data, several control fields are used to form a signature. These control fields enable the Recursive Data Folding Decoder (RDFD) to extract a signature from the generated output data stream. The resulting data block is then another data sequence, which is again analyzed by the Recursive Data Folding Encoder (RDFE) to again calculate the characteristic polynomial, linear complexity and initial value for that particular data block. This recursive extracting, formatting and appending to the next group of consecutive samples is performed until all the data in the original data stream has been processed and encoded. The end result is a final formatted data block or final signature. The final signature is the result of the recursive data folding and effectively represents the compressed data stream. The data contained in the final signature represents the data needed to implement the first LFSR polynomial to generate the start of the original data stream and the next LFSR polynomial in the sequence.

The Recursive Data Folding Decoder (RDFD) is a decompression apparatus that takes the final signature as input and then recursively generates the original data stream and next formatted signature. The formatted signatures are used to implement LFSRs to generate the next sequential output data streams and the next signature. The Recursive Data Folding Decoder (RDFD) performs this data stream generation and signature extraction until all the compressed data has been decompressed and output. As different LFSR configurations will be required to generate different data streams, the LFSR circuitry must be programmable to allow the implementation of any LFSR.

Because the compressed data is represented by a function it can be represented by a small amount of data. In addition, the greater level of compression achieved by the present invention is due to the fact the results from a subsequent compression operation are combined with the next group of consecutive data samples and are recursively folded or compressed. As a result, the final signature that represents the compressed version of the original data stream only requires a small amount of data.

In another embodiment of the invention several Linear Feedback Shift Registers can be configured to form a so-called combiner. This logic circuitry combines the sequences from two LFSRs by using a third LFSR to select or multiplex between the two.

In another embodiment, Non linear Feedback Shift Registers (NLFSR) and Feedback with Carry Shift Registers (FCSR) can be used by the Recursive Data Folding Decoder (RDFD) to generate the decompressed output data stream and any intermediate signatures.

In yet another embodiment of the invention the Recursive Data Folding Encoder (RDFE) can be employed to compress a data stream generated by other compression means and the Recursive Data Folding Decoder (RDFD) can be used to decompress and output a data stream that represent a another form of compressed data stream, which is subsequently decompressed by other decompression means. This approach then allows for the use of invention in legacy systems.

Further features of the invention, its nature and various advantages will become readily apparent from the following detailed description of the invention and the embodiments thereof, from the claims and from the accompanying drawings.

According to the present invention there is provided a method and apparatus for compressing a data stream, comprising the steps of: a) selecting an optimum number of consecutive data samples from an input stream of data samples; b) use a linear feedback shift register synthesis analytical method to calculate at least the feedback polynomial and initial value for an linear feedback shift register that will generate the data stream that represents the concatenated group of consecutive data samples; c) generate a signature, the signature format comprising a plurality of data fields, the plurality of data fields including at least the feedback polynomial data, initial value data, polynomial size, cycle count, signature type, digital rights management type, sample coding type, total signature bit length; d) selecting the next consecutive group of data samples, appending these data samples to the previous signature from step ( c) to form a next data stream; e) performing the steps (a), (b), (c), and (d) until all the data samples from an input stream have been read, compressed and formatted into a final signature.

A specific embodiment of the invention will now be described by way of example with reference to the accompanying drawings in which:-Figure 1 shows a generic block diagram of a Fibonacci Linear Feedback Shift Register; Figure 2 shows a generic block diagram of a Galois Linear Feedback Shift Register; Figure 3 shows an example for the ordering and tagging of data samples for a data stream; Figure 4 illustrates the pointer naming convention for a specific group of consecutive data sample; Figure 4A illustrates a group of three consecutive zero padded data samples; Figure 4B illustrates a group of three consecutive variable length encoded data sample; Figure 4C shows how continuation signatures can be stored to form index signatures, which reference chapters in a final signature; Figure 5 shows an example analogue input waveform and the corresponding output from a staircase integrator; Figure 6 shows how groups of consecutive samples of an analogue input waveform can be represented by an offset and delta values; Figure 6A shows how the decompressed output data stream can be generated by combining two separate programmable linear feedback shift registers; Figure 6B shows how one programmable LFSR controls the clock of two other programmable LFSRs; Figure 7 shows the format for a compressed signature; Figure 8 shows an example of a formatted signature that has been appended to a group of samples; Figure 9A shows a section from the Recursive Data Folding Encoder flow diagram; Figure 9B shows a section from the Recursive Data Folding Encoder flow diagram; Figure 9C shows a section from the Recursive Data Folding Encoder flow diagram; Figure 9D shows a section from the Recursive Data Folding Encoder flow diagram; Figure 9E shows a section from the Recursive Data Folding Encoder flow diagram; Figure 9F shows a section from the Recursive Data Folding Encoder flow diagram; Figure 10 is a generic logical block diagram for a K-bit wide Fibonacci Linear Feedback Shift Register; Figure 11 illustrates a logical block diagram for a I -bit component from a programmable Fibonacci Linear Feedback Shift Register; Figure 12 is a generic logical block diagram for an N-bit programmable Galois Linear Feedback Shift Register; Figure 13 illustrates a logical block diagram for a 1-bit component from a programmable GáTlois Linear Feedback Shift Register; Figure 14 shows a logical block diagram of the main components used in a specific arrangement of the decompression apparatus; Figure 15 shows a generic block diagram of an audio encoding system using the compression apparatus; Figure 16 shows a generic block diagram of an audio player based on the decompression apparatus; The data compression and decompression apparatus comprises two main units. These are a compression unit, referred to herein as a Recursive Data Folding Encoder (RDFE) and a decompression unit, referred to herein as a Recursive Data Folding Decoder (RDFD). The Recursive Data Folding Decoder 600 effectively performs the inverse operation to the Recursive Data Folding Encoder 800 and can be independent units. The Recursive Data Folding Encoder 800 produces a formatted signature 700 that is the result of compressing a bit stream. Once all the data in a data stream has been compressed the last formatted signature 700 produced by the RDFE 800 is referred to as a Final Signature 700. During the compression process, the RDFE 800 can produce intermediate signatures 700. All the formatted signatures 700 have the same format, as shown in figure 7. The signature type field 702 identifies the different types of signatures. The final signature 700 represents the compressed data stream. It is this value that is used by the Recursive Data Folding Decoder 600 to decompress the signature and generate a data stream that is identical to the original data stream.

The Recursive Data Folding Encoder 800 can be embodied in hardware circuitry as an integrated circuit or part of an integrated circuit, in software as a program or as a combination of hardware circuitry and software. The Recursive Data Folding Decoder 600 is preferably embodied in hardware circuitry as an integrated circuit or part of an integrated circuit when the application requires that the decompressed data stream be produced in real time or at a very fast data rate. However, this does not preclude the Recursive Data Folding Decoder 600 from being implemented insoftware or a combination of software and hardware circuitry. A detailed description of the Recursive Data Folding Decoder 600 is provided later.

As shown in figure 3. consecutive data samples 721 from a complete input data stream are labelled from sample 0 to sample k-I. Each data sample 721 is a binary number. The number of bits used to represent each sample is programmable and depends on the application. For example, for video applications sample resolutions can be, but are not limited to, to between 8-bits and 16-bits. For voice and high quality audio applications each sample can be between 8-bits and 32-bits. The data stream to be compressed is formed by concatenating consecutive data sample. These can be arranged as big endian or little endian. However, once a format has been chosen it must be applied to all data samples 721. The samples 721 shown in figure 3 are Pulse Code Modulation (PCM) samples. These binary data samples 721 can be taken form a stored memory media, such as non-volatile semiconductor memory or from the output of an Analogue to Digital Converter (ADC). As described later, the data samples can -10-be taken from different forms of Analogue to Digital Converters. This enables the data samples 721 to be encoded and represented in different formats.

Figure 4 illustrates how the input data stream can be partitioned into groups of consecutive samples 720. The Next Start Pointer 730 points to the first sample 721 in a particular group of consecutive samples 720. The Next End Pointer 735 points to the last sample 721 in a particular group of consecutive samples 720. The number of samples 721 in a particular group of consecutive samples 720 can be same or it can vary. After a particular group of consecutive samples 720 has been processed, then the next sequential group of consecutive samples 720 are processed. Consequently, the Next Start Pointer 730 and the Next End Pointer 735 are updated accordingly as each new group of consecutive samples 721 are processed.

The operation of the Recursive Data Folding Encoder (RDFE) 800 will now be described in detail. The Recursive Data Folding Encoder 800 is used to compress a complete input data stream. The algorithm to compress a data stream is represented by the flow diagrams shown in figures 9A, 9B, 9C, 9D, 9E and 9F. As outlined previously, the Recursive Data Folding Encoder 800 employs analytical techniques to parse the input data stream determine which function or functions would be required to generate the input data stream. The function or functions are based on Linear Feedback Shift Registers.

In an embodiment of the invention, the algorithm used to calculate and determine the function or functions required to generate the input data stream is the Berlekamp Massey Algorithm. The Berlekamp-Massey algorithm is an efficient algorithm for determining the linear complexity of a finite binary sequence s of length n. It allows the construction of the feedback polynomial or connection polynomial for an LFSR. The output sequence generated by the LFSR will then be the same as the input data sequence of the original input data stream.

As shown in figure 9A, after the start procedure 801 of the compression or RDFE 800 algorithm, the initialisation process 802 initialises method parameters. This includes, but is not limited to, setting the Total Number of Samples Register X equal to 0, setting the Next Start Pointer equal to 0, setting the Next End Pointer equal to 0 and setting the Number Of Samples Per Segment N to 0. After the initialisation procedure 802 has been completed the next procedure is procedure 803. Procedure 803 is used to read each sample of the input data stream, encode each data sample and store each sample 721 in time order until all samples have been read and stored. These samples are labelled consecutively from 0 to X -1.

There are different ways in which the raw data samples from the input data stream can be encoded. The RDFD 600 will need to be able group decoded bits into a data sample of the correct size. To do this a data Sample Size field 705 is used. The data sample size field 705 indicates the number of bits that are used to represent each data sample. This is effectively the sample resolution. Another field, the Encoding Type field 704 indicates how the data samples 721 are encoded. In one embodiment, the data samples 721 can be encoded as Pulse Code Modulation (PCM) data sample. As all the samples must have the same number of bits, any data samples with a value less than (2"N -1)/ 2 will need to be zero extended.

This is shown in figure 4A. Here three consecutive data samples 721 have been PCM encoded 723. The encoded data samples 723 in figure 4A have a resolution of 8-bits. The first data sample has a value of 7 and is zero extended with 5 binary zeros. The second encoded data sample 723 has a value of 23 and therefore is zero extended with 3 binary -11 -zeros. The third encoded data sample 723 has a value of 151. This encoded data sample does not require any zero extension, as the most significant bit is a binary one.

One of the disadvantages of PCM encoding the data samples 721 is that all the samples will have the same number of bits. For small values, this means many binary zeros are added to the data stream for compression. One way around this is to employ variable length encoding.

In another embodiment, the input data samples 721 and variable length encoded. An example of the resulting encoded data samples 723 of using this technique are shown in figure 4B. For variable length encoding, each encoded data sample 723 is made up of two appended components. The first component is a fixed length field 722, which indicates the size of the associated data sample in bits. The second component or field is the actual data sample 721. In figure 4B, the first encoded data sample 723 contains a 3-bit sample size field 722 and a 3-bit data sample 721. The value of the 3-bit sample size field is 3. This indicates that the appended data sample 721 has 3-bits. The second encoded data sample 723 has a 3-bit sample size 722 of 5 (101 in binary). This indicates the appended data sample 721 is 5-bits wide. The value in this example is 23 or 10111 in binary. The third encoded sample has a sample size 722 of 7 (111 in binary). This indicates the appended data sample 721 is 7 bits wide. The value in this example is 75 or 1001011 in binary.

In yet another embodiment, the input data stream can be converted to data samples using delta modulation or differential PCM. This reduces the size of the data stream for compression as it makes use of a 1-bit code. The difference between PCM and delta modulation is that in the former the instantaneous amplitude of an input data stream is input to the RFDE 800 as an N-bit digit code, whereas in the delta modulation method the rate of change of input signal amplitude is input to the RFDE 800. Figure 5 show an analogue input signal 730 and the corresponding output 731 from a staircase integrator.

In yet another embodiment, the delta-sigma modulation or conversion can be used to generate the digital data samples 721 required by the RFDE 800 for compression. The delta-sigma converter also generates a 1-bit code, but the instantaneous amplitude is generated.

Encoding the input data samples using any of the methods outlined above provides means for the RFDD 600 to identify the boundaries of each sample and recover the original data stream. The method of encoding is indicated by the value in the Encoding Type field 704 of a formatted signature 700. Though three methods of analogue to digital conversion have been described to generate the digital input data stream, this does not preclude other methods of performing analogue to digital conversion and or generating an input data stream for input and compression by the RFDE 800.

The next step is procedure 804, which determines if the Total Number Of Sample (X -1) is less than or equal to the 2 A (K -1). If the result is positive (YES), then the algorithm jumps to procedure 805. This is shown in figure 9B and represented by flow B on the flow diagram. If the result is negative (NO), then the algorithm proceeds to procedure 810. This is shown in figure 9C and represented by flow A on the flow diagram. The reason for implementing procedure 804 is that if the Total Number Of Samples is less than the value 2 A (K -1), then only one iteration of the algorithm is required as the size of LFSR is adequate to generate the original data sequence. If the Total Number Of Samples is greater than the value 2 A (K -I), then more than one iteration of the algorithm is required to compress and encode the input data stream.

-12 -If flow B is taken the flow diagram shown in figure 9B is executed. Procedure 805 is used to set the parameter N = Total Number Of Samples X. The next procedure 806 is to set the parameters NSP = 0 and NEP = (X -1). Procedure 807 is then executed, which implements the Berlekamp Massey Algorithm. Procedure 807 therefore calculates the characteristic polynomial for the sequence of X samples 721, the linear complexity and the initial vale of the LFSR. The values output from procedure 807 are input to procedure 808, where the initial value, characteristic polynomial of the generator LFSR and the sample count N are stored. Procedure 809 takes the initial value, characteristic polynomial of the generator LFSR and the sample count N, together with other control data and uses this data to generate the final signature 700. The final signature 700 is output and stored in memory means before executing procedure 850. Procedure 850 is used to terminate the compression and encoding algorithm as all the data from the input data stream has been encoded.

The formatted signature 700 consists of several different fields. The signature format 700 is shown in figure 7. The signature length field 701 indicates the total bit size of the signature 700. The signature type field 702 is used to indicate the signature type of the current signature 700. A signature can take three different forms. A signature 700 can be an initial signature, a continuation signature or a final signature. These are explained in more detail later. The Digital Rights Management (DRM) control field 703 is used to indicate which, if any, type of encryption and authorization protocols have been used to generate the input data stream. The Polynomial Size field 706 indicates the number of bits or bit width of the LFSR.

This value is the maximum width for an LFSR used in the compression process. During the compression process the RDDE 800 may calculate a generator LFSR whose bit width less than the value given in the Polynomial Size field 706. The LFSR Tap Vector field 707 is used to configure the generator LFSR by selecting, which feedback taps are selected. The Polynomial Initial Value field 708 is value that is loaded into the LFSR at the start of each LFSR output sequence iteration. The Cycle Count field 709 indicates the number of clock cycles the LFSR is clocked to generate the output sequence. The Cycle Count field 709 is valid for each output sequence iteration.

If flow A is taken the flow diagram shown in figure 9C is executed. The next procedure is procedure 810 in which a value for N is selected. The value N represents a group of N consecutive samples 720. After selecting N, procedure 811 is executed. Procedure 811 is used to set the value of the Next Start Pointer 730 to 0 and the Next End Pointer 735 to a value of (N -1). The next procedure is procedure 812, which implements the Berlekamp Massey Algorithm. Procedure 812 therefore calculates the characteristic polynomial for the group of consecutive N samples 720, the linear complexity and the initial vale of the generator LFSR. The values output from procedure 812 are input to procedure 813, where the initial value, characteristic polynomial of the generator LFSR and the sample count N are stored. Procedure 814 takes the initial value, the characteristic polynomial of the generator LFSR and the sample count N, together with other control data and uses this data to generate a signature 700. The signature 700 is then stored in memory means for future use by subsequent procedures of the encoding algorithm. Procedure 815 determines if the produced characteristic polynomial is optimal. If it is not optimal a jump is back to procedure 810. If it is optimal then the next procedure in the algorithm in procedure 816.

This is indicated by flow C in the flow diagram in figure 9D.

Procedure 816 is used to update the value of parameter Z. The value of Z is set to equal the number of remaining samples after a group of consecutive samples 720 has been processed.

The next procedure is procedure 817. Procedure 817 performs a mathematical division and -13-test on the result. The parameter Z is divided by parameter N and a test is performed on the quotient. If the value of the quotient is greater than zero then the next procedure to be executed is procedure 818, else the next procedure is procedure 826. The jump to procedure 826 from procedure 817 is depicted by the flow D in figure 9D. If the value of the quotient from procedure 817 is greater than zero, then there must be at least N more samples to be processed. Consequently, procedure 818 is used to update the Next Start Pointer 730 and the Next End Pointer 735 accordingly. Procedure 819 is then the next procedure and takes the next group of N consecutive sample 720 pointed at by the Next Start Pointer and the Next End Pointer and appends them to the previous stored signature 700. The configuration for the concatenation of the next group of N samples 720 and the appended previous signature 700 is shown in figure 8. This concatenation of the previous signature 700 and the next group of N samples now represents a new sequence of consecutive samples. This new group of consecutive samples is passed to procedure 820, which implements the Berlekamp Massey Algorithm. Procedure 820 therefore calculates the characteristic polynomial for the group of consecutive N samples 720, the linear complexity and the initial vale of the generator LFSR. The values output from procedure 820 are input to procedure 821, where the initial value, characteristic polynomial of the generator LFSR and the sample count N are stored. Procedure 822 takes the initial value, the characteristic polynomial of the generator LFSR and the sample count N, together with other control data and uses this data to generate a signature 700. As there are more data samples to be processed, this signature 700 is referred to as a continuation signature. The continuation signature 700 is then stored in memory means for future use by subsequent procedures of the encoding algorithm.

Procedure 823 determines if the produced characteristic polynomial is optimal. If it is not optimal then procedure 825 is implemented in which a new value of N is selected.

Procedures 823, 824 and 825 are optional and do not have to be implemented. From procedure 825 a jump back to procedure 816 is made. If it is optimal then a new value of N is selected in procedure 825. From here a jump is made to the input of procedure 817.

If the value of parameter Z, calculated by performing procedure 817, is not greater than zero then the next procedure to be executed is procedure 826. Procedure 826 performs another division and test operation. The parameter Z is divided by parameter N and a test is performed on the remainder. If the value of the remainder is greater than zero then the next procedure to be executed is procedure 827, else the next procedure is procedure 833. The jump to procedure 833 from procedure 826 is depicted by the flow E in figure 9E. If the value of the remainder from procedure 826 is greater than zero, then there must be at least (N -1) more samples to be processed. A jump to procedure 833 indicates that there are no more samples to be processed. Therefore, procedure 833 is used to convert the previous derived initial value, the characteristic polynomial of the generator LFSR and the sample count N, together with other control data and uses this data to generate a final signature 700.

The final signature 700 is then stored in memory means for future. As the final signature 700 has been calculated by the RDFE 800 the compression and encoding algorithm is complete and the next procedure 850 is used to terminate the algorithm. Figure 9F shows procedures 833 and 850.

Procedure 827 is used to update the value of N to equal the remainder from procedure 826.

The next procedure is procedure 828. Consequently, procedure 828 is used to update the Next Start Pointer 730 and the Next End Pointer 735 accordingly. Procedure 829 is then the next procedure and takes the next group of N consecutive sample 720 pointed at by the Next Start Pointer and the Next End Pointer and appends them to the previous stored signature 700. The configuration for the concatenation of the next group of N samples 720 and the -14 -appended previous signature 700 is shown in figure 8. This concatenation of the previous signature 700 and the next group of N samples now represents a new sequence of consecutive samples. This new group of consecutive samples is passed to procedure 830, which implements the Berlekamp Massey Algorithm. Procedure 830 therefore calculates the characteristic polynomial for the group of consecutive N samples 720, the linear complexity and the initial vale of the generator LFSR. The values output from procedure 830 are input to procedure 831, where the initial value, characteristic polynomial of the generator LFSR and the sample count N are stored. Procedure 832 takes the initial value, the characteristic polynomial of the generator LFSR and the sample count N, together with other control data and uses this data to generate a final signature 700. The final signature 700 is then output and stored in memory means. As the final signature 700 has been calculated by the RDFE 800 the compression and encoding algorithm is complete and the next procedure 850 is used to terminate the algorithm.

The final signature 700 now represents the compressed input data stream. To extract the original data stream from the final signature 700 decompression apparatus is required. The Recursive Data Folding Decoder 600 effectively performs the inverse operation to the Recursive Data Folding Encoder 800. At the heart of the Recursive Data Folding Decoder 600 is a programmable LFSR 650.

The algorithm depicted in figures 9A to figure 9F take the input data samples 725 and store them in memory before starting the compression process. Groups of consecutive data samples 720 are processed in reverse chronological order, that is the last group to be stored in memory are processed first. This allows the Recursive Data Folding Encoder 800 to compress the input data stream in one pass. A simple example of this process is shown in figure 4. The first group of N consecutive samples 720 to be processed are pointed at by the Next Start Pointer 730, shown as NSP_0 in figure 4 and the Next End Pointer, shown as NEPO in figure 4. The processing or compression order is then (NSP1, NEP1), (NSP2, NEP_2), (NSP_3, NEP_3), with the group of consecutive samples (NSP_4, NEP_4) being processed last by the Recursive Data Folding Encoder 800.

In another embodiment, the order in which the groups of consecutive data samples 720 are processed and compressed is different. This embodiment is useful when the total amount of input data stream storage is limited. In this embodiment the overall compression algorithm required to generate the final signature 700 is performed in two stages. In this embodiment the input data stream 725 is processed in time order. In the first stage of compression (not shown), the first group of consecutive data samples 720 to be compressed would be the first group of data sample 721 received by the Recursive Data Folding Encoder 800. In the first stage of compression, the first group of N consecutive samples 720 to be processed are pointed at by the Next Start Pointer 730, shown as NSP_4 in figure 4 and the Next End Pointer, shown as NEP_4 in figure 4. The processing or compression order is then (NSP_3, NEP3), (NSP_2, NEP2), (NSP1, NEP1), with the group of consecutive samples (NSPO, NEPO) being processed last by the Recursive Data Folding Encoder 800.

However, when a group of N consecutive data samples has been processed to generate a signature 700, the signature 700 is stored separately in memory means (not shown). In the second stage of compression each of the stored signatures 700 are then concatenated in time order to form a new data stream. The Recursive Data Folding Encoder 800 then views this new data stream as any other and compresses it as before to generate the final signature 700.

An embodiment of the Recursive Data Folding Decoder 600 can decompress this two stage final signature 700. A final signature 700 that is compressed using the two-stage compression algorithm is identified by a code in the signature type field 702. The Recursive Data Folding Decoder 600 allowing it to perform the correct decompression algorithm

decodes the signature type field 702.

Another advantage of performing a two-stage type compression is that it allows an index of signatures to be formed. This is useful when very large files have been compressed and a user wishes to quickly jump to a new section. For example, if the compressed data file represented a compressed video or movie and a user wished to "fast forward" to a later scene the user could either make the Recursive Data Folding Decoder 600 run at faster clock rate allowing the decompression to speed up, or they could use an index of signatures that are stored with the final signature to point to a new chapter or scene. This arrangement is shown in figure 4C. In the example shown in figure 4C, groups of consecutive data samples 720 are also labeled as Chapter 0 to Chapter (L -1). As each group of N consecutive data samples 720 are processed or compressed a continuation signature 700 is generated. In the one stage compression algorithm these signatures are appended to next group of consecutive data samples. In the embodiment, this is also the case, however, the continuation signature is also stored separately in memory means (not shown). These continuation or intermediate signatures 700 represent the data stream compressed so far. As a result they can be decompressed individually by the Recursive Data Folding Decoder 600 to output the data stream compressed thus far. By generating and storing individual signatures 700 for each group of consecutive data samples 720 an index of signatures can be generated. Storing these with a final signature would allow a user (via the Recursive Data Folding Decoder 600) to quickly select and access any chapter of compressed data. For even greater compression, the index signatures 700 can be concatenated to form a new data stream and these could be compressed to form a final signature 700 that was a final signature of index signatures.

Though the Berlekamp-Massy algorithm has been described to determine the initial state and feedback polynomial for an input data stream 720, this does not preclude the use of any other analytical method for determining the initial state and feedback polynomial for an input data stream 720. Other methods include correlation attack methods, cross correlation methods, especially when they are combined with the Walsh-1-Tadamard Transform to compute simultaneously the cross correlation between (ce) and the outputs of all possible initial states of the given register. In another embodiment, the Recursive Data Folding Encoder 800 can employ any of these analytical methods to determine the initial state and feedback polynomial for an input data stream 720 and therefore use this information to "construct" a linear feedback shift register that would produce the same input data stream or sequence.

In yet another embodiment (not shown), data samples from individual data channels in a multi-channel system can be compressed individually. In such an arrangement, a linear feedback shift register would be provided to decompress each final signature. Each of the Recursive Data Folding Decoders 600 would be synchronized with each other to ensure correct output stream timing.

In yet another embodiment (not shown), data samples from individual data channels in a multi-channel system can be compressed as a single input data stream. In such an arrangement, the Recursive Data Folding Decoder 600 would separate each output data sample and pass it to the correct output channel at the correct time interval.

Figure 6 shows how an input waveform 730 can be represented by a sample that represents and offset value 732 and a plurality of subsequent samples that represent the deltas 733 or differences from the offset values. One of the advantages of this encoding method is that it reduces the number of bits to represent the input data stream.

As mentioned previously, Linear Feedback Shift Registers (LFSR5) can be implemented in two ways. The Fibonacci implementation 100 consists of a simple shift register in which a binary-weighted modulo-2 sum of the taps is fed back to the input. Figure 1 shows a generic logical block diagram of a Fibonacci implementation 100. The Fibonacci implementation comprises one or a plurality of register or flip-flop means 110, labelled as 11 OA through liON in figure 1 (individually and collectively referred to as register means 110). The output from each register means 110 connects to a switch means 120, labelled as 120A through I 20N in figure 1.The binary-weighted modulo-2 sum of the switch outputs 120 or taps that is fed back to the input for the first stage register 11 OA is implemented using exclusive or gates 130. The output from a switch means 120 is programmable. If a switch 120 is open then the output from the corresponding register 110 is not feedback. In fact, the output of the switch means is then set to logic zero. If a switch 120 is closed then the output from the corresponding register 110 is feedback to the exclusive or gate 130. Consequently, by changing the open and closed positions of the switching means 1 20A -1 20N different LFSRs can be implemented using the same logic circuitry means. The LFSR is then referred to as a programmable LFSR 650. In all cases, the output from the last register, shown as register lION in figure 1 is always feedback to the input of the exclusive or gate 130. The exclusive or gate 130 can be implemented as one N input exclusive or gate or several smaller exclusive or gates having fewer inputs. However, the overall logical function is the same.

The Galois implementation 200 consists of a shift register, the contents of which are modified at every clock cycle by a binary-weighted value of the output stage. When implemented in digital hardware, the modulo-2 addition is performed with exclusive-OR (XOR) gates. Figure 2 shows a generic logical block diagram of a Galois implementation 200. The Galois implementation 200 comprises one or a plurality of register or flip-flop means 210, labelled as 21 OA through 21 ON in figure 2 (individually and collectively referred to as register means 210). The input to each register means 210 is the exclusive or of the output from the previous register and the output from the switch means 260, labelled as 260A through 26ON in figure 2 (individually and collectively referred to as register means 260). The input to each switch means 260 is the output 23OA from register 21 OA. The input 240 to each register means 210 are labelled as 24OA through 21 OM in figure 2 (individually and collectively referred to as register means 240). The output 230 to each register means 210 are labelled as 23OA through 23ON in figure 2 (individually and collectively referred to as register means 230). The output from the switch means 260 are labelled as 25OA through 25ON in figure 2 (individually and collectively referred to as register means250). The exclusive or means are shown as 2 input exclusive or gates 220, labelled as 22OA through 22OM in figure 2 (individually and collectively referred to as register means 220). The output 250 from a switch means 260 is programmable. If a switch 260 is open then the output 250 is then set to logic zero. If a switch 260 is closed then the corresponding output 250 is equal to the input to the switch means, which is the output 23OA from register 21OA.

The last register, labelled as register 21 ON in figure 2 will always have its corresponding switch means 26ON closed. Consequently, the input to register 21 ON is the output from -17- register 210A. By changing the open and closed positions of the switching means 260A - 260N different LFSRs can be implemented using the same logic circuitry means. The LFSR is then referred to as a programmable LFSR 650. One advantage of the Galois implementation is that it is generally faster than the Fibonacci in hardware circuitry due to the reduced number of gates in the feedback loop.

In one embodiment the programmable LFSR 650 can be implemented as a Fibonacci LFSR.

In a preferred embodiment the programmable LFSR 650 can be implemented as a Galois LFSR.

A preferred embodiment of the Recursive Data Folding Decoder 600 is shown in figure 14.

The control section 610 interfaces to all the other sections and is used to control and transfer data to and from the various sections. The master clock 611 is input to the control section 610 and is used to clock all the control section's logic. The clock signal 620 that is output from the control section is derived from the master clock 611. The programmable LFSR is clocked at such a rate that no aliasing effects are produced for the particular application the Recursive Data Folding Decoder 600 is employed. The clock rate will also be at such a rate as to minimize any distortion affects for the particular application the Recursive Data Folding Decoder 600 is employed. The master reset 612 is input to the control section 610.

This signal is used to initialize the control section and put its logic into a known state at either power on or if the apparatus 600 is reset. The reset signal 622 that is output from the control section 610 is derived from the master reset 612. The display means 680 is used to display a range of information. This includes data typed in via the keyboard means 681, data read from the memory means 682, data from the internal interface means 683 and control and status information generated by any of the control processes performed by the control section 610. Data to be displayed on the display means 680 is transferred to the display means from the control section 610 via interface means 628. Data entered using the keyboard means 681 is transferred to the control section 610 via the interface means 626.

The memory means 682 can be volatile semiconductor means, or non-volatile semiconductor means, magnetic memory means, optical memory means or any combination of these memory means. Data is transferred between the memory means 682 and the control section 610 via interface means 626. The memory means can be used to store the control programs that implement the Recursive Data Folding Decoder algorithms, as shown in figures 9A -9F, and one or a plurality of final signatures 700. The external interface 683 allows data to be transferred to and from a range of peripheral equipment (not shown). This configuration allows final signature data 700 that is stored on peripheral equipment to be loaded into the RDFD 600 apparatus. The final signature data that is transferred from the peripheral equipment can be loaded directly for immediate decoding or decompression by the control section 610 or be stored in the memory means for later use. The external interface circuit means communicates with peripheral equipment means via interface means 684. The control section 610 communicates with the external interface 683 using the control bus interface means 625 and the bi-directional data bus interface means 624.

For data to be decompressed, the final signature 700 that represents the compressed data needs to be loaded into the programmable LFSR 650. As shown in figure 7, a signature 700 contains several fields. A user selects which final signature 700 they wish to decode. The selection can be entered via the keyboard means 681 or be read from the memory means 682. Once a user has decided which final signature 700 needs to be decompressed or decoded the control section 610 first resets the polynomial initial value shadow register 630, the polynomial initial value register 640, the programmable LFSR 650, the programmable -18-LFSR tap selection register 660 and the programmable LFSR tap selection shadow register 670.

The control logic 610 then loads the polynomial initial value shadow register 630 with the value contained in the polynomial initial value field 708. The data can be loaded in parallel or serially. When loaded in parallel the polynomial initial value is output via the Data Out bus 623 and input to the polynomial initial value shadow register 630. The value is loaded into the registers on the next clock cycle when the Initial Value Register Load signal (not shown) is active. If the data is loaded serially, a bit stream is output from the Data_Out pin 623 and input to the polynomial initial value shadow register 630. The polynomial initial value shadow register 630 is a shift register and so data is shifted bit by bit on each clock cycle when the Initial Value Register Shift (IVR_Shift signal 613) is active. The output of the polynomial initial value shadow register 630 is input to the polynomial initial value register 640 via the data bus 631. The value on the polynomial initial value shadow register output data bus 631 is loaded into the polynomial initial value register 640 on the next clock cycle when the IVR_LOAD signal 614 is active.

In a similar fashion, the programmable LFSR tap selection shadow register 670 is loaded with the value contained in the polynomial LFSR tap vector field 707. The data can be loaded in parallel or serially. When loaded in parallel the programmable LFSR tap vector is output via the Data_Out bus 623 and input to the programmable LFSR tap selection shadow register 670. The value is loaded into the registers on the next clock cycle when the Programmable LFSR Tap Selection Shadow Register Load signal (not shown) is active. If the data is loaded serially, a bit stream is output from the Data_Out pin 623 and input to the programmable LFSR tap selection shadow register 670. The programmable LFSR tap selection shadow register 670 is a shift register and so data is shifted bit by bit on each clock cycle when the Tap Shadow Register Shift (TSR_Shift signal 621) is active. The output of the programmable LFSR tap selection shadow register 670 is input to the programmable LFSR tap selection register 660 via the data bus 671. The value on the programmable LFSR tap selection register output data bus 671 is loaded into the programmable LFSR tap selection register 660 on the next clock cycle when the TSR_LOAD signal 619 is active.

The TSR_LOAD signal 619 is the Tap Selection Register Load signal 619.

The programmable LFSR tap vector output from the programmable LFSR tap selection register 660 is input into the programmable LFSR 650 on the programmable LFSR tap selection output data bus 661. The polynomial initial value output from the polynomial initial value register 640 is input into the programmable LFSR 650 on the polynomial initial value register output data bus 641. The reason for implementing the programmable LFSR tap selection shadow register 670 and the polynomial initial value shadow register 630 is that they form double buffers and allow these registers to be loaded with data from the control logic 610 while their respective operational registers 660 and 640 are driving the programmable LFSR 650. This double buffering allows the programmable LFSR 650 to be re-programmed in a single clock cycle. This reduces any interruption to the data output stream. The polynomial initial value output 641 is first selected as an input to the individual programmable LFSR registers when the Initial Value Select (IV_SELECT) signal 617 is active. The polynomial initial value is loaded into the programmable LFSR registers on the next clock cycle. The clocking to the flip-flops is controlled by the LFSR_ENABLE signal 616. When the LFSR_ENABLE signal 616 is active data present at the flip-flop 420, 520 input is clocked into the flip-flop and appears at the output. When the LFSR_ENABLE signal 616 is disabled data present at the flip-flop output remains in the same state. The loading of the programmable LFSR will be explained in more detail later.

Once the programmable LFSR 650 has been loaded with the values for the final signature 700, the control logic clocks the programmable LFSR using clock signal 620 a predefined number of times. The number of clock cycles is determined by the value contained in the cycle count field 709 of the final signature 700. Every clock cycle data is output on output bus 618 from the programmable LFSR 650. This data is the decompressed data of the original compressed data stream. This data is also input to the control logic 610 for further processing, analysis and display. The control logic 610 implements a cycle count counter (not shown), which enable the control logic to determine when the predefined number of clock cycles has been implemented. Part of the output data will be the next signature 700.

The control logic can determine the size and field boundaries of the next signature 700 from the size fields of the signature. The length field 701 contains the total length in bits of the signature 700. The logic to implement this feature is not shown. The various fields from the next signature 700 can therefore be stored and loaded into their respective shadow registers as the current signature is being processed.

Once the predefined number of clock cycles has been performed the control logic will then load the next signature values into the programmable LFSR 650. This can be performed in a single cycle so there is a seamless transition (continuous data stream) at the data output 618.

This process of loading a signature 700, configuring the programmable LFSR 650, clocking the programmable LFSR 650 a predefined number of times to output a data stream is repeated until the Initial Signature 700 has been loaded and processed. The control logic 610 determines the signature 700 type from the signature type field 702.

In one embodiment the programmable LFSR 650 can be implemented as a programmable Fibonacci LFSR. Figure 10 shows a generic logical block diagram for an K-bit wide programmable Fibonacci Linear Feedback Shift Register. The K-bit wide programmable Fibonacci Linear Feedback Shift Register 650 is constructed from one or a plurality of programmable 1-bit components means 400, labelled as 400A through 400N in figure 10 (individually and collectively referred to as register means 400). Figure 11 illustrates a logical block diagram for a programmable 1-bit component 400 from a programmable Fibonacci Linear Feedback Shift Register. The initial value output data bus comprises one or a plurality of individual signals or wire 641, labelled as 641A through 641N in figure 10 (individually and collectively referred to as register means 641). The LFSR Tap Selection vector comprises one or a plurality of individual signals or wire 661, labelled as 661 A through 66lN in figure 10 (individually and collectively referred to as register means 661).

The output from an individual programmable 1-bit component 400, are labelled as 41 OA through 41 ON in figure 10 (individually and collectively referred to as register means 410).

The output 410 from an individual 1-bit component 400 is connected to the input 411 of the next consecutive I -bit component 400. The input to an individual programmable 1-bit component 400, are labelled as 411A through 41 iN in figure 10 (individually and collectively referred to as register means 411). The final stage output 618 is a signal wire that outputs the decompressed data stream. The feedback output from an individual programmable 1-bit component 400, are labelled as 403A through 403N in figure 10 (individually and collectively referred to as register means 403). The feedback input to an individual 1-bit component 400, are labelled as 405A through 4O5N in figure 10 (individually and collectively referred to as register means 405). The feedback output 403 from an individual 1-bit component is connected directly to the feedback input of the previous 1-bit component. The special case if for the i-bit component labelled 400A, for which the feedback output 403A is connected directly to the feedback input 41 1A. The control bits from the LFSR Size Register (not shown), are labelled as 41 5A through 41 5N in figure 10 (individually and collectively referred to as register means 415). The LFSR Size refers to the number of 1-bit components 400 used to form a particular LFSR configuration.

As the size of a programmable LFSR configuration can be less than the maximum number of 1-bit components 400 used to implement a programmable LFSR 650, then the feedback signal from the relevant most significant 1-bit component 400 needs to be selected and feedback. The feedback output 403 is derived from the output of the 2 input exclusive or gate 421. Exclusive or gate input 413 is derived from the 2 to 1 multiplexer means 424. If the feedback output 410 needs to be feedback to other 1-bit components 400 then the control bit 661 from the programmable LFSR tap selection register 660 is set to route the feedback output signal 410 through the multiplexer 424 to output 413. If the feedback output 410 is not required to be feedback, then the control bit 661 from the programmable LFSR tap selection register 660 is set to select the logic zero input to the input of the exclusive or gate 421. Multiplexer means 423 are used to route the feedback input 405 from the next significant stage to the other input 412 of the exclusive or gate 421. Multiplexer means 423 is controlled by a bit 615 from the LFSR Size Register (not shown). If the 1-bit component 400 is the most significant stage in a particular configuration of a programmable LFSR 650, then the control bit 615 is used to select the logic zero input. This ensures that the feedback output 403 is that of the most significant I-bit component 400.

Each I-bit component 400 contains a register or flip-flop 420. The flip-flop 420 is clocked by clock 401 and can be reset using the reset signal 402. The flip-flop means 420 can be any type of flip-flop, such as a J-K flip-flop or D type flip-flop. In this example the reset signal is active low. The reset can be synchronous or asynchronous. The flip-flop 420 can be loaded with the value output from the multiplexer means 422, which is controlled by the IV_SELECT signal 617. When an initial value needs to be loaded the IV_SELECT signal 617 is used to route the initial value bit 641 to the input of the flip-flop 420. On the next clock cycle the input data is registered and appears at the flip-flop output 410. The other input to the multiplexer means 422 is the output 411 from the previous 1-bit component 400.

When the programmable LFSR 650 is operational and outputting the decompressed data stream, the IV_SELECT signal 617 is disabled. In this state, the input to the flip-flop 420 is the signal that appears on the input 411. Consequently, by setting the state of select signals for each of the multiplexers used in each of the 1-bit components 400, a programmable LFSR 650 can be implemented. This programmable LFSR can then implement any N-bit LFSR.

In another preferred embodiment the programmable LFSR 650 can be implemented as a programmable Galois LFSR. Figure 12 shows a generic logical block diagram for a K-bit wide programmable Galois Linear Feedback Shift Register. The K-bit wide programmable Galois Linear Feedback Shift Register 650 is constructed from one or a plurality of programmable I bit components means 500, labelled as 500A through SOON in figure 12 (individually and collectively referred to as register means 500). Figure 13 illustrates a logical block diagram for a programmable 1-bit component 500 from a programmable Galois Linear Feedback Shift Register.

The K-bit wide programmable Galois Linear Feedback Shift Register 650 is constructed from one or a plurality of programmable 1-bit components means 500, labelled as SOOA through 500N in figure 12 (individually and collectively referred to as register means 500).

Figure 13 illustrates a logical block diagram for a programmable 1-bit component 500 from a programmable Galois Linear Feedback Shift Register. The initial value output data bus comprises one or a plurality of individual signals or wire 641, labelled as 641A through 641N in figure 12 (individually and collectively referred to as register means 641). The LFSR Tap Selection vector comprises one or a plurality of individual signals or wire 661, labelled as 661A through 661N in figure 12 (individually and collectively referred to as register means 661). The output from an individual programmable 1-bit component 500, are labelled as 51 OA through 51 ON in figure 12 (individually and collectively referred to as register means 510). The output 510 from each individual 1-bit component 500 is connected to an input of the N to I multiplexer 524. The input to an individual programmable i-bit component 500, are labelled as 51 lÀ through 51 iN in figure 12 (individually and collectively referred to as register means 511). The input 511 of a 1-bit component 500 are connected directly from the output 510 from the previous stage. A special case is the least significant stage 500A, which will have its input 511 A connected to logic zero. As the size of a programmable LFSR configuration can be less than the maximum number of 1-bit components 500 used to implement a programmable LFSR 650, then the feedback signal from the relevant most significant 1-bit component 500 needs to be selected and feedback.

The output from the multiplexer 524 forms the feedback signal 503. This is routed to each 1-bit component 500. The output of the multiplexer 524 is determined by the bit pattern on the multiplexer select lines 615. The multiplexer select lines 615 are output from the LFSR Size Register (not shown). The feedback signal 503 is also the decompressed data stream and forms output signal 618.

Each 1-bit component 500 contains a register or flip-flop 520. The flip-flop means 520 can be any type of flip-flop, such as a J-K flip-flop or D type flip-flop. The flip-flop 520 is clocked by clock 620 and can be reset using the reset signal 621. In this example the reset signal is active low. The reset can be synchronous or asynchronous. The flip-flop 520 can be loaded with the value output from the multiplexer means 522, which is controlled by the IV_SELECT signal 617. When an initial value needs to be loaded the IV SELECT signal 617 is used to route the initial value bit 641 to the input of the flip-flop 520. On the next clock cycle the input data is registered and appears at the flip-flop output 510. The other input to the multiplexer means 522 is taken from the output of a 2 input exclusive or gate 521. One input 511 to the exclusive or gate 521 is taken from the output 510 of the previous 1-bit component 500. The other input to exclusive or gate 521 is taken from the output of multiplexer means 523. The select line of multiplexer means 523 is controlled by a bit 66lfrom the LFSR Tap Selection Register 660. One input to the multiplexer means 523 is the feedback signal 503. The other input to the multiplexer means 523 is tied to logic zero.

Consequently, the setting of the multiplexer select line 661 determines if the feedback signal 503 is routed to the exclusive or gate 521 or a logic zero value.

When the programmable LFSR 650 is operational and outputting the decompressed data stream, the TV_SELECT signal 617 is disabled. In this state, the input to the flip-flop 520 is the signal that appears at the output of the exclusive or gate 521, which is routed through multiplexer 522. Consequently, by setting the state of select signals for each of the multiplexers used in each of the 1-bit components 500, a programmable LFSR 650 can be implemented. This programmable LFSR can then implement any N-bit LFSR.

The logic circuitry described so far that is used to implement the Recursive Data Folding Decoder 600 and the Recursive Data Folding Encoder 800 uses synchronous logic. In -22 -another embodiment of the invention, asynchronous logic circuitry is used to implement the Recursive Data Folding Decoder 600 and or the Recursive Data Folding Encoder 800.

The logic circuitry described so far that is used to implement the Recursive Data Folding Decoder 600 outputs a single data bit per clock cycle. In another embodiment, the programmable LFSR 650 can employ logic circuitry (not shown) that outputs a plurality of data bits per clock cycle. Though a multi-output programmable LFSR 650 is more complex in terms of logic circuitry, it would enable the clock rate to be reduced.

The logic circuitry described so far that is used to implement the Recursive Data Folding Decoder 600 and the Recursive Data Folding Encoder 800 is based on digital logic. In another embodiment of the invention, multi-level logic circuitry is used to implement the Recursive Data Folding Decoder 600 and or the Recursive Data Folding Encoder 800. In this case, each output symbol would form part or all of the output value of a data stream.

The logic circuitry described so far that is used to implement the Recursive Data Folding Decoder 600 and the Recursive Data Folding Encoder 800 is based on a linear feedback shift register. In yet another embodiment, Non linear Feedback Shift Registers (NLFSR) and Feedback with Carry Shift Registers (FCSR) can be used by the Recursive Data Folding Decoder (RDFD) 600 to generate the decompressed output data stream and any intermediate signatures. A Fibonacci configured feedback-with-cany shift register (FCSR) architecture is one in which a small amount of memory which is used in the feedback algorithm. The Feedback with Carry Shift Registers (FCSR) can also be configured as a Galois architecture.

This is more efficient than the Fibonacci architecture because the feedback computations are performed in parallel. Another form of the (Fibonacci) FCSR architecture can be implemented in which the feedback bit is delayed for N clock cycles before being returned to the first cell of the shift register.

The non linear feedback shift register can be used to generate a de Bruijn sequence.

Though the Recursive Data Folding Encoder 800 and the Recursive Data Folding Decoder 600 can be used as an independent compression decompression system, there is no reason why the apparatus cannot be used in conjunction with legacy compression and decompression means. The Motion Picture Expert Group (MPEG) (Registered Trade Mark) has developed many compression and decompression standards for both audio and video data. Two advantages of this approach are that the legacy-compressed data is already available and it would take less time for the Recursive Data Folding Encoder 800 to compress the data. This is especially so for very large data files, such as those produced from a real time video sequence.

Figure 15 shows how the Recursive Data Folding Encoder 800 can be used to compress the data stream produced by a legacy audio compression means 905. The legacy audio compression means 905 includes, MP3 (Registered Trade Mark), AAC (Registered Trade Mark), WMA (Registered Trade Mark) and AC3 (Registered Trade Mark). Analogue audio signals 911 are input to corresponding analogue to digital converter means 902. The analogue to digital converter means 902 operate at such a frequency as to minimize aliasing and distortion affects. The resolution of the analogue to digital converters 902 is dependent on the audio application and can range from 4-bits to at least 32-bits. The outputs from the analogue to digital converters 902 are input to the data interface means 903. The digital data can be stored in the memory means 904 for future use or be transferred directly to the lossy -23 -audio compression block 905 via the communication means 914. The control and data bus 913 is used to interface the Recursive Data Folding Encoder 800 to the memory means 904.

It is also used to connect the memory means 904 to the data interface 903. The memory means 904 can be semiconductor memory means, magnetic memory means or optical memory means. Overall control of the system is provided by the control means 901. Control means 901 communicates with the analogue to digital converters 902, the lossy audio compression block 905, the Recursive Data Folding Encoder 800 and the Final Signature output logic 906 via a control and data bus 910. Once the audio data has been processed and compressed using the legacy audio compression means 905, the resulting data file is stored in the memory means 904. The Recursive Data Folding Encoder 800 then reads the data file from the memory means 904, compresses the data file and generates the final signature 700.

This is output to the final signature interface 906 via interface means 916.

The final signature 700 produced by compressing a legacy compressed audio file can then be used in an audio player 950. Final signatures 700 that represent compressed audio files are stored in the final signature memory 957. The final signatures 700 are transferred into the audio player via the data interface means 952. Data is transferred to the data interface means 952 from peripheral equipment means (not shown) on bus 966. From the data interface 952, data is then transferred to the final signature memory means 957 under the control of the control logic means 951. Overall control is provided by control logic means 951. Final signature data 700 can be loaded into the final signature memory 951 via the local bus 960.

When instructed to do so, the control logic 951 transfers the selected final signature 700 from the final signature memory 957 to the Recursive Data Folding Decoder 600. The Recursive Data Folding Decoder 600 then starts to decompress the final signature 700 and outputs a data stream. This is input to the lossy audio decompression block 956 via interface means 962. The data streams output from the lossy audio decompression block 956 are then input to the digital to analogue converters 955 using interface means 963. The analogue outputs 964A, 964B are then amplified by power amplifier means953A, 953B before being output to corresponding loudspeakers 954A, 954B.

Data streams 725 are generated in a wide range of applications. These applications include audio recording and playback, video recording and playback, telecommunications, generating text documents and generating software programs. If a data stream can be recorded and stored in memory means, then it can be converted to form a final signature 700. Consequently, the Recursive Data Folding Encoder 800 can be used to form final signatures for audio data, video data, graphical data, text data and software programs. As a result, the Recursive Data Folding Decoder 600 can be used in all these application to decompress the previously compressed data streams. For example, in a microprocessor or digital signal processor, the software programs or sub-programs could be compressed as final signatures. These could be read by a Recursive Data Folding Decoder 600 in the processor to generate the next software code to be processed. This technique would reduce the size of the overall program memory, the internal caches and the time to access software if it were stored in virtual memory. In a video player back apparatus, no mechanical discs,such as DVDs or CDs would be required. All video or movie data would be coded as final signatures and stored in non-volatile semiconductor memory. This would also allow whole movies to be transmitted in a fraction of a second, as a final signature is only bytes long rather than megabytes or gigabytes long. In fact, there would only be a need for real time broadcasts. -24 -

The programmable LFSR 650 described so far is based on a single linear feedback shift register. In yet another embodiment of the invention, the decompressed output data stream 618 can be generated by combining two or more separate programmable linear feedback shift registers 650. In the configuration shown in figure 6A, the output from the upper programmable LFSR 650A is used to control the output of the other programmable LFSRs 650B. When the output of the upper programmable LFSR 51 ON is logic one, then the output from the lower programmable LFSR 650B is output. If the output of the upper programmable LFSR 650A is logic zero, then the output from the lower programmable LFSR 650B is discarded. Figure 6B shows how one programmable LFSR 650A controls the clock 620 of two other programmable LFSRs 650. Programmable LFSR 650B is clocked if the output from programmable LFSR 650A is logic one. Programmable LFSR 650C is clocked if the output from the programmable LFSR 650A is a logic zero. The output 618 is the exclusive or 650 of both the outputs from programmable LFSR 650B and 65OC.

Programmable LFSR 650B is stop / go clocked, whereas programmable LFSR 650C is go / stop clocked.

One of the reasons for combining a plurality of programmable LFSRs 650 to generate the decompressed output data stream is that these configurations have better cryptographic qualities than a single programmable LFSR 650. This will be important in applications where copyrighted data needs to be protected. These applications include compressed music files, compressed video or film files and compressed text file, such as books.

The original input data stream can be encrypted to form a new input data stream 725. The type of Digital Rights Management (DRM), watermarking, authentication or encryption method used to represent on input data stream 725 during the compression process with the Recursive Data Folding Encoder 800 is indicated by a code in the DRM Control field 703.

In yet another embodiment, the Recursive Data Folding Decoder 600 will employ the appropriate decryption and authentication circuitry means (not shown) enabling the original data stream to be recovered and output.

Although the invention has been described herein with reference to particular preferred embodiments, it is to be understood that these embodiments are illustrative of the aspects of the invention. As such, a person skilled in the art may make numerous modifications to the illustrative embodiments described herein. Such modifications and other arrangements which may be devised to implement the invention should not be deemed as departing from the spirit and scope of the invention as described and claimed herein.

Claims

-25 -

CLAIMS

1. Method and apparatus for compressing a data stream, comprising the steps of: a) selecting an optimum number of consecutive data samples from an input stream of data samples; b) use a linear feedback shift register synthesis analytical method to calculate at least the feedback polynomial and initial value for an linear feedback shift register that will generate the data stream that represents the concatenated group of consecutive data samples; c) generate a signature, the signature format comprising a plurality of data fields, the plurality of data fields including at least the feedback polynomial data, initial value data, polynomial size, cycle count, signature type, digital rights management type, sample coding type, total signature bit length; d) selecting the next consecutive group of data samples, appending these data samples to the previous signature from step (c) to form a next data stream; e) performing the steps (a), (b), (c), and (d) until all the data samples from an input stream have been read, compressed and formatted into a final signature.

2. The apparatus as claimed in Claim 1, wherein the width of a linear feedback shift register in terms of the number of single bit registers K is chosen to enable the generation of at least 2' binary information bits.

3. The apparatus as claimed in Claim 2, wherein the linear feedback shift register synthesis analytical method used to determine the linear complexity, initial value and feedback polynomial function for a binary input data stream include at least one of the Berlekamp-Massey Linear Feedback Shift Register (LFSR) shift register synthesis Algorithm, convolution attack methods, cross convolution methods, cross correlation methods combined with the Walsh-Hadamard Transform, the Chinese Remainder Theorem, Maximum Likelihood (ML) Decoding, Edit Distance on the Alternating Step Generator, Euclid's algorithm and the LFSR algorithm.

4. The apparatus as claimed in Claim 2, wherein the algorithm for compressing the binary input data samples is performed on groups of consecutive data samples in time reverse order, the order of selecting the group of consecutive data samples comprising the steps of: (a) store all the input data samples to be compressed in memory means, (b) set the NSP0 (X -N), the NEP0 = (X-1), (c) then set the NSP(1) = (NSP(1. -N), the NEP(1) = (NSP(. -1), (d) repeat step (c) until the NSP(1) is less than zero, then set NSP() = 0, where N is an integer variable, X is the total number of data samples, NSP(1) is the Next Start Pointer, NEP(1) is the Next End Pointer and i is the ith group of consecutive data samples.

5. The apparatus as claimed in Claim 2, wherein the algorithm for compressing the binary input data samples is performed on groups of consecutive data samples in time order in a two stage process, the order of selecting the group of consecutive data samples and compressing then comprising the steps of: (a) store a group of N consecutive input data samples to be compressed in memory means, (b) set the NSP0 = 0, the NEP0 = (N-I), (c) calculate the signature and store in memory means at location h, (d) then set the NSP(I) (NEP(l - + 1), the NEP(1) (NEP(1 -1) + N), (e) calculate the signature for the ith group and store at location ((h + i) -1), (f) repeat steps (d and e) until the NEP(1) is greater than X, then set NEP(1) (X -1) (g) concatenate the signatures stored at locations h to (h + i) in processed order, treat this data stream as an input data stream and calculate the final signature, where N is an integer variable, X is the total number of data samples, NSP(1) is the Next Start Pointer, NEP(1) is the Next End Pointer and i is the ith group of consecutive data samples.

6. The apparatus as claimed in Claim 4 or Claim 5 wherein, the formatted signatures calculated for each group of consecutive data samples is stored separately in memory means, the group of formatted signatures being formatted to form an index to specific locations in the input data stream.

7. The apparatus as claimed in Claim 6, wherein the group of formatted signatures are concatenated in time order to form a data stream, this said data stream then being compressed to form a final signature of index signatures.

8. The apparatus as claimed in Claim 5, wherein the concatenated signatures of stage (g) are considered as an input data stream that is subsequently divided into i groups of consecutive data samples for compression, the number of recursive passes being indicated in the final signature.

9. The apparatus as claimed in any preceding claim, wherein the clock frequency and data sampling frequency are performed at a rate that ensures there are no aliasing artefacts and distortion is minimized.

10. The apparatus as claimed in Claim 9, wherein all the input data samples required for compression are pulse code modulated and zero extended where necessary so each data sample contains the same number of bits.

11. The apparatus as claimed in Claim 9, wherein the input data samples required for compression can be of a variable length, the bit length of each input data sample being indicated by a fixed length code field appended to each data sample.

12. The apparatus as claimed in Claim 10 or Claim 11, wherein the concatenated data samples are formatted in at least of big endian and little endian formats.

-27 - 13. The apparatus as claimed in Claim 9, wherein the input data samples required for compression are represented by a one-bit data symbol code that is generated as a result of the input data samples being delta modulated.

14. The apparatus as claimed in Claim 9, wherein the input data samples required for compression are represented by a one-bit data symbol code that is generated as a result of the input data samples being delta-sigma modulated.

15. The apparatus as claimed in claim 9, wherein the control means includes user interface means to enable the selection of a final signature.

16. The apparatus as claimed in Claim 15, which further comprises interface means to allow final signature data to be transferred to and from peripheral apparatus means.

17. The apparatus as claimed in Claiml6, wherein the input data stream is taken from the output of a iossy compression apparatus means.

18. The apparatus as claimed in Claim 17, further comprising decompression means that can decompress one or a plurality of compressed final signatures enabling the original input data stream to be generated and output from the apparatus.

19. The decompression apparatus as claimed in Claim 18, which comprises at least a programmable linear feedback shift register means, control circuitry means, the control circuitry means being used to configure the programmable Linear Feedback Shift Register means under user control with data contained in a selectable final signature, the programmable linear feedback shift register means then being operable via the control means to generate an output data sequence, the output sequence containing the next signature, which is stored in memory means in the control circuitry means and output data that is output to peripheral apparatus means, the control circuitry means clocks the linear feedback shift register means a defined number of time that is determined by a control field in the current signature, on completing the output data sequence for a particular signature the programmable linear feedback shift register means is reconfigured based on data contained in the next signature, the process of configuring the programmable linear feedback shift register means, outputting a data sequence for a predetermined number of cycle being performed recursively until all output data has been output.

20. The decompression apparatus as claimed in 19, which further comprises a polynomial initial value shadow register and a programmable linear feedback shift register tap selection shadow register, these registers being loaded with their respective values from the next signature either at initialisation or when the next signature is calculated during parallel operation to the programmable linear feedback shift register continuing to generate the output data stream for the current signature.

21. The apparatus as claimed in Claim 19, wherein the decompression means comprising the steps of: (a) loading the initial value register with the initial value stored in the polynomial initial value field of the final signature, loading the programmable LFSR tap selection register with the value stored in the LFSR Tap Vector field of the final signature, loading the LFSR size register with the value in the Polynomial Size field of the final -28 -signature, loading the cycle count with the value in the Cycle Count field of the final signature, loading the control logic means registers with their respective values from the Sample Size field, the Encoding Type field, the Digital Rights Management Type field, the Signature Type field and the Length field; (b) clock the LFSR the number of times indicated in the Cycle Count field; (c) store the first J decompressed bits in memory means as these represent the next signature, where J is the value stored in the current Length field of the signature; (d) repeat steps (a), (b) and (c) until the signature type field decoded by the control logic means of the stored next signature indicates that the current signature is an initial signature; (e) decompress the initial signature, as this is the last signature.

22. The apparatus as claimed in Claim 21, wherein the linear feedback shift register means is implemented in circuitry means, the circuitry means including at least one of a Fibonacci configured linear feedback shift register means, a Galois linear feedback shift register means, a feedback with carry shift register and non-linear feedback shift register means.

23. The apparatus as claimed in Claim 21, wherein the decompressed output data stream is generated from a plurality of linear feedback shift registers.

24. The apparatus as claimed in Claim 23, wherein the output from one of the programmable linear feedback shift registers is used to control the output of the other programmable linear feedback shift registers.

25. The apparatus as claimed in Claim 23, wherein output from one of the programmable linear feedback shift registers is used to control the clock of the remaining programmable linear feedback shift registers.

26. The apparatus as claimed in Claim 21, wherein the input data stream is compressed by the compression means in order to target a specific programmable linear feedback shift register type employed in the decompression means.

27. The apparatus as claimed in Claim 21, wherein clock frequency and data sampling frequency are performed at a rate that ensures there are no aliasing artefacts and distortion is minimized in the output data stream.

28. The apparatus as claimed in Claim 21, wherein the circuit means employs asynchronous logic means.

29. The apparatus as claimed in Claim 21, wherein the circuit means further comprises multi level logic means.

30. The apparatus as claimed in Claim 29, wherein each symbol of the output data stream is a multi-level signal.

-29 - 31. The apparatus as claimed in Claim 21, wherein one or a plurality of apparatus functions are implemented using software means.

32. The apparatus as claimed in Claim 21, wherein decompressed output data stream is input to a lossy decompression means.

33. The apparatus as claimed in Claim 21, wherein the apparatus is employed in data compression applications and data decompression applications.

34. The apparatus as claimed in Claim 33, wherein the application is selected from a plurality of applications, the plurality of applications including audio applications, video applications, document data applications, data broadcast applications, data storage applications and processor cache applications.

35. The apparatus as claimed in Claim 2, wherein the said input data stream has been converted to a new input data stream using encoding encryption means, the encoding means being selected from a plurality of encoding means, the plurality of encoding means including, encryption means, watermarking means, Digital Rights Management means.

36. The apparatus as claimed in Claim 19, wherein decoding means are used to extract the original data from the output data stream, the decoding means is selected from a plurality of decoding means indicated by the value in the Digital Rights Management field, the plurality of decoding means including, decryption means, authentications means, watermarking means and Digital Rights Management means.

37. The apparatus as claimed in Claim 2, wherein one or a plurality of input data streams are combined into a single data stream for compression.

38. The apparatus as claimed in Claim 2, wherein individual data channels from a multi-channel system are compressed as individual final signatures.

39. The apparatus as claimed in Claim 19, wherein data output from a single final signature is separated and output to a plurality of separate output data streams, the output data streams being synchronised in time.

40. The apparatus as claimed in Claim 19, wherein a plurality of final signatures are decompressed by a plurality of decompression means, allowing separate data channels to be decompressed individually, the plurality of decompression means being time synchronised.

41. The apparatus as claimed in Claim 19, wherein the compression and decompression apparatus are separate and independently operable units.

42. The apparatus substantially as described herein with reference to Figures 1 -16 of the accompanying drawings.