GB2432468A

GB2432468A - An integrated optical SERDES transceiver circuit using LVDS amplifiers

Info

Publication number: GB2432468A
Application number: GB0523724A
Authority: GB
Inventors: Nishanth Kulasekeram
Original assignee: Seiko Epson Corp
Current assignee: Seiko Epson Corp
Priority date: 2005-11-22
Filing date: 2005-11-22
Publication date: 2007-05-23
Also published as: GB0523724D0

Abstract

An integrated SERDES receiver/transmitter comprises an on-chip PIN diode 100 and an on-chip laser diode 112 coupled to respective optical fibres 102,108 to provide a high data rate backplane interface. The PIN diode 100 is coupled to a transimpedance amplifier 102 which feeds an LVDS receiver amplifier (64,74,86 in figures 5,6 and 7). The laser diode 112 is driven by an LVDS circuit 106. A conventional electrical LVDS receiver amplifier 96 is coupled to an electrical input 90. The amplifier 96 may be used as the LVDS amplifier of the optical receiver. The received signals, and the signals for transmission, are coupled to a serializer/deserializer 98. The received signals may be looped back to the transmitter. Using an optical link provides low jitter and thus a higher data rate or a longer link length than an electrical LVDS SERDES arrangement (figure 4). The LVDS receiver amplifier may comprise both PMOS and NMOS input differential pairs (figure 9). The LVDS receiver amplifiers have high output impedance, so the electrical and optical input signals may be provided simultaneously.

Description

LVDS ARRANGEMENT & LVDS CIRCUIT The invention relates to an LVDS

arrangement for data transmission and reception and an LVDS amplifier circuit for use in such an LVDS arrangement.

In recent years there has been an increase in demand for high data throughputs in various environments, which conventional technologies have been unable to satisfy. Thus data transmission devices like RS-422, RS-486, SCSI and others, which are limited in data rate and power dissipation capability, cannot meet these demands. However, Low-Voltage Differential Signalling (LVDS) is a new technology which is able to meet such demands and is therefore becoming the most popular differential data-transmission standard.

LVDS technology allows products to address high data rates ranging from 100's of Mbps to the Gbps region and has therefore been deployed across market segments where the need for speed and low power exists.

Although LVDS is capable of a very high data rate, it nevertheless consumes less power than many current devices. It also offers low-noise coupling, low EM! emissions, and a switching capability beyond many current standards. LVDS applications can be used anywhere where a high data rate is required and where data have to be transferred over relatively long distances. This technology also has the ability to be integrated into system-level integrated circuits. Hence LVDS technology can be found in printers, flat panels, switches, routers, audio/video digital signal processing and many other applications.

A typical LVDS architecture is shown in Fig. 1. In Fig. 1 a transmission-side LVDS amplifier circuit 10, having a single-ended input and differential (double-ended) output, is connected to a receive-side LVDS amplifier circuit 12, having differential (double-ended) inputs and a single-ended output, by way of a transmission line 14. The data to be transmitted pass through a data transmission interface 16, a data register 18, a first-in/first-out (FIFO) shift register 20 and an 8-bit/lO-bit encoding stage 22 before being converted from parallel form to serial form in a so-called SERDES stage 24, which will be described later. The output of the SERDES stage 24 feeds the input of the transmission-side LVDS 10. Similarly, at the receive-end, the serial-format data stream output by the receive-side LVDS 12 is converted back into parallel form by a SERDES 26 and the data and clock, which may be embedded in the data, are recovered in a data/clock recovery stage 28. The recovered data are decoded in 8-bit/lO-bit decoder 30 and the recovered data words are aligned in a word alignment FIFO 32 before being taken to a data-receive interface 34, from which they are taken to further circuitry for processing.

The LVDS circuits 10 and 12 and the transmission line 14 are shown in slightly greater detail in Fig. 2. In Fig. 2 the transmission line 14, which is conventionally of copper and has a characteristic impedance Z0, is terminated by a low-value resistor RT, which may have a value of around 100 ohm, for example, at the input of the receive-side LVDS circuit 12. The use of a differential transmitter output and receiver input allows two balanced signals to be transmitted through the transmission line, but in opposite directions. Consequently the electromagnetic field from the two signals are radiated in opposite directions and, as a result, cancel out most of each other's electromagnetic interference.

A typical receive-side SERDES design is shown in Fig. 3. The SERDES is basically a stack of high-speed D-type registers and includes a phase-locked loop (PLL) 40, which serves to provide a clock signal for controlling the timing of the data passing through the SERDES. There are two ways of providing the clock. Either the clock may be derived from the PLL itself on the basis of the frequency of the basic PLL input frequency generator, or the PLL may be used to recover a clock signal, which is already embedded in the incoming data. The two clock signals so derived are provided by blocks "Timing and Control" 42 and "Clock Recovery" 44, respectively, and a choice will normally be made as to which of these two clock signals to employ. As regards control of the incoming data, the PLL 40 clocks these data at every positive edge of the PLL into the two latches shown, thereby suitably retiming the data and establishing parallel outputs as shown on the 10-bit "Dataout" line.

An example of a conventional integrated LVDS on-chip transceiver system is illustrated in Fig. 4. The chip comprises, integrated on a common substrate, an LVDS receiver 50, an LVDS transmitter 52 and a common SERDES circuit 54. The chip has, among others, a differential input 56 and a differential output 58 connected respectively to the differential input of the LVDS receiver 50 and to the differential output of the LVDS transmitter 52. The SERDES 54, the basic operation of which has already been described, is a bi-directional device and serves to either convert a serial stream of received data from the LVDS receiver 50 to parallel form or convert a parallel stream of data to be transmitted to serial form for application to the LVDS transmitter 52. The LVDS transmitter 52 converts the serial data it receives into a differential output.

It is known that a limit to the upper speed of the transmission protocol is the bit-error rate of the date being transmitted. This error rate in turn depends on the jitter present on the data edges. The present invention recognises that, in contrast to an electrical signal, an optical signal suffers less from jitter and can therefore facilitate a higher throughput of data. Alternatively, or additionally, it enables more reliable transmission at a more conventional throughput rate over longer distances either between chips on the same backplane, or even between backplanes.

In accordance with a first aspect of the invention there is provided an LVDS arrangement comprising: an optical transducer element; an LVDS amplifier circuit, and a signal-transforming stage connected between the optical transducer element and the LVDS amplifier circuit and arranged to interface a current signal associated with the optical transducer element with a voltage signal associated with the LVDS amplifier circuit.

The LVDS arrangement may be an LVDS receiver arrangement, in which case the optical transducer element is an optical receiving element for receiving an optical input signal and delivering a current output signal in dependence on said optical input signal, and the signal-transforming amplifier is a transimpedance amplifier.

The transimpedance amplifier may have a single-ended output and the LVDS amplifier circuit a differential input, and the LVDS arrangement may further comprise a matching circuit for matching the single-ended output of the amplifier to the differential input of the LVDS amplifier circuit.

The LVDS receiver arrangement preferably further comprises a serial-to-parallel SERDES circuit connected to an output of the LVDS amplifier circuit.

The LVDS arrangement may be an LVDS transmitter arrangement, in which case the optical transducer element is an optical transmitting element for receiving a current input signal and delivering an optical output signal in dependence on said current input signal, and the signal-transforming amplifier is a transconductance amplifier.

The transconductance amplifier may have a single-ended input and the LVDS circuit a differential output, and the LVDS arrangement may further comprise a matching circuit for matching the differential output of the LVDS amplifier circuit to the single-ended input of the transconductance amplifier.

The LVDS transmitter arrangement preferably further comprises a parallel-to-serial SERDES circuit connected to an input of the LVDS amplifier circuit.

The transimpedance amplifier may comprise a MOS configured in common-gate mode, the optical receiving element being connected to a source terminal of the MOS and an output of the transimpedance amplifier being taken from a drain terminal of the MOS.

In a second aspect of the invention, there is provided an LVDS amplifier circuit for use as the LVDS amplifier circuit forming part of the LVDS arrangement as described above, wherein the LVDS amplifier circuit comprises: a first differential amplifier arrangement of a first transistor polarity; a first current-mirror arrangement connected to first output terminals of said first differential amplifier arrangement; a second differential amplifier arrangement of a second, and opposite, transistor polarity; a second current-mirror arrangement connected to second output terminals of said second differential amplifier arrangement; wherein the first output terminals are cross-coupled to respective halves of the first current-mirror arrangement and the second output terminals are cross-coupled to respective halves of the second current-mirror arrangement; and a mirror output of the first current-mirror arrangement and a mirror output of the second current-mirror arrangement together form a common output of the LVDS arrangement.

The first and second current-mirror arrangements may each comprise a first current mirror, a second current mirror and a third current-mirror, wherein the first and second current-mirrors of the first current-mirror arrangement and the third current-mirror of the second current-mirror arrangement comprise transistors of the second transistor polarity, while the third current-mirror of the first current-mirror arrangement and the first and second current-mirrors of the second current-mirror arrangement comprise transistors of the first transistor polarity.

The LVDS amplifier circuit may further comprise a current-mirror current source feeding the first differential amplifier arrangement.

The LVDS amplifier circuit may also comprise a switching arrangement connected to the first and second differential amplifier arrangements for selectively enabling and disabling the first and second differential amplifier arrangements.

The transistors of the LVDS circuit may be either MOS or bipolar transistors, or a mixture of the two.

The invention further provides, as a third aspect, an LVDS amplifier circuit configured as LVDS circuit 120 shown in Fig. 9 of the drawings, wherein VDD represents a positive voltage rail relative to a ground voltage rail (GND), VDD' represents a positive voltage rail which may be equal to, or different from, VDD, En represents an enabling input voltage, IN and INA represent differential inputs and line 130 represents a single-ended output of the LVDS circuit.

The LVDS amplifier circuit just set forth may employ transistor polarities and voltage-supply rails as shown, or these may be reversed.

As a fourth aspect, the present invention provides an integrated LVDS arrangement comprising: an LVDS receiver arrangement including an optical receiving element for receiving an optical input signal; an LVDS amplifier circuit, and a transimpedance amplifier connected between the optical receiving element and the LVDS amplifier circuit; an LVDS transmitter arrangement including an LVDS modulator circuit; an optical transmitting element, and a transconductance amplifier connected between the LVDS modulator circuit and the optical transmitting element; a SERDES circuit connected to an output of the LVDS amplifier circuit and to an input of the LVDS modulator circuit, and an input-voltage terminal arrangement connected to the SERDES circuit by way of an LVDS amplifier circuit, whereby data can be fed to the integrated LVDS arrangement by way of the input-voltage terminal arrangement and/or the optical receiving element and data can be taken out of the integrated LVDS arrangement by way of the optical transmitting element.

The LVDS amplifier circuit, which is connected to the input-voltage terminal arrangement, may be the same as the LVDS amplifier circuit, which is connected to the optical receiving element.

Embodiments of the invention will now be described, by way of example only, with the aid of the attached drawings, of which: Fig. 1 is a block diagram of a known LVDS system architecture; Fig. 2 is a block schematic arrangement of a known LVDS transceiver arrangement; Fig. 3 is a circuit diagram illustrating the principle features of a known SERDES circuit; Fig. 4 is a block schematic diagram of a known integrated LVDS on-chip transceiver system; Fig. 5 is a block schematic diagram of an LVDS receiver architecture in accordance with the present invention; Fig. 6 is a block schematic diagram of an LVDS on-chip receiver arrangement in accordance with the present invention; Fig. 7 is a block schematic diagram of an LVDS on-chip transceiver arrangement in accordance with the present invention; Fig. 8 is a block schematic diagram of an integrated LVDS on-chip transceiver arrangement in accordance with the present invention; Fig. 9 is a circuit diagram of an embodiment of an LVDS amplifier circuit in accordance with the present invention; Fig. 10 is a circuit diagram of a typical single-ended to differential converter, which may be employed in connection with the present invention, and Fig. 11 is a perspective representation of an integrated electro-optical system employing an LVDS arrangement in accordance with the present invention.

A schematic representation of an embodiment of an LVDS arrangement according to the invention is shown in Fig. 5. In Fig. 5 an optical diode (which is preferably a "PIN" diode) 60 is provided, which picks up optical radiation from the end of an optical fibre taking the place of the copper transmission line 14 in Fig. 2. The diode is connected to an input of a transimpedance amplifier 62, which accepts an input current from the diode 60, which is proportional to the optical radiation incident on the diode, and outputs in dependence on that current a differential voltage. This differential voltage then feeds the differential input of an LVDS circuit 64. Suitable biasing arrangements are included for the diode 60 and gain-determining feedback is provided by feedback resistance Rf.

A slightly modified form of this arrangement, which can be applied to a chip, is shown in Fig. 6. Here -as in Fig. 5 -a PIN diode 70 (which is biased by the application of two supply voltages, Supply 1 and Supply 2) feeds a transimpedance amplifier 72, which feeds an LVDS circuit 74, which in turn feeds a SERDES with a serial data stream.

The SERDES outputs this data stream in parallel form. However, in this case a post-amplifier 78 is also provided, which matches the single-ended output of the transimpedance amplifier 72 to the double- ended (differential) input of the LVDS circuit 74.

Fig. 7 shows a schematic block diagram of a possible on-chip transmitter arrangement, which could be employed on the same chip as the Fig. 6 arrangement. In Fig. 7 a diode 80 (e.g. a PIN diode) feeds a transimpedance amplifier 82, which again feeds a post amplifier 84. This time, however, the post amplifier 84 outputs a signal in single-ended form only instead of double-ended, and this single-ended output feeds the input of an LVDS transmitter 86. A differential output of the LVDS transmitter 86 drives differential output terminals Q, Qn. Terminals Q, Qn can be used to drive a copper transmission line linking either with another chip on the same board or backplane or another chip on a different board or backplane. In this arrangement the diode 70 receives data from an optical-fibre link and output it again in electrical form on terminals Q, Qn for use on a different chip or possibly on a different board, etc. In a practical chip employing both the Fig. 6 and Fig. 7 arrangements the diodes 70 and 80 may be the same component and the transimpedance amplifiers 72, 82 niay be the same component, thereby saving on hardware and space.

It is also possible to employ the Fig. 7 arrangement as a transceiver arrangement instead of just a transmitter arrangement. This is achieved by reversing the signal direction, so that the terminals Q, Qn constitute voltage inputs, which feed the differential inputs of the LVDS circuit 86, which is now configured as a receiver circuit. The LVDS receiver circuit 86 outputs a single-ended signal to drive the post-amplifier 84, which in turn drives the amplifier 82. In this case, however, amplifier 82 is a transconductance amplifier, since it is voltage-driven from the post-amplifier and current-drives the diode 80. Furthermore, diode 80 will be a laser transmitting diode, as opposed to a PIN receiving diode. In practice, both a PIN diode and a laser diode could be mounted side-by-side on the chip, thereby allowing both the receiving and transmitting functions of a transceiver to be performed.

Fig. 8 shows an integrated on-chip optical LVDS arrangement according to a further embodiment of the invention. In this arrangement, which is an inventive development of the known integrated on-chip arrangement of Fig. 4, there are three main ports on the chip. These are an electrical input port 90, an optical input port 92 and an optical output port 94. The electrical input port 90 feeds the differential input of an LVDS amplifier circuit 96, which outputs a single-ended serial voltage signal to a SERDES 98.

The SERDES 98 converts the serial data stream of this voltage signal to parallel data for use elsewhere on the chip. A PIN diode 100, which is disposed at the end of an optical fibre 102 forming the optical input port 92, converts the optical data signal emerging from the fibre to an electrical current, which is then converted from current to voltage form in a transimpedance amplifier 102, as already described in connection with Fig. 5. The transimpedance amplifier 102 then outputs a serial data stream, which is converted into parallel form in the SERDES 98 (see the upward-facing arrow on line 104 connecting the SERDES with the transimpedance amplifier). In practice the signal passing from the transimpedance amplifier 102 to the SERDES 98 may pass through an LVDS amplifier circuit, as shown in Fig. 5. This LVDS amplifier circuit may be a separate component from the LVDS amplifier circuit 96, or it may be the same component. If a separate component is used, its output may be directly connected to the output of the LVDS 96.

This is possible because an LVDS circuit normally has a high-inipedance output. Finally, an LVDS modulator circuit 106 is included, which drives a laser diode 112 for outputting a data stream into an optical fibre 108 at the output port 94.

The data driving the modulator 106 can either be data which passes through the SERDES 98 from right to left (that is, from parallel to serial form) and is taken to the modulator along line 104 (see the downward-facing arrow on line 104), or it can be the same data as that which has been received from PIN diode 100 via the transimpedance amplifier 102 (see line 110). A situation in which it may be desirable to pass the signal received from diode 100 directly back out via the laser diode 112 is where, for example, signals were being transferred over a long distance on a large backplane (for example, from one end to the other) and there was a potential problem with large bit-error changes due to jitter. In order to ensure that the signal edges were well defined, it would be possible to provide a form of regeneration on the signals being transferred by allowing a chip at an intermediate location on the backplane to receive the relevant signals from one of the chips at one end of the backplane, via the optical input port 92, and output the same signals, suitably refreshed, at the optical output port 94. These regenerated signals would then be passed on to the chip at the other end of the backplane.

A detailed circuit diagram showing an embodiment of the LVDS amplifier circuits 64 and 74 of Figs. 5 and 6, respectively, is illustrated in Fig. 9. The circuit consists of a front-end optical transimpedance receiver consisting of an optical diode 110, which may be constituted by a PIN diode or an MSM diode, feeding the source of a common-gate configured MOS 112. The source of MOS 112 is connected to ground via a resistor 114, while the drain is connected to a positive voltage rail (VDD) via a resistor 116. The gate of the MOS 112 is connected to ground. This stage thus operates on the basis of an input current from the diode 110 establishing a proportional output voltage on the MOS drain.

This voltage is then taken to the input of a single-ended to differential (double-ended) converter, i.e. matching circuit 118, which may of any conventional design. Fig. 10 shows an example of such a matching circuit consisting of a differential amplifier, one input (gate) of which is fed from the output of the transimpedance amplifier 112, while the other input (gate) is biased by a potential divider between the two rails VDD and ground.

The outputs (drains) of the differential amplifier form the differential output of the stage 118. This differential output is taken to the input of the LDVS circuit proper shown as circuit 120 in Fig. 9. Thus outputs OUT and OUTA from the converter 118 form inputs IN and INA, respectively, of the circuit 120.

The LVDS amplifier circuit comprises two differential amplifiers 122, 124, made up of respective MOS pairs MN3, MN4 and MP8, MP9. MOSs MN3 and MN4 are N-channel MOSs, while MOSs MP8 and MP9 are P-channel MOSs. The current source for differential amplifier 122 is formed by mirror-configured MOS pair MN! and MN2 and a further N-channel MOS, MNO, is provided with its drain connected to the commoned gates of MN1 and MN2 and its source connected to ground. MNO is a switching MOS, whose gate is controlled by an enabling voltage, En. Likewise the differential amplifier 124 is connected at its commoned source line to voltage rail VDD via a further switching MOS, MPIO, whose gate is similarly controlled by voltage En.

The drains of MOSs MN3 and MN4 form a pair of nodes A, B, while the drains of MOSs MP8 and MP9 form a pair of nodes C, D, as shown. Nodes A, B are "pulled up" (that is, provided with a pull-up voltage) by MOS arrangement 126, consisting of MPO- MP5 and MN5, MN6, while Nodes C, D are "pulled down" (that is, provided with a pull-downs voltage) by MOS arrangement 128, consisting of MN7-MN12 and MP6, MP7.

MOS arrangement 126 comprises a set of three current mirrors: MPO-MP2, MP3-MP5 and MN5, MN6. MOSs MP2 and MP3 are cross-connected at their drains to nodes B and A and the drains of MN5 and MN6 are connected respectively to the drains of MP4 and MP1. Moving to MOS arrangement 128, this is configured in similar maimer to MOS arrangement 126. Thus, arrangement 128 likewise comprises three mirrors: MN7-MN9, MN1O-MN12 and MP6, MP7. There is a similar cross-coupling of the drains of MN9 and MNIO with nodes D and C, respectively, while the drains of MP6 and MP7 are connected respectively to the drains of MN! 1 and MN8.

The single-ended output 130 of the LVDS circuit 120 is provided by the commoned drains of MP1/MN6 on the one hand and the commoned drains of MP6, MNI1 on the other. This output 130 is then passed through a buffer 132 to form the final output 134 of the LVDS circuit. The buffer 132, which may invert the output signal, ensures that the excursions of the output signal substantially reach the positive and ground voltage-supply rails.

The inputs of MN3, MN4 are connected in parallel with the gates of MP9 and MP8, respectively. As regards supply-voltage allocation, the mirror arrangement 126 (i.e. MPO-MP5) and the cominoned sources of the differential amplifier 124 (MP8 and MP9) are fed from the same positive voltage rail, shown as VDD, while the sources of MP6 and MP7 and the drain of MN2 may be fed from VDD or from a different positive voltage rail, shown here as VDD'.

In operation, when En is low, the circuit chain consisting of transistors MNI-MN6 and MPO-MP5 is active. When INA is HIGH and IN LOW, MN3 switches on while MN4 switches off. Node A is therefore pulled LOW, which results in MPO-MP2 switching on, thereby pulling node B HIGH. Also when En is LOW, transistor MP1O is switched on.

When INA is HIGH and IN LOW, MP9 is switched off, while MP8 is switched on. This in turn makes transistors MP8, MP9 and MN7-MN12 all active. As a result Node C is pulled HIGH, while Node D is pulled LOW by the action of mirror MN7-MN9. The output 130 is buffered by inverter 132 before being fed into a SERDES bank of high-speed D-type registers, such as the SERDES 98 shown in Fig. 8.

The converse happens when INA is LOW and IN is HIGH. Thus node B is pulled LOW by MN4 and node D is pulled HIGH by MP9, while node A is pulled HIGH by mirror MP3-MP5 and node C is pulled LOW by mirror MNIO-MNI2.

Fig. 11 shows an example of an integrated electro-optical system employing an LVDS arrangement as described above.

The integrated electro-optical system comprises a backplane 150, to which circuit boards 152, 154 and 156 are connected. Each of these boards has mounted thereon one or more chips containing the LVDS arrangement described earlier consisting of at least the receiver arrangement shown in Fig. 5 and, where appropriate, the more comprehensive on-chip arrangement shown in Fig. 8. Where the chips interconnect between boards -or even between the backplane shown and another, remote, backplane -signals will be passed between the boards/backplanes using the transceiver input/output ports 92, 94 shown in Fig. 8. Electrical inputs may also be accommodated by way of the electrical input port 90.

These electrical inputs may be in place of, or in addition to, the optical inputs.

Although the LVDS circuit of Fig. 9 has been described as consisting of MOS devices (e.g. CMOS), it may instead be based on the use of bipolar devices, or even a mixture of MOS and bipolar.

Claims

CLAIMS

1. An LVDS arrangement comprising: an optical transducer element; an LVDS amplifier circuit, and a signal-transforming stage connected between the optical transducer element and the LVDS amplifier circuit and arranged to interface a current signal associated with the optical transducer element with a voltage signal associated with the LVDS amplifier circuit.

2. An LVDS arrangement as claimed in claim 1, wherein the LDVS arrangement is an LVDS receiver arrangement, and: the optical transducer element is an optical receiving element (70; 110; 100) for receiving an optical input signal and delivering a current output signal in dependence on said optical input signal, and the signal-transforming amplifier is a transimpedance amplifier (72, 112-116, 102).

3. An LVDS arrangement as claimed in claim 2, wherein the transimpedance amplifier has a single-ended output and the LVDS amplifier circuit has a differential input, and the LVDS arrangement further comprises a matching circuit (78; 118) for matching the single-ended output of the amplifier to the differential input of the LVDS amplifier circuit.

4. An LVDS arrangement as claimed in claim 2 or claim 3, further comprising a serial-to-parallel SERDES circuit (98) connected to an output of the LVDS amplifier circuit.

5. An LVDS arrangement as claimed in claim 1, wherein the LVDS arrangement is an LVDS transmitter arrangement, and: the optical transducer element is an optical transmitting element (112) for receiving a current input signal and delivering an optical output signal in dependence on said current input signal, and the signal-transforming amplifier is a transconductance amplifier.

6. An LVDS arrangement as claimed in claim 5, wherein the transconductance amplifier has a single-ended input and the LVDS circuit has a differential output, and the LVDS arrangement further comprises a matching circuit for matching the differential output of the LVDS amplifier circuit to the single-ended input of the transconductance amplifier.

7. An LVDS arrangement as claimed in claim 5 or claim 6, further comprising a parallel-to-serial SERDES circuit connected to an input of the LVDS amplifier circuit.

8. An LVDS arrangement as claimed in any one of claims 2 to 4, wherein the transimpedance amplifier comprises a MOS configured in common-gate mode, the optical receiving element being connected to a source terminal of the MOS and an output of the transimpedance amplifier being taken from a drain terminal of the MOS.

9. An LVDS amplifier circuit for use as the LVDS amplifier circuit forming part of the LVDS arrangement as claimed in any one of the preceding claims, wherein the LVDS amplifier circuit comprises: a first differential amplifier arrangement (MN3, MN4) of a first transistor polarity; a first current-mirror arrangement (126) connected to first output terminals (A, B) of said first differential amplifier arrangement; a second differential amplifier arrangement (MP8, MP9) of a second, and opposite, transistor polarity; a second current-mirror arrangement (128) connected to second output terminals (C, D) of said second differential amplifier arrangement; wherein the first output terminals (A, B) are cross-coupled to respective halves (MP3-MP5, MN5; MPO-MP2, MN6) of the first current-mirror arrangement (126) and the second output terminals (C, D) are cross-coupled to respective halves (MN1O-MN12, MP6; MN7-MN9, MP7) of the second current-mirror arrangenient (128); and a mirror output of the first current-mirror arrangement (126) and a mirror output of the second current-mirror arrangement (128) together form a common output (130) of the LVDS arrangement.

10. An LVDS amplifier circuit as claimed in claim 9, wherein the first and second current-mirror arrangements (126; 128) each comprise a first current mirror (MPO-MP2; MN7-MN9), a second current mirror (MP3-MP5; MN1O-MN12) and a third current- mirror (MN6, MN5; MP7, MP6), wherein the first and second current-mirrors (MPO- MP2, MP3-MP5) of the first current-mirror arrangement (126) and the third current-mirror (MP7, MP6) of the second current-mirror arrangement (128) comprise transistors of the second transistor polarity, while the third current-mirror (MN5, MN6) of the first current-mirror arrangement (126) and the first and second current-mirrors (MN7-MN9; MN1O-MN12) of the second current-mirror arrangement (128) comprise transistors of the first transistor polarity.

11. An LVDS amplifier circuit as claimed in claim 10, further comprising a current-mirror current source feeding the first differential amplifier arrangement (122).

12. An LVDS amplifier circuit as claimed in claim 11, further comprising a switching arrangement connected to the first and second differential amplifier arrangements (122, 124) for selectively enabling and disabling the first and second differential amplifier arrangements.

13. An LVDS amplifier circuit as claimed in any one of claims 9 to 12, wherein the LVDS amplifier circuit is based on the use of MOS transistors and/or bipolar transistors.

14. An LVDS amplifier circuit configured as LVDS circuit 120 shown in Fig. 9 of the drawings, wherein VDD represents a positive voltage rail relative to a ground voltage rail (GND), VDD' represents a positive voltage rail which may be equal to, or different from, VDD, En represents an enabling input voltage, IN and INA represent differential inputs and line 130 represents a single-ended output of the LVDS circuit.

15. An LVDS amplifier circuit as claimed in claim 14, wherein the polarities of the transistors and the relative polarities of the power rails are reversed.

16. An integrated LVDS arrangement comprising: an LVDS receiver arrangement including: an optical receiving element (100) for receiving an optical input signal; an LVDS amplifier circuit, and a transimpedance amplifier (102) connected between the optical receiving element and the LVDS amplifier circuit; an LVDS transmitter arrangement including: an LVDS modulator circuit (106); an optical transmitting element (112), and a transconductance amplifier connected between the LVDS modulator circuit and the optical transmitting element; a SERDES circuit (98) connected to an output of the LVDS amplifier circuit and to an input of the LVDS modulator circuit, and an input-voltage terminal arrangement (90) connected to the SERDES circuit (98) by way of an LVDS amplifier circuit (96), whereby data can be fed to the integrated LVDS arrangement by way of the input-voltage terminal arrangement (90) and/or the optical receiving element (100) and data can be taken out of the integrated LVDS arrangement by way of the optical transmitting element (112).

17. An integrated LVDS arrangement as claimed in claim 16, wherein the LVDS amplifier circuit (96) which is connected to the input-voltage terminal arrangement is the same as the LVDS amplifier circuit which is connected to the optical receiving element.

18. An LVDS arrangement substantially as shown in, or as hereinbefore described with reference to, Fig. 5, or Fig. 6 and Fig. 7, or Fig. 8, or Fig. 9 of the drawings.