GB2425418A

GB2425418A - An efficient class B RF amplifier with supply voltage modulation

Info

Publication number: GB2425418A
Application number: GB0508049A
Authority: GB
Inventors: Haim Friedlander; Gadi Shirazi
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 2005-04-22
Filing date: 2005-04-22
Publication date: 2006-10-25
Anticipated expiration: 2025-04-22
Also published as: GB2425418B; WO2006115879A2; WO2006115879A3; GB0508049D0

Abstract

The dc collector or drain current of class B amplifying transistor 101 is detected by a sense resistor 108 and differential amplifier 112. The output voltage Vcc of the switching regulator 107 is controlled to be in proportion to the sensed current so that the amplifier operates slightly below saturation at all input power levels. In a class B amplifier, the DC supply current is proportional to the output RF power level. The amplifier may be used in mobile or base stations. The technique avoids the effect of transistor variations with time or variations between devices. There is no need to calculate the power envelope from in-phase and quadrature data and there is no need to compensate for inherent delays to achieve matching of the supply voltage and the RF power envelope.

Description

TITLE: AMPLIFIER CIRCUIT AND RF TRANSMITTER

INCORPORATING THE CIRCUIT

FIELD OF THE INVENTION

The present invention relates to an amplifier circuit and an RF transmitter incorporating the circuit.

In particular, the invention relates to a linear power amplifier circuit incorporating an improved envelope follower for use in RF transmission.

BACKGROUND OF THE INVENTION

Linear power amplifiers are widely used in RF iS transmitters. Such amplifiers are known to have poor efficiency. This is due to the fact that the operating point must be chosen sufficiently low so that the power envelope peaks will not be clipped. The efficiency becomes worse as the peak-to-average ratio of the amplified signal increases.

Many efficiency improvement techniques have been developed for linear power amplifiers. One of these techniques is known as supply modulation', or envelope following' (EF) . In this technique, the DC supply voltage is varied over time in accordance with the power envelope, so that the amplifier is always operating just below saturation and relatively good efficiency is thereby maintained. A switching regulator is normally used to provide the varying supply voltage.

The key to successful operation of the known envelope follower technique is to determine the optimum instantaneous supply voltage correctly. This is difficult since there are inherent delays that must be compensated for in order to match the supply voltage to the power envelope waveform. Another problem is dependence of operation on the characteristics of the amplifying device, e.g. transistor, used in the amplifier, which may change over time or vary from unit to unit.

One known method of predicting the optimum supply voltage is to calculate the power envelope from the sum of squares of the in-phase (I) and quadrature phase (Q) components of the baseband modulation signal, i.e. 12+Q2.

This method is an open loop one, i.e. it assumes fixed characteristics of the power amplifier. This is a disadvantage, since as noted earlier the characteristics can change with time. Furthermore, the baseband modulation signal is not always predictable, as in the case of an analog AN transmitter.

Another known method involves sampling a portion of the power at the input of the amplifier stage and detecting the envelope. Again, this is an open loop method that assumes fixed characteristics of the amplifier stage, and compensation must be applied for delays that may or may not be constant.

SUMMARY OF THE INVENTION

The present invention provides an improved amplifier circuit for use in a RF transmitter, wherein the circuit operates an improved envelope follower procedure.

According to the present invention in a first aspect there is provided an amplifier circuit for use in a RF transmitter, the amplifier circuit being as defined in claim 1 of the accompanying claims.

According to the present invention in a second aspect there is provided a RF transmitter as defined in claim 15 of the accompanying claims.

In contrast to the prior art amplifier circuits

described earlier, the amplifier circuit of the invention uses a closed loop to control the output voltage from a supply voltage regulator. The output voltage is controlled to have an envelope which follows a signal representing a sampled direct current flowing through the amplifying device of the amplifier circuit.

As shown later, this enables a substantially constant efficiency of operation to be maintained.

The invention may be implemented in a simple and inexpensive manner and beneficially requires no knowledge of the power envelope of the input RF signal, unlike the prior art circuit mentioned earlier. The amplifier circuit of the invention is therefore suitable for amplifying a RF signal having any type of modulation, analogue or digital.

Furthermore, variations in the operating characteristics of the amplifying device during use can be compensated for automatically.

The amplifying device employed in the amplifier circuit according to the first aspect of the invention may comprise a solid state amplifying device such as a transistor which may be in bipolar form or in insulated

gate field effect (e.g. JFET or MOSFET) form.

For example, where the transistor is in the form of a bipolar junction transistor, the input signal is applied at the base electrode of the transistor (which in this case is the first terminal as referred to in claim 1), and the output signal may be extracted from the collector electrode of the transistor (which in this case is the second terminal referred to in claim 1) . The modulated supply voltage may be applied at the collector electrode.

Alternatively, where a MOSFET (metal oxide semiconductor field effect transistor) is employed, the input signal is applied at the gate electrode of the transistor (which in this case is the first terminal as referred to in claim 1) . The modulated supply voltage may be applied to the transistor at the drain electrode (which in this case is the second terminal referred to in claim 1) . The output signal may be extracted from the drain electrode.

The amplifier circuit according to the present invention may be a linear amplifier which may find use in RF circuits for a wide number of applications, including both analogue and digital applications. Such applications include transmitters for RF communications, RF smartcards, RF near field excitation devices, radio and television broadcasting, radar and many others. In this specification, RF' is generally understood to mean frequencies of greater than 10KHz, e.g. up to 500GHz. In many cases the RF energy produced in the application will have a frequency of from 100KHz to 100GHz.

Where the invention is employed in RF communications transmitters, such transmitters may be incorporated in communications apparatus. For example, the apparatus may comprise a mobile or fixed radio transceiver. Mobile radio transceivers are also referred to herein as mobile stations (MS5) . The term mobile station (MS) is intended to include within its meaning apparatus such as mobile and portable telephones and mobile and portable radios, data communication terminals and the like which operate by radio communication.

Systems which provide communications to or from MSs by fixed or base transceivers known in the art as base transceiver stations' or BTSs' may be arranged to give communications coverage in a network of regions known as cells and are referred to herein as cellular radio communications systems. Thus, the invention may find partcular use in a MS or in a BTS of a mobile or cellular communication system. The operational power levels are much greater in a BTS than in a MS.

Embodiments of the present invention will now be described by way of example with reference to the accompanying drawings, in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic circuit diagram of an RF amplifier circuit embodying the invention.

FIG. 2 is a circuit diagram, partly in block schematic form, of a circuit which may be employed as a switching regulator in the circuit of FIG. 1.

FIG. 3 is a schematic diagram of an example of part of the circuit shown in FIG. 2.

FIG. 4 is a block schematic diagram of an RF transmitter embodying the invention.

DESCRIPTION OF EMBODIMENTS OF THE INVENTION

FIG. 1 is a schematic circuit diagram of an RF amplifier circuit 100 embodying the invention. A power transistor 101 is shown as a bipolar transistor (but could easily be replaced by another form of transistor, for example a MOSFET, as will readily be apparent to those skilled in the art) . The transistor 101 includes a base electrode 102 to which an input RF signal is applied, an emitter electrode 103 which is earthed and a collector electrode 104 from which an output amplified RF signal is extracted at an output connection 105 via a DC blocking capacitor 116. A bias circuit 114 sets the operating point of the transistor 101 such that the transistor 101 is operating as a linear power amplifier (e.g. class B) . An RF signal is applied to an input terminal 117. This signal passes through a D.C. blocking capacitor 115 and arrives at the base electrode 102 of the transistor 101.

A D.C. supply voltage is generated by a voltage source 106 and is applied through a switching or envelope follower regulator 107 which adjusts the voltage in a manner to be described later. The output voltage provided by the regulator 107 is a voltage which is applied in turn through a shunt resistor 108 and a RF choke (inductive coil) 109 to the collector electrode 104 of the transistor 101. This applied voltage V causes a current ix: to flow into the collector electrode 104 of the transistor 101 between the collector electrode 104 and the emitter electrode 103. The magnitude of this current is closely proportional to the amplitude of the RF signal applied at the base electrode 102 of the transistor 101, and also to the amplitude of the amplified RF signal at the collector electrode 104.

Connections 110 and 111 lead from the respective ends of the shunt resistor 108 to form inputs to a differential amplifier 112. The differential amplifier 112 thereby measures the potential difference between the respective ends of the shunt resistor 108 which is a measure of the current T)C flowing through the shunt resistor 108 as well as into the collector electrode 104 of the transistor 101. An output connection 113 from the differential amplifier 112 leads to the switching regulator 107 thereby forming a feedback loop. The connection 113 delivers a control signal indicating the measured value of lix' to a control input of the switching regulator 107. As described in more detail later, the switching regulator 107 adjusts the output voltage Vcc provided by the switching regulator 107 so that the output voltage V(-:c is proportional to the indicated value of the control signal which in turn is a measure of DC.

The circuit 100 shown in FIG. 1 operates as a class B linear amplifier. Operation may be further understood from the following analysis.

The collector efficiency 17 of the transistor 101 is given by: P. RI' Equation 1

I

where PRF is the output RF power, Va: is the supply voltage and Ij is the current flowing through the transistor 101. For a linear class B amplifier stage, the DC current Jx-' is proportional to the square root of the output RF power P,?F: 1ix:=ki[ Equation 2 where k1is a constant.

Substituting the expression for DC of Equation 2 into the efficiency formula of Equation 1, we obtain: 17= = Equation 3 V *k J' k1 We see that in order to maintain constant efficiency 11, V(:( needs to be made proportional to the square root of PR,-: - k2 ç 17 k2.Ji.k1 k2k1 consi. 9 --

where k2andkjare constants. Recalling from Equation 2 that: I1.-_k1.jf= Equation 4 we see that: (wherek!fL) Equation 5 We may conclude from Equation 5 that if we make Vcc linearly proportional to ljc, the efficiency 1 will remain constant. This is accomplished in the circuit 100 shown in FIG. 1 by sampling the DC current iJ)C by the connections 110 and 111 and the differential amplifier 112 and feeding back a control signal representing the measured value of lix' to the switching regulator 107 in order to control the output voltage Vcc provided by the switching regulator 107 in direct proportion to Ipx'.

The switching regulator 107 included in the circuit shown in FIG. 1 is a device which converts the varying control signal from the differential amplifier 112 in FIG. 1 into an output voltage which replicates the form of the input signal. In other words the output voltage Vcc has an envelope which follows that of the input control signal. Devices of this kind are known per se and for example are used in the prior art envelope follower circuits described earlier. Such devices are known alternatively as tracking voltage regulators, dynamic supply modulators or power controllers and are in the family of devices known as DC-DC converters. The switching regulator 107 may be any of the known devices suitably adapted. An illustrative example of such a device will now be described.

FIG. 2 is a circuit diagram, partly in block schematic form, of a circuit 150 which is an example of a circuit employed as the switching regulator 107. The circuit 150 includes an electronic switch 153 and a synchronous rectifier 159 which is a further electronic switch. The electronic switch 153 and the synchronous rectifier 159 are shown in the particular form of p-mos (positive channel metal oxide semiconductor) and n-mos (negative channel metal oxide semiconductor) transistor devices respectively with an applied positive voltage.

This is for illustration only. It will be apparent to those skilled in the art that the polarities could be reversed either with reversal of the polarity of the applied voltage or with use of a special gate system, e.g. using a capacitor. Alternatively, the electronic switch 153 and the synchronous rectifier 159 may be bipolar junction transistors.

The voltage source 106, which may for example be one or more batteries or an output from a mains supply rectifier, provides an input DC voltage V which is applied to a source electrode 156 of the electronic switch 153. The electronic switch 153 also includes a gate electrode 155 and a drain electrode 157. The electronic switch 153 is connected at its drain electrode 157 to a drain electrode 162 of the synchronous rectifier 159. The synchronous rectifier 159 also has a gate electrode 161 and a source electrode 163 which is grounded.

An inductor 165 is connected to the drain electrode 157 of the electronic switch 153 and to the drain electrode 162 of the synchronous rectifier 159 via a junction 164. The inductor 165 is connected at a junction 168 to a parallel combination of a capacitor 169 and a load resistor 167 both of which are grounded at their other ends (distant from the inductor 165) . An output voltage is developed at an output terminal 166 connected to the junction 168.

A control logic unit 179 produces an output pulsed (approximately square wave) drive waveform Wi which is applied to the gate electrode 155 of the electronic switch 153 and an output pulsed (approximately square wave) drive waveform W2 which is applied to the gate electrode 161 of the synchronous rectifier 159. The waveforms Wi and W2 are such that the waveform Wi drives the electronic switch 153 to be on, i.e. to conduct, whilst the synchronous rectifier 159 is off and the waveform W2 drives the synchronous rectifier 159 to be on, whilst the electronic switch 153 is off, although there can be delay between the synchronous rectifier 159 being turned off by the waveform W2 and the electronic switch 153 being turned on by the waveform Wi. The waveforms Wi and W2 typically have a cycle frequency in the range 10kHz to 10MHz but the frequency is not limited to this range.

The components of the circuit 150 described so far operate in the following way. Electrical energy from the voltage source 106 is transferred from the voltage source 106 to the load impedance provided by the resistor 167 by repetitive pulsing provided by the switching of the electronic switch 153 caused by application of the drive waveform Wi. Excess energy delivered from the voltage source 106 is stored and unloaded in the reactive components, namely the inductor 165 and the capacitor 169, whilst constant power is maintained in the load resistor 167, producing an output voltage at the output terminal 166. As noted earlier, the synchronous rectifier 159 is driven to conduct by the drive waveform W2 during portions of the cycle of the drive waveform Wi when the electronic switch 153 is not conducting. The synchronous rectifier 159 serves as an electrically controlled rectifying diode. Excess electrical energy stored in the inductor 165 and in the capacitor 169 in each positive part of the waveform Wi is extracted as electrical current in each positive part of the waveform W2 via conduction of the synchronous rectifier 159.

The circuit 150 includes a feedback loop 180. A connection 181 extends from the junction 168 to a resistor 183 which is connected to another resistor 185 grounded at its other end. The resistors 183 and 185 form a voltage divider. A connection 187 from the junction between the resistors 183 and 185 is applied as one input to a comparator 189. The comparator 189 receives as another input an input voltage VIN which is the control signal provided as an output from the differential amplifier 112 via the connection 113 shown in FIG. 1. The comparator 189 is connected to the control logic unit 179. An output signal from the comparator 189 is thereby applied to the control logic unit 179.

In operation of the feedback loop 180, a sample of the output voltage Vcc suitably divided down by the voltage divider comprising the resistors 183 and 185 is applied via the feedback loop 180 to the comparator 189 where it is compared with the input signal voltage VIN to produce as an output signal an error control signal equal to the difference between the two input signals.

The error control signal is applied to the control logic unit 179. The error control signal is employed by the control logic unit 179 to adjust a width of the pulses in the waveforms Wi and W2. This adjustment provides pulse width modulation.

In an example illustrated in FIG. 3, the control logic unit 179 includes a further comparator 191 to which the error control signal from the comparator 189 is applied as a first input signal via a connection 195.

The comparator 191 also receives a second input signal from a sawtooth waveform generator 193 via a connection 197. The comparator 191 produces a waveform output at an output connection 199 which comprises a waveform of pulses whose width is determined by the size of the error control signal from the comparator 189.

If the pulse width of the pulses of the waveform Wi is increased in the manner described, the electronic switch 153 is held on longer and the peak current in the inductor 165 is allowed to climb allowing the output voltage V to be increased. If the pulse width of the pulses of the waveform Wi is reduced, the electronic switch 153 is held on for less time and the peak current in the inductor 165 is reduced causing the output voltage V to be reduced. The output voltage is equal to the peak voltage pulse amplitude applied to inductor 165 times the duty cycle. The duty cycle is defined for a given cycle period as the time the electronic switch 153 is on divided by the total cycle period.

Thus the circuit 200 provides a suitable implementation of the switching regulator 107 shown in FIG. 1 by providing an output voltage which replicates the form of, i.e. follows the envelope of, the lower level input voltage VIN which is the control signal obtained from differential amplifier 112.

FIG. 4 is a block schematic diagram of an RF transmitter 200 embodying the invention. The transmitter may be a linear transmitter used for example in a communications mobile station or base transceiver station referred to earlier. The transmitter 200 includes a RF synthesizer 201 which generates a RF carrier signal. The synthesizer is connected to a modulator 202 in which the carrier signal is modulated with a modulation signal containing information to be carried by the carrier signal. The modulator 202 is connected to an amplifier 203 which may comprise one or more amplification stages, at least one of which is the power amplifier circuit 100 of FIG. 1. The amplifier 203 is connected to an antenna 205 via a switch 204. The switch 204 separates output RF signals delivered from the amplifier 203 to the antenna 205 from input RF signals received by the antenna 205 and delivered to a receiver (not shown) via a connection 206. The switch 204 may be replaced by another known separator device (not shown) such as an isolator or a circulator. The antenna 205 sends amplified, modulated RF signals provided as outputs by the amplifier 203 over-the-air to one or more distant receivers (not shown)

Claims

1. An amplifier circuit for use in a RF transmitter including an amplifying device having a first terminal to which an input signal is applicable, a second terminal and a third terminal, a voltage source for producing a supply voltage and a regulator for regulating the supply voltage to produce an output voltage for application to the second terminal to cause a direct current to flow through the amplifying device between the second terminal and the third terminal, wherein the amplifier circuit includes means for sampling the direct current between the second terminal and the third terminal and a feedback loop connected from the means for sampling to the regulator to provide a control signal representing the magnitude of the sampled direct current and wherein the regulator is operable to adjust the output voltage to have an envelope form which follows an envelope form of the control signal.

2. An amplifier circuit according to claim 1 wherein the regulator comprises a DC to DC converter circuit including an electronic switch, means for applying a drive waveform to the electronic switch, a load impedance and one or more reactive components and is operable to transfer electrical energy from the voltage source to an output terminal connected to the load impedance to produce the output voltage by repetitive pulsing of the electronic switch caused by the drive waveform.

3. An amplifier circuit according to claim 2 wherein the means for applying a drive waveform is operable to provide a drive waveform which has a pulse width modulation which is determined by the control signal from the means for sampling the direct current.

4. An amplifier circuit according to claim 3 including a feedback loop from the output terminal, a comparator which has a first input provided by the feedback loop from the output terminal and a second input provided by a connection from the means for sampling the direct current.

5. An amplifier circuit according to claim 4 wherein the means for applying a drive waveform includes a further comparator having a first input from the first mentioned comparator and a second input and including means for applying a sawtooth waveform to the second input of the further comparator.

6. An amplifier circuit according to claim 4 or claim 5 wherein the feedback loop from the output terminal of the regulator includes a voltage divider to divide down a sample of the output voltage.

7. An amplifier circuit according to any one of claims 2 to 6 wherein the regulator includes an inductor connected between the electronic switch and the load impedance, a capacitor connected in parallel with the load impedance to the inductor and a synchronous rectifier, having one terminal connected to the electronic switch and the inductor, operable to receive a further drive waveform from the means for applying a drive waveform.

18 - -

8. An amplifier circuit according to any one preceding claim which is operable as a linear amplifier in a class B operational mode.

9. An amplifier circuit according to any one preceding claim wherein the amplifying device is operable whereby the direct current flowing between the second and third terminals is proportional to the square root of the output power obtained by applying an RF signal at the first terminal.

10. An amplifier circuit according to any one preceding claim wherein the means for sampling current comprises a resistor connected between the regulator and the second terminal and a differential amplifier having input terminals connected to respective ends of the resistor.

11. An amplifier circuit according to claim 10 wherein the resistor comprises a shunt resistor connected to the second terminal of the amplifying device through an RF choke.

12. An amplifier circuit according to any one of the preceding claims wherein the amplifying device comprises a solid state amplifying device.

13. An amplifier circuit according to claim 12 wherein the amplifying device comprises a bipolar transistor or

an insulated gate field effect transistor.

14. An amplifier circuit according to any one of the preceding claims and substantially as herein described with reference to FIG. 1 of the accompanying drawings.

15. A RF transmitter including an amplifier circuit according to any one of the preceding claims.