GB2410584B - Simultaneous multi-threading processor circuits and computer program products configured to operate at different performance levels - Google Patents

Simultaneous multi-threading processor circuits and computer program products configured to operate at different performance levels

Info

Publication number
GB2410584B
GB2410584B GB0508862A GB0508862A GB2410584B GB 2410584 B GB2410584 B GB 2410584B GB 0508862 A GB0508862 A GB 0508862A GB 0508862 A GB0508862 A GB 0508862A GB 2410584 B GB2410584 B GB 2410584B
Authority
GB
United Kingdom
Prior art keywords
operate
computer program
program products
different performance
performance levels
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
GB0508862A
Other versions
GB0508862D0 (en
GB2410584A (en
Inventor
Gi-Ho Park
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/631,601 external-priority patent/US7152170B2/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Priority claimed from GB0403738A external-priority patent/GB2398660B/en
Publication of GB0508862D0 publication Critical patent/GB0508862D0/en
Publication of GB2410584A publication Critical patent/GB2410584A/en
Application granted granted Critical
Publication of GB2410584B publication Critical patent/GB2410584B/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1028—Power efficiency
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
GB0508862A 2003-02-20 2004-02-19 Simultaneous multi-threading processor circuits and computer program products configured to operate at different performance levels Expired - Lifetime GB2410584B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR20030010759 2003-02-20
US10/631,601 US7152170B2 (en) 2003-02-20 2003-07-31 Simultaneous multi-threading processor circuits and computer program products configured to operate at different performance levels based on a number of operating threads and methods of operating
GB0403738A GB2398660B (en) 2003-02-20 2004-02-19 Simultaneous multi-threading processors operating at different performance levels

Publications (3)

Publication Number Publication Date
GB0508862D0 GB0508862D0 (en) 2005-06-08
GB2410584A GB2410584A (en) 2005-08-03
GB2410584B true GB2410584B (en) 2006-02-01

Family

ID=34743283

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0508862A Expired - Lifetime GB2410584B (en) 2003-02-20 2004-02-19 Simultaneous multi-threading processor circuits and computer program products configured to operate at different performance levels

Country Status (1)

Country Link
GB (1) GB2410584B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9529727B2 (en) * 2014-05-27 2016-12-27 Qualcomm Incorporated Reconfigurable fetch pipeline

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0768608A2 (en) * 1995-10-13 1997-04-16 Sun Microsystems, Inc. Maximal concurrent lookup cache for computing systems having a multi-threaded environment
US5717892A (en) * 1995-01-17 1998-02-10 Advanced Risc Machines Limited Selectively operable cache memory
WO2001048599A1 (en) * 1999-12-28 2001-07-05 Intel Corporation Method and apparatus for managing resources in a multithreaded processor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5717892A (en) * 1995-01-17 1998-02-10 Advanced Risc Machines Limited Selectively operable cache memory
EP0768608A2 (en) * 1995-10-13 1997-04-16 Sun Microsystems, Inc. Maximal concurrent lookup cache for computing systems having a multi-threaded environment
WO2001048599A1 (en) * 1999-12-28 2001-07-05 Intel Corporation Method and apparatus for managing resources in a multithreaded processor

Also Published As

Publication number Publication date
GB0508862D0 (en) 2005-06-08
GB2410584A (en) 2005-08-03

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Legal Events

Date Code Title Description
PE20 Patent expired after termination of 20 years

Expiry date: 20240218