GB2405533A - Printed circuit board having through-hole vias and micro-vias - Google Patents

Printed circuit board having through-hole vias and micro-vias Download PDF

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Publication number
GB2405533A
GB2405533A GB0320353A GB0320353A GB2405533A GB 2405533 A GB2405533 A GB 2405533A GB 0320353 A GB0320353 A GB 0320353A GB 0320353 A GB0320353 A GB 0320353A GB 2405533 A GB2405533 A GB 2405533A
Authority
GB
United Kingdom
Prior art keywords
circuit board
printed circuit
hole
pad
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB0320353A
Other versions
GB0320353D0 (en
Inventor
Walter Bruessau
Rudi Ganss
Holger Krueger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to GB0320353A priority Critical patent/GB2405533A/en
Publication of GB0320353D0 publication Critical patent/GB0320353D0/en
Publication of GB2405533A publication Critical patent/GB2405533A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09627—Special connections between adjacent vias, not for grounding vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

A printed circuit board (PCB) for use with a ball grid array package (BGA) 15 comprises a plurality of etched copper layers and substrate layers, a grid of solder pads provided on an outer surface of the PCB for connection to the BGA and a grid of through hole vias 10 (TH via) which are situated between the solder pads. The TH vias are drilled, lined with a conductive layer and provided with a TH via pad situated beneath the surface. Each solder pad is electrically connected to an adjacent TH via in a layer beneath the outer surface. A micro-via 11 may be provided underneath each solder pad, and a copper layer etched to provide a connector 12 between the micro-via and the through hole via pad. A method of manufacture of the PCB is also claimed.

Description

A METHOD OF MANUFACTURING A PRINTED CIRCUIT BOARD
The present invention relates to a method of manufacturing a printed circuit board, in particular for use with a ball grid array (BOA) package.
BGA packages for integrated circuits have become increasingly popular as they are able to make more efficient use of the available space on the printed circuit board (PCB), than packages using pins or leads. As the pitch of BGA packages has reduced over the years, to a size of 0.8mm to 1.27mm today, the size of the solder pads required in corresponding positions on the PCB, in particular for hard ball arrays at around 0.7mm diameter, has remained the same, leading to a reduction in the free distance between each pad, to around 100,um. Given the number of pins in a typical BGA package (typically up to 1600), the majority of signal breakout is done in inner PCB layers. This, in turn requires that there be some means by which the soldered pins are connected to the respective layer. Conventionally, this is done in one of two ways. The first uses an array of through hole vies which are connected to the soldering pads using a dogbone geometry of connections on the surface of the PCB. This is shown in Fig. 1. An array of through hole via landing pads 1 is interleaved with an array of corresponding solder pads 2. The pads 1, 2 are joined by etched connectors 3, all on the top surface of the PCB. All of the top surface, bar the soldering pads and via pad holes, must be covered with soldering resist enamel, and blistering of this enamel during soldering must be avoided. For this, there must be a minimum free distance between a given via landing pad 1 and any of the four surrounding solder pads 2, which is typically between 0.15mm and 0.20mm. If blistering does occur, then there is a risk that solder will flow into the through hole via causing a lack of solder at the ball and a bad solder joint, and additionally a risk that an electrical short-circuit between the via pad 1 and solder pad 2 may occur. For thick PCB's, typically greater than l.5mm thickness, the minimum diameter of the via pad 1 must be at least 0.6mm and the drill must have at least 0.3mm diameter. An allowance of 50,um must be made for drill positioning error and a minimum copper edge of 100,um left to ensure good contact with the dogbone connector. Reducing the drill diameter below 0.3mm results in significant extra cost in the manufacturing process because such thin drills have a tendency to rupture frequently and must be replaced.
The second arrangement, shown in Fig. 2, uses buried vies which are connected to solder pads 4 on the surface of the PCB via micro-via pads 5 created in a first copper layer beneath the surface, located directly below the solder pad 4, and micro-vias 6 which connect to the micro-via pads 5. The normal procedure for manufacturing PCB's involves taking a substrate with copper on either side, etching the copper as necessary, applying a prepreg layer, then further etched copper and substrate layers. To join these layers together a process known as clenching is carried out. Each time this is done, there is the possibility of misalignment, so it is desirable to reduce the number of clenching steps used. For the buried via method of Fig. 2, a PCB is made up and through hole vies drilled, then additional prepreg, copper and substrate layers are applied on each side, so that the via openings are covered over. Thus, buried vies will always require an additional clenching step over the dogbone arrangement of Fig. l. This can increase the costs by between 15% and 25%. A further problem of using buried vies in PCB's which are more than 2mm thick, with vies of more than 1.7mm is that an additional hole sealing process is required because there is insufficient resin contained in the prepreg layer, between the top layer and a layer below, to fill up the buried via holes. For buried vies of greater than 2.5mm, a further clenching step is required because the holes must be made as two separate vies, then brought together. The chances of rejection of the PCB due to misalignment in this step are significant.
Conventionally, designers have had to choose between these methods and then.
accept the associated problems and expense. It is desirable to reduce the number of layers required and also to reduce the pitch of the BGA package which can be used with the PCB.
In accordance with a first aspect of the present invention, a method of manufacturing a printed circuit board for use with a ball grid array package, comprises assembling a printed circuit board comprising a plurality of etched copper layers and substrate layers; providing a grid of solder pads on an outer surface of the assembled printed circuit board for connection to the ball grid array package; forming through hole vies in the printed circuit board by drilling through the printed circuit board, applying a conductive layer to the drilled hole and providing a through hole via pad; wherein the through hole vies are formed as a grid in the printed circuit board, interleaved with the grid of solder pads; wherein the diameter of each through hole via pad is sufficiently small to enable a minimum free distance between each through hole via pad and each solder pad to be maintained; and wherein each solder pad is electrically connected to an adjacent through hole via in a layer beneath the outer surface.
In accordance with a second aspect of the present invention, a printed circuit board for use with a ball grid array package comprises a plurality of etched copper layers and substrate layers; a grid of solder pads provided on an outer surface of the assembled printed circuit board for connection to the ball grid array package; through hole vies formed in the printed circuit board, each lined with a conductive layer and provided with a through hole via pad; wherein the through hole vies are formed as a grid in the printed circuit board, interleaved with the grid of solder pads; wherein the diameter of each through hole via pad is sufficiently small to enable a minimum free distance between each through hole via pad and each solder pad to be maintained; and wherein each solder pad is electrically connected to an adjacent through hole via in a layer beneath the outer surface.
The present invention recognises that by setting the connection with a through hole via in a layer beneath the surface it is possible to reduce the size of the landing pad needed and so increase the density of the array of solder pads on the surface without suffering from short circuits. By taking the connections off the surface layer, the amount of free material needed to ensure a good connection to the through hole via is reduced, so the holes can be drilled without requiring particularly small diameter drills which are prone to failures. Removing the alternative of the dog bone structure prevents solder flowing away, so good solder joints are possible.
Any suitable connection beneath the outer surface can be made, as long as for connection of the BGA, a type of via, which is located directly under the solder pad and which does not require a larger landing pad than the solder pad, is used. Preferably, a micro-via is provided beneath each solder pad, and the first copper layer beneath the outer surface is etched to provide a connection between the micro-via and one of the adjacent through hole vies.
An example of a method of manufacturing a printed circuit board and a printed circuit board in accordance with the present invention will now be described with reference to the accompanying drawings in which: Figure 1 illustrates a conventional dogbone geometry; Figure 2 illustrates a conventional buried via breakout geometry; Figure 3 is a side view of a PCB showing different via types; Figure 4 illustrates a geometry resulting from the method of the present invention, viewed from above; and, Figure 5 shows a PCB manufactured in accordance with the method of the present invention.
In Fig. 3, a side view of a PCB shows examples of two different types of breakout, through hole vies 10 and micro-vias 11. The micro-vias only go part way through the PCB before being connected to an etched copper track 12 in a layer away from the surface. Through hole vies go from one side of the PCB 13 to another and are connected to the copper tracks 12 at different levels according to which components need to be connected. On the outer surface of the PCB, surface mount devices 14 such as capacitors or resistors, or integrated circuits 15 using ball grid array packages are mounted.
Fig. 4 illustrates the method of the present invention. In a surface layer 20 of the PCB, soldering pads 21 are provided in an array. Interleaved with this array, are holes 26 where through hole vies have been drilled through the PCB. In a first layer 22 beneath the surface are through hole via pads 23 to which are connected micro-vias 24 via connectors 25. The conductive layer of the through hole via and the through hole via pads 23 may be made by means of a suitable electro-plating technique and typically by galvanising the printed circuit board with copper. The micro- vias 24 connect the first layer 22 with the surface layer 20 and are positioned beneath each solder pad 21 on the surface layer 20.
Unlike the prior art methods, there is no connection on the top surface between the solder pads 21 and the through hole via landing pads 23 as required in the example of Fig. 1, nor 3 are buried vies necessary as required in the method of Fig. 2. Instead, the PCB is manufactured by drilling through holes vies in every location in which there would have been a buried via in the Fig. 2 example. These through hole vies are drilled using a drill having a diameter which does not result in frequent breakage, typically 0.3mm or greater and have a landing pad diameter which, for the example sizes given so far, is about 0.15mm less than with the conventional spacing requirement. This is because the connections are not made on the surface layer, so there is no need to have large minimum copper edges. The copper edges can be reduced by about 3/4, e.g. from 100pm to about 25,um. The size of the landing pads is now determined by the requirement for the through hole galvanization process to work effectively, not for enabling good connections on the surface.
A grid of holes appears on the surface away from which the integrated circuit is mounted, which would not appear if buried vies were used, but this does not severely affect component placement on that side, and on the side where the IC is mounted, the holes are beneath the body of the IC package anyway. As the diameter of the through hole vies is reduced with respect to a conventional through hole via, there is still surface space on the opposite surface to where the IC package is mounted, which can be used if surface connections are required or components must be placed. Generally, signalling lines will not be on the surface because of electromagnetic compatibility problems.
Fig. 5 shows an example of a PCB which has been designed for use with hard ball BGA's. These typically require solder landing pads of around 0. 70mm (as compared with solder pad diameters for other types of connection which tend to be of the order of 0.40mm to 0.50mm). The diameter of the manufactured solder pad 30 is 680pm and the diameter of the through hole via landing pad 31 is 450,um. The pitch 32 of the solder pad array is about lOOOpm and the separation 33 between the edges of adjacent solder pads and via landing pads is between lOO,um and 150,um. This PCB was tested and found to exhibit error free behaviour.
The financial savings possible from avoiding expensive additional clenching procedures during the PCB manufacture as compared with the buried via technique of Fig. 2 are of the order of 15% to 25% and for PCB's of thicknesses greater than 2mm, the saving is significantly higher. Given that these savings are per board, the overall impact to a company producing tens of thousands of boards in a year is considerable.
The invention is most applicable where the solder ball is large compared with the pitch of the BGA to be mounted on the PCB and the free distance is less than the size of the solder ball. Although the invention has been described with reference to ball grid array packages, it would be equally applicable to a PCB for use with any other package where there is a need to reduce the pitch and still maintain an acceptable separation between the vies and the solder pads.

Claims (4)

1. A method of manufacturing a printed circuit board for use with a ball grid array package, the method comprising: assembling a printed circuit board comprising a plurality of etched copper layers and substrate layers; providing a grid of solder pads on an outer surface of the assembled printed circuit board for connection to the ball grid array package; forming through hole vies in the printed circuit board by drilling through the printed circuit board, applying a conductive layer to the drilled hole and providing a through hole via pad; wherein the through hole vies are formed as a grid in the printed circuit board, interleaved with the grid of solder pads; wherein the diameter of each through hole via pad is sufficiently small to enable a minimum free distance between each through hole via pad and each solder pad to be maintained; and wherein each solder pad is electrically connected to an adjacent through hole via in a layer beneath the outer surface.
2. A method according to claim 1, wherein a micro-via is provided beneath each solder pad; wherein a first copper layer beneath the outer surface is etched to provide a connector; and wherein each solder pad is electrically connected to its adjacent through hole via by means of respective micro-vias and connectors.
3. A printed circuit board for use with a ball grid array package, the printed circuit board comprising a plurality of etched copper layers and substrate layers; a grid of solder pads provided on an outer surface of the assembled printed circuit board for connection to the ball grid array package; through hole vies formed in the printed circuit board, each lined with a conductive layer and provided with a through hole via pad; wherein the through hole vies are formed as a grid in the printed circuit board, interleaved with the grid of solder pads.
wherein the diameter of each through hole via pad is sufficiently small to enable minimum free distance between each through hole via pad and each solder pad to be maintained; and wherein each solder pad is electrically connected to an adjacent through hole via i: a layer beneath the outer surface.
4. A printed circuit board according to claim 3, wherein a micro-via is provided beneath each solder pad; wherein a first copper layer beneath the outer surface is etched to provide a connector; and wherein each solder pad is electrically connected to its adjacent through hole via by means of respective micro-vias and connectors.
GB0320353A 2003-09-01 2003-09-01 Printed circuit board having through-hole vias and micro-vias Withdrawn GB2405533A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB0320353A GB2405533A (en) 2003-09-01 2003-09-01 Printed circuit board having through-hole vias and micro-vias

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0320353A GB2405533A (en) 2003-09-01 2003-09-01 Printed circuit board having through-hole vias and micro-vias

Publications (2)

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GB0320353D0 GB0320353D0 (en) 2003-10-01
GB2405533A true GB2405533A (en) 2005-03-02

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8325416B2 (en) 2006-06-13 2012-12-04 Sharp Kabushiki Kaisha Re-writeable optical element and a display, reflector and backlight incorporating the same
US9881115B2 (en) 2016-04-27 2018-01-30 International Business Machines Corporation Signal via positioning in a multi-layer circuit board using a genetic via placement solver
US10037900B1 (en) 2017-05-09 2018-07-31 Nxp B.V. Underfill stop using via bars in semiconductor packages
US10657308B2 (en) 2015-06-22 2020-05-19 International Business Machines Corporation Signal via positioning in a multi-layer circuit board
US11570894B2 (en) 2020-05-15 2023-01-31 Rockwell Collins, Inc. Through-hole and surface mount printed circuit card connections for improved power component soldering

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5001605A (en) * 1988-11-30 1991-03-19 Hughes Aircraft Company Multilayer printed wiring board with single layer vias
US5758413A (en) * 1995-09-25 1998-06-02 International Business Machines Corporation Method of manufacturing a multiple layer circuit board die carrier with fine dimension stacked vias
EP0883330A1 (en) * 1997-06-03 1998-12-09 International Business Machines Corporation Circuit board with primary and secondary through holes
WO2000022894A1 (en) * 1998-10-13 2000-04-20 Sun Microsystems, Inc. Apparatus and system with increased signal trace routing options in printed wiring boards and integrated circuit packaging

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5001605A (en) * 1988-11-30 1991-03-19 Hughes Aircraft Company Multilayer printed wiring board with single layer vias
US5758413A (en) * 1995-09-25 1998-06-02 International Business Machines Corporation Method of manufacturing a multiple layer circuit board die carrier with fine dimension stacked vias
EP0883330A1 (en) * 1997-06-03 1998-12-09 International Business Machines Corporation Circuit board with primary and secondary through holes
WO2000022894A1 (en) * 1998-10-13 2000-04-20 Sun Microsystems, Inc. Apparatus and system with increased signal trace routing options in printed wiring boards and integrated circuit packaging

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8325416B2 (en) 2006-06-13 2012-12-04 Sharp Kabushiki Kaisha Re-writeable optical element and a display, reflector and backlight incorporating the same
US10657308B2 (en) 2015-06-22 2020-05-19 International Business Machines Corporation Signal via positioning in a multi-layer circuit board
US9881115B2 (en) 2016-04-27 2018-01-30 International Business Machines Corporation Signal via positioning in a multi-layer circuit board using a genetic via placement solver
US10037900B1 (en) 2017-05-09 2018-07-31 Nxp B.V. Underfill stop using via bars in semiconductor packages
US11570894B2 (en) 2020-05-15 2023-01-31 Rockwell Collins, Inc. Through-hole and surface mount printed circuit card connections for improved power component soldering

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