GB2393601A - One-bit steerable multi-channel, multi-beam loudspeaker array - Google Patents

Abstract

A loudspeaker system with one or more multi-channel digital audio inputs and/or two or more single channel digital audio inputs, a digital signal processing system with one or more internal system clocks, driving an array of more than ten acoustic-output transducers, and a plurality of semiconductor power switches to amplify signals to signal levels adapted to drive the transducers, the system being capable of producing two or more independently steerable beams of sound, the sound in each beam corresponding to the content of one channel only or a combination of two or more of the channels of the digital audio inputs, wherein the digital signal processing system comprises a plurality of one-bit modulators to reduce the bit-width of an input to one bit, wherein the outputs of the modulators are connected to operate the solid state power switches.

Description

239360 1

( DIGITAL LOUDSPEAKER SYSTEM

FIELD OF THE INVENTION

5 This invention relates to a device including an array of electroacoustic transducers capable of receiving a multi channel audio input signal and to produce independently steerable and focusable beams of audible sound at a level suitable for home entertainment or professional sound 10 reproduction applications. More specifically, the invention relates to improving the signal processing and power conversion circuit required to generate steerable beams of audible signals. BACKGROUND OF THE INVENTION

The commonly-owned published international patent application no. WO0123104 and the international Patent application no. PCT/GB02/01472 describe arrays of transducers and their use to 20 achieve a variety of effects. The applications describe methods and apparatus for receiving an input signal, replicating it a number of times and modifying each of the replicas before routing them to respective output transducers such that a desired sound field is created. This sound field may comprise a

25 directed beam, focussed beam or a simulated origin. The digital loudspeaker array system described in those applications can also be referred to as sound projector in analogy to light beam emitting systems.

30 To generate a so-called surround-sound environment where a listener is immersed in a sound field emitted from distributed

sources, beams of sound generated by the sound projector are reflected from surfaces such as ceiling and walls back to the listener. The listener perceives the sound beam as if emitted 35 from an acoustic mirror image of a source.

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In operation, each transducer requires a replica of the input signal after some signal processing operations such as mixing, compensation, delay, noise filtering and windowing.

In the examples of WO-0123104 and PCT/GB02/01472, the internal digital signals are converted into signals capable of driving an electro-acoustic transducer by means of a pulse-width modulator (PWM) and a switching power circuit, often referred 10 to as switching or class-D amplifier. The PWM receives its input from a noise shaping circuit that essentially acts as a (re-) quantizer reducing the bit-width of the digital audio signal, e.g. from 16 or 24 bit to 8 bit, whilst removing part of the quantization noise from the audible frequency range.

However, the PWM stage constitutes a complex part of the above loudspeaker system. It is therefore a particular object of the invention to provide a digital loudspeaker system or sound projector capable to accept as input digital data samples 20 representing one or more channels of digitized audio sound material and to produce for such input channels independently steerable and focusable beams of audible sound, with simplified signal processing and amplification systems compared to known sound projectors.

SUGARY OF THE INVENTION

The digital loudspeaker system of this invention is a digital electroacoustic device, more specifically a digitally driven 30 array of electroacoustic transducer or sound projector, adapted to accept digital data samples representing one or more channels of digitized audio sound material as input, and adapted to produce, for each such input channel, an independently steerable and focusable beam of audible sound, at 35 a level suitable for home entertainment or professional sound - 2 -

reinforcement applications using suitable digital processing means. According to a first aspect of the invention, the loudspeaker 5 system comprises a plurality of electroacoustic transducers with the appropriate driver stages wherein input the driver stages are connected to the output of one-bit modulators.

A one-bit modulator outputs a series of essentially identical 10 pulses varying between either two or three signal levels. The latter is equivalent to identical pulses with a (changing) sign and can be referred to 1.5-bit modulator (instead of l-bit modulator). For the scope of the present invention "one-bitH is meant to include 1.5-bit modulators. A particular class of such 15 modulators is known as sigma-delta or deltasigma modulators.

The use of a three-level signal modulator with zero level has the advantage of reducing the average power consumption of the loudspeaker system compared to the two-level signal.

The power drivers are preferably power transistor, or more specifically power FETs (field effect transistor), circuits

known as half or full bridges.

25 These and other aspects of inventions will be apparent from the following detailed description of non-limitative examples and

drawings. 30 BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic drawing of a typical set-up of a loudspeaker system in accordance with the present invention; - 3

FIG. 2 is a block diagram of a first part of a digital loudspeaker system; FIG. 3 is a block diagram of a second part of a digital 5 loudspeaker system; FIG. 4 is a block diagram of a third part of a digital loudspeaker system; 10 FIG. 5 shows a signal processing element in accordance with the present invention for use in the loudspeaker system of FIGs.l 4; FIGS. 6A,B illustrate the signal output of the signal 15 processing element of FIG. 5; FIG. 7 is a schematic diagram of a semiconductor power switch to amplify the output signals of the element of FIG. 5; 20 FIG. 8 is the apparatus of FIG. 2 including elements in accordance with an example of the invention; FIG. 9 is the apparatus of FIG. 3 including elements in accordance with an example of the invention; and FIG. 10 is a simulated output of a loudspeaker system in accordance with the present invention in response to a 2 kHz input signal.

30 DETAILED DESCRIPTION

There now follows a description of a preferred embodiment of

the first aspect of the present invention, which, as will become apparent, utilises also the techniques of the other 35 above-described aspects.

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Referring to FIG.1, a digital loudspeaker system or sound projector 10 includes an array of transducers or loudspeakers 11 that is controlled such that audio input signals are emitted 5 as a beam or beams of sound 12-1, 12-2. The beams of sound 12 1, 12-2 can be directed into - within limits - arbitrary directions within the half-space in front of the array. By making use of carefully chosen reflection paths, a listener 13 will perceive a sound beam emitted by the array as if 10 originating from the location of its last reflection or -more precisely- from an image of the array as reflected by the wall, not unlike a mirror image.

In FIG. 1, two sound beams 12-1 and 12-2 are shown. The first 15 beam 121 is directed onto a side-wall 161, which may be part of a room, and reflected in the direction of the listener 13.

The listener perceives this beam as originating from an image of the array located at or behind the reflection spot 17, thus from the right. The second beam 12-2, indicated by dashed 20 lines, undergoes two reflections before reaching the listener 13. However, as the last reflection happens in a rear corner, the listener will perceive the sound as if emitted from a source behind him or her.

25 Whilst there are many uses to which a digital sound projector could be put, it is particularly advantageous in replacing conventional surroundsound systems employing several separate loudspeakers placed at different locations around a listener's position. The digital sound projector, by generating beams for 30 each channel of the surround-sound audio signal and steering those beams into the appropriate directions, creates a true surround-sound at the listener position without further loudspeakers or additional wiring.

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Making now reference to FIGs. 2 to 4, components of a digital sound projector system are described in the following as known from the above referenced patent applications W0-0123104 and PCT/GB02/01472.

Referring now to FIG.2, at the input, common-format audio source material in Pulse Code Modulated (PCM) form is received from devices such as compact disks (CDs), digital video disks (DVDs) etc. by the digital sound projector as either an optical 10 or coaxial digital data stream in the S/PDIF format. But other input digital data formats can be also used. This input data may contain either a simple two channel stereo pair, or a compressed and encoded multi-channel soundtrack such as Dolby Digitaltm 5. 1 or DTStm, or multiple discrete digital channels of 15 audio information.

Encoded and/or compressed multi-channel inputs are first decoded and/or decompressed in a decoder 21 using the devices and firmware available for standard audio and video formats. An 20 analogue to digital converter (not shown) is also incorporated to allow connection (AUX) to analogue input sources which are immediately converted into a suitably sampled digital format.

The resulting output comprises typically three, four or more pairs of channels. In the field of surround-sound, these

25 channels are often referred to left, right, centre, surround (or rear) left and surround (or rear) right channels. Other channels may be present in the signal such as the low frequency effect channel (LFE).

30 These channels or channel-pairs are each fed into a two-channel samplerate-converter (SRC) 22, allowing the internal system clocks to be independent of the source data-clock.

Alternatively each channel can be passed through a single channel SRC) for re-synchronisation and re-sampling to an 35 internal (or optionally, external) standard sample-rate clock - 6

(SSC) (typically about 48.8kHz or 97.6kHz) and bus width (typically 24 bit). This sample rate conversion eliminates potential problems due to clock speed inaccuracy, clock drift, and clock incompatibility. The SRCs provide this 5 synchronization, as well as isolation from the interference of any external data clocks. Finally, where two or more of the digital input channels have different data-clocks (as for example stemming from separate digital microphone systems), then again the SRCs ensure that internally all disparate 10 signals are synchronized.

The outputs of the SRCs are converted to 8 channels of 24-bit words at an internally generated sample rate of 48.8kHz.

15 A digital signal processing (DSP) stage 23 performs filtering of the digital audio data input signals for enhanced frequency response equalization to compensate for the irregularities in the frequency response (i.e. transfer function) of the acoustic output-transducers used in the final stage of the digital sound 20 projector. The number of separately processed channels may optionally at this stage be reduced by combining additively the (one or more) low-frequency-effects [LFE] channel(s) with one or more of the 25 other channels, for example the centre channel, in order to minimise the processing beyond this stage. However, if a separate sub-woofer system is to be used with the transducer array or if the system has sufficient processing power, then more discrete channels may be maintained throughout the 30 processing chain.

The DSP stage 23 also performs anti-alias and tone control filtering on all eight channels, and over-sampling and interpolation to an overall eight-times oversampled data rate, 35 creating 8 channels of 24-bit word output samples at 390 kHz.

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Signal limiting and digital volume-control is performed in this DSP stage too.

The DSP stage includes one or more (typically two or three) 5 digital signal processor units. These may be Texas Instruments TMS320C6701 DSPs running at 133MHz, and the DSPS either perform the majority of calculations in floating-point format for ease of coding, or in fixedpoint format for maximum processing speed. Alternatively, especially where fixed-point calculations 10 are being performed, the digital signal processing can be carried out in one or more Field Programmable Gate Array (FPGA)

units being available from Manufactures such as Xilinx. A further alternative is a mixture of DSPs and FPGAs. Some or all of the signal processing may alternatively be implemented with 15 customized silicon in the form of an Application Specific Integrated Circuit (ASIC).

A microprocessor, typically based on an ARM (RTM) core, in the control user interface unit 24 generates timing delay data for 20 the transducers of the array, from real-time beam-steering settings sent by the user to the digital sound projector via an remote control or an interfacing computer device. Given that the digital sound projector is able to independently steer each of the output channels (one steered output channel for each 25 input channel, typically 4 to 6), there are a large number of separate delay computations to be performed. This number is equal to the number of steered output channels times the number of transducers. If the digital sound projector is also capable of dynamically steering each beam in real-time, the 30 computations also need to be performed without noticeable delay. Once computed, the delay requirements or times are distributed to the FPGAs of the DSP stage 23 (where the delays are actually applied to each of the streams of digital data samples) over the same parallel bus as the digital data samples 8 -

themselves. The ARM core in the control user interface 24 also handles all system initialization and external communications.

The signal stream enters the FPGA logic that controls high 5 speed static buffer RAM devices 25 to produce the required delays applied to the digital audio data samples of each of the eight channels, with a discretely delayed version of each channel being produced for each of the output transducers (256 in this implementation).

Apodisation, or array aperture windowing, where graded weighting factors are applied to the signals for each transducer, as a function of each transducer's distance from the centre of the array, to control beam shape, is applied 15 separately in the FPGA to each channel's delayed signal versions. Applying apodisation at this stage of the digital signal processing allows different output sound beams to have differently tailored beam-shapes. These separately delayed and separately windowed digital sample streams, one for each of 8 20 channels and for each of the 256 transducers making 2048 delayed versions in total are then summed in the FPGA for each transducer to create an individual 390kHz 24-bit signal for each of the 256 transducer elements. The apodisation or array aperture windowing, may optionally be performed after the 25 summing stage for all of the channels at once (instead of for each channel separately, prior to the summing stage) for simplicity, but in this case each sound beam output from the digital sound projector will have the same window function which may not be optimal.

In the known device, the two hundred and fifty-six signals of 24-bit width and at 390kHz are then each passed through a quantizing/noise shaping circuit also implemented in the FPGA of the DSP stage 23 to reduce the data sample word lengths to 8 35 bits at 390kHz, whilst maintaining a high signal-to-noise-ratio 9

(SNR) within the audible band (i.e. the signal frequency band from 2OHz to 2OkHz).

The data stream with reduced sample word width is distributed 5 in 26 serial data streams at 31.25 Mb/s each and additional volume data. Each data stream is assigned to one of 26 driver boards. The driver circuit boards, as shown in FIG. 4, which are 10 preferably physically local to the transducers 31 they drive, provide a pulse-width-modulated class-BD output driver circuit for each of the transducers they control. In the example of PCT/GB02/01472, each driver board is connected to ten transducers, whereby the transducers are directly connected to i 15 the output of the class-BD output driver circuits without any intervening lowpass-filter (LPF).

Each PWM generator 32 drives a class-D power switch or output stage 33, which directly drives one transducer, or a series-or 20 parallelconnected pair of adjacent transducers. The supply voltage unit 34 to the class-D power switches can be digitally adjusted to control the output power level to the transducers.

By controlling this supply voltage over a wide range, e.g. 10:1, the power to the transducer can be controlled over a much 25 wider range, 100:1 for a 10:1 voltage range, or in general N2:1 for an N:1 voltage range.

The supply voltage variation is performed by low-loss switching regulators mounted on the same printed circuit boards (PCBs) as 30 the class-D power switches. There is one switching regulator for each class-D switch to minimise power supply line inter modulation. To reduce cost, each switching regulator can be used to supply pairs, triplets, quads or other integer multiples of class-D power switches.

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A typical transducer 31 has a diameter small enough to ensure approximately omnidirectional radiation from the transducer up to high audio frequencies (e.g. > 12kHz to 15kHz) is important if the loudspeaker array system is to be able to steer beams of 5 sound at small angles from the plane of the transducer array.

Thus, a transducer diameter of between 5mm and 30mm is considered to be the optimum for whole audio-band coverage. A transducer-to-transducer spacing small compared with the shortest wavelengths of sound to be emitted by the digital 10 sound projector is desirable to minimise the generation of "spurious sidelobes of acoustic radiation (i.e. beams of acoustic energy produced inadvertently and not emitted in the desired direction(s)). Practical considerations on possible transducer sizes suggest that transducer spacing in the range 15 5mm to 45mm is advantageous for most applications.

As illustrated by FIG. 4, the digital sound projector user interface produces overlay graphics for on-screen display of setup, status and control information, on any suitably 20 connected video display, e.g. a plasma screen. To this end, the video signal from any connected audiovisual source (e.g. a DVD player) may be looped through the digital sound projector en route to the display screen where the digital sound projector status and command information is then also overlaid on the 25 programme video. If the process delay of the signal processing operations from end to end of the digital sound projector are sufficiently long, (e.g. when the length of the compensation filter running on the first two DSPs which depends on the transducer linearity and the equalization required, is long) an 30 optional video frame store can be incorporated in the loop through video path, to re-synchronise the displayed video with the output sound. This step avoids problems known as lip-sync.

l / The above configuration of a loudspeaker system or sound projector has been described in the co-owned applications WO-

0123104 and PCT/GB02/01472.

5 In an example of the present invention, it was found that employing 1.5bit modulators combined with the noise shaping circuit could reduce the number of components. Such modulators are known per se in the art. A suitable example of a modulator is described for example within the United States patent no. 10 5,087,914. In that document a 1-bit modulator in combination with a DC calibration system is used as an Analog-to- Digital (A/D) converter. While for the remaining elements 21, 22 of the loudspeaker system reference can be made to FIGs.1-4 above, the quantization/noise shaper implemented within the DSP or FPGA 15 circuit 23 is configured as 1.5-bit modulator. As a consequence, the PWM stage described in the previous example is no longer required: the three-level output signals of the 1.5 bit modulator can be directly used as means to trigger the power switching stage.

Referring now to FIG. 5, there is illustrated a block diagram of a deltasigma modulator that converts a 24-bit digital signal into a 1.5-bit digital stream. Each of the two hundred and fifty-six signals at 24-bit width and 390kHz provide an 25 input to a delta-sigma modulator. Its entry node is a summing junction connected to a first stage of integration. In FIG. 5, a summing junction is denoted with +H while an integrator is denoted with 1/(1-z**(-1)) in z-Transform notation with "**" indicating an exponent. The output of the first stage of 30 integration is input to a summing junction, the output of which is input to a second stage of integration. The output of the second stage of integration is input to the input of a third stage of integration. The output of the third stage of integration is input to a summing junction, the output of which 35 is input to the input of a fourth stage of integration. The - 12

output of the fourth stage of integration is input to the input of a fifth stage of integration. The outputs of each of the stages of integration are fed forward to a summing junction.

The feed forward paths have gain coefficients al, a2, al, ad 5 and as, respectively.

In the present example, the coefficients are set to (negative) powers of 2 to facilitate the implementation of the 1.5-bit modulator in fixed- point logic. Their values are 1, 1/2, 1/8, 10 1/64 and 1/512 for al, a2, al, a4 and as, respectively. Whilst an implementation in fixed-point logic is preferable in terms of speed and costs, floating-point logic may be used as an alternative. When using floating-point logic, the restraints on the values for the feed-forward loops are less stringent. In 15 both types of logic, other values can be found in accordance with the known theory of filter design to achieve a stable filter. The output of the final summing stage is fed into a quantizer 20 which - in the present example - allows to forward the sign of the signal together with the two-level signal itself.

Effectively, the quantizer is a three level quantizer with output signals levels at full scale, zero and minus full scale, often referred to as a 1. 5-bit quantizer. The output is 25 connected via a decoder to the input of the power switches.

Details of the decoder and the output signal it generates are illustrated in FIGs.6A,B below. However, the output is also subtracted from the next input signal by connecting it to the summing junction at the entry node. Again, the z-Transform 30 notation (z**(-1)) is used to indicate delay elements in the circuit diagram of FIG. 5.

The 1-bit modulator includes two feedback loops having gain coefficients bl and b2, respectively, associated therewith. The 35 values for the feedback coefficients are 1/1024 and 1/4096 - 13

(2**(-15)), respectively, to place zeros in the audio band at approximately 15.5 kHz and 7.2 kHz. In each feedback loop, there is a onestep delay element.

5 The values of the above coefficients are chosen to optimise performance and stability. The stability of the modulator can be further improved by introducing a clipping threshold at each integrator stage or by introducing further gain adjustments.

The clipping replaces the signal value for any value above a 10 predetermined threshold by the threshold value. The integrators of the example clip at 4, 16, 64, 256 and 1024, measured in quantization step size, respectively.

The output of the 1-bit modulator is defined as a three level 15 signal representing 1, 0 and -1, respectively. The signal is encoded as a 1-bit level and a 1-bit sign signal. The output is decoded by the decoder 60 shown in FIG. 6A. The decoder consists essentially of a group of AND gates 61 with an inverter 62. The circuit shows the 3 state output from the 20 quantizer represented in logic levels. There is a 3.072 MHz square wave clock (with a 50:50 mark space ratio) which gates the output from the first two gates. The output from the final gates is transferred to the inputs of the power switches of Fig 7 below via a complementry MOSFET level converter (not shown).

25 In practice, some of the above gates may be implemented as latches. A sample signal is shown in FIG.6B. The circuit ensures a return to zero between every signal pulse with a 1:1 mark-space 30 ratio. The pulse edges are idealized and may be subject to slew-rate control to smoothen the transition between the levels. The output signal of the 1-bit modulator is fed directly into 35 the power switch stage 70 of FIG. 7 without further modulation.

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The power switch can be implemented in a full- or half-bridge configuration as known per se in the art.

A full bridge circuit of FIG. 7 includes two pairs of power 5 MOSFET transistors 72 capable of switching signal levels of 30 Volts with a transducer 71 as load coupled to the drains. The left branch is active on positive signals, the right half of the bridge activates on negative pulses. The volume control unit of the digital sound projector controls the supply voltage 10 Vvol. The switching frequency of the bridge is approximately 64*48 kHz = 3.072 MHz (or 6 Mhz for a 1:1 mark space ratio as shown in FIG. 6).

The above example can be modified in various aspects. For example a twolevel 1-bit modulator could be used.

Alternatively, the full or H-bridge may be replaced by a half bridge power switch.

A block diagram of the modified sound projector is shown in 20 FIGs. 8 and 9. Identical numerals to those used in FIGs. 2 and 3 are used throughout except for those elements that are modified or replaced in light of the present invention.

Referring now to FIG. 8, the input section 21, 22 and the first 25 stages of the digital processing section 23 are those described above. The noiseshaping section and the quantizer are replaced by 1.5-bit modulators 83 that generate a signal output at 3072 kHz or 6 MHz at the 1:1 mark space ratio for the N driver circuits. No clock is required beyond this point as the output 30 can be fed directly into the modified driver circuits 93 of which n are shown in FIG. 9.

In FIG. 10 a simulated output of the above example is shown, illustrating is a plot of the power spectrum of a 2 kHz signal 35 into the three state modulator operating are 64*48 kHz. The -

feed-forward and feedback coefficient values are those given above. The integrators clip at 4, 16, 64, 256 and 1024, respectively. The two zeros are due to the values of bl and b2.

The ordinate indicates the power level in dB. The SNR is 5 measured to be 115 dB (by comparing the energy in 0-5 kHz band with energy in the 5-20 kHz frequency band).

Claims (6)

1. ! CLAIMS

   A loudspeaker system adapted to receive one or more multi channel digital audio inputs and/or two or more single 5 channel digital audio inputs, comprising a digital signal processing system with one or more internal system clocks, an array of more than ten electro-acoustic transducers and a plurality of semiconductor power switches to amplify signals to signal levels adapted to drive said 10 transducers, said system being capable of producing two or more independently steerable beams of sound, the sound in each beam corresponding to one of said channels only or a combination of two or more of said channels of said digital audio inputs, wherein said digital signal 15 processing system comprises a plurality of one-bit modulators to reduce the bit-width of an input to one bit, wherein the outputs of said modulators are connected to operate said solid state power switches.

   20
2. 2. The loudspeaker system of claim 1 comprising more than 20 transducers.
3. 3. The loudspeaker system of claim 1 wherein the modulators reduce the digital signal to one bit and a sign 25 information or a three level signal.
4. The loudspeaker system of claim 1 wherein the output of the modulators is a sequence of pulses with a signal level returning to zero level for a finite time between a pulse 30 and the following pulse of said sequence.
5. 5. The loudspeaker system of claim 1 wherein the power switches include a full bridge circuit with at least four solid state power transistors.

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   (
6. 6. The loudspeaker system of claim 5 wherein the power switches are connected to a voltage source controlled in accordance with the volume setting of the loudspeaker system. - 18