GB2393286A

GB2393286A - Method for finding a local extreme of a set of values associated with a processing element by separating the set into an odd and an even position pair of sets

Info

Publication number: GB2393286A
Application number: GB0309207A
Authority: GB
Inventors: Mark Beaumont
Original assignee: Micron Europe Ltd
Current assignee: Micron Europe Ltd
Priority date: 2002-09-17
Filing date: 2003-04-23
Publication date: 2004-03-24
Anticipated expiration: 2023-04-23
Also published as: GB0309199D0; GB0309206D0; GB2393287B; GB2393287A; GB2393279B; GB2393279A; GB2393280A; GB0309198D0; GB0309207D0; GB2393290A; GB2393290B; GB2393285B; GB0309209D0; GB2393288A; GB2393284B; GB2393282A; GB2393286B; GB0309211D0; GB0309205D0; GB0309212D0

Abstract

A method for finding the local extrema of a set of values associated with a processing element is disclosed. The set of values is separated into an odd numbered set and an even numbered set, the extrema of each set is then determined and the local extrema of the whole set is finally found. The values can be loaded from the first odd position into a first register, and from a first even position into a second register. The value in the first register is then loaded in to a third register, and the value in the second register is loaded into a fourth register. Then the value in the next odd/even position is loaded into the first/second register. The odd/even extrema can then be determined by comparing the values in the first/second registers with the values in the third/fourth registers. The selected extrema from the two pairs of registers is then stored in the third and fourth registers and the next odd and even values are loaded into the first and second registers to be compared with the stored values. Also disclosed is the use of eight registers for working with short values given by a least and most significant byte.

Description

( METHOD FOR FINDING LOCAL EXTREMA OF A SET

OF VALUES FOR A PARALLEL PROCESSING ELEMENT

BACKGROUND OF THE [NVENTION

100021 The present invention relates generally to parallel processing and more particularly to determining an extreme (e.g., maximum or minimum) from a set of values within a single processing element of a parallel processing system.

[00031 Conventional central processing units ("CPU's"), such as those found in most personal computers, execute a single program (or instruction stream) and operate on a single stream of data. for example, the CPU fetches its program and data from a random access memory ("RAM"), manipulates the data In accordance with the program instructions, and writes the results back sequentially. There is a single stream of instructions and a single stream of data (note: a single operation may operate on more than one data item, as in X = Y + Z. however, only a single stream of results is produced). Although the C PU may determine the sequence of instructions executed in the program itself, only one operation can be completed at a time. Because conventional ('PlJs execute a single program (or instruction stream) and operate on a single stream of data, conventional CPUs may be referred to as a single-instruction, single data CPU or an SISD CPU.

100041 The speed of conventional CPUs has dramatically increased in recent years.

Additionally, the use of cache memories enables conventional CPUs faster access to the desired instruction and data streams. However because conventional ('I'lJs can complete only one operation at a time, conventional CPUs are not suitable for extremely demanding applications having large data sets (such as moving image processing, high quality speech recognition, and analytical modeling applications, among others).

( 1 51 Improved performance over conventional SISD CPUs may be achieved by building systems which exhibit parallel processing capability. Typically, parallel processing systems use multiple processing units or processing elements to simultaneously perform one or more tasks on one or more data streams. For example in one class of parallel processing system, the results of an operation from a first CPU are passed to a second CPU for additional processing, and from the second CPU to another CPU, and so on. Such a system, commonly known as a "pipeline", is referred to as a multiple-instruction, single-data or MISD system because each CPU receives a different instruction stream while operating on a single data stream. Improved performance may also be obtained by using a system which contains many autonomous processors, each running its own program (even if the program running on the processors is the same code) and producing multiple data streams. Systems in this class are referred to as a multiple-instruction, multiple-data or MIMD system.

100061 Additionally, improved performance may be obtained using a system which has multiple identical processing units each performing the same operations at once on different data streams. The processing units may be under the control of a single sequencer running a single program. Systems in this class are referred to as a single-instruction, multiple data or SIMD system. When the number of processing units in this type of system is very large (e.g., hundreds or thousands), the system may be referred to as a massively parallel SIMD system.

100071 Nearly all computer systems now exhibit some aspect of one or more of these types of parallelism. For example, MMX extensions arc SIMD; multiple processors (graphics processors, etc) are MIMD; pipelining (especially in graphics accelerators) is MISD.

Furthermore, techniques such as out of order execution and multiple execution units have been used to introduce parallelism within conventional CPUs as well.

100081 Parallel processing is also used in active memory applications. An active memory refers to a memory device having a processing resource distributed throughout the memory structure. The processing resource is most often partitioned into many similar processing elements (PEs) and is typically a highly parallel computer system. By distributing the processing resource throughout the memory system, an active memory is able to exploit the very high data bandwidths available inside a memory system. Another advantage of active memory is that data can be processed "on-chip" without the need to transmit the data across a system bus to the CPU or other system resource. Thus, the work load of the Cl'[) may be reduced to operating system tasks, such as scheduling processes and allocating system resources. 100091 A typical active memory includes a number of interconnected l'Es which are capable of simultaneously executing instructions sent from a central sequencer or control unit. T he PEs may be connected in a variety of di ffercnt arrangements depending on the design

( requirements for the active memory. For example, PEs may be arranged in hypercubes, butterfly networks, one-dimensional strings/loops, and twodimensional meshes, among others. 10010] A typical PE may contain data, for example a set of values, stored in one or more registers. In some instances, it may be desirable to determine the extreme (e.g., the highest or lowest value) of the set of values. Conventional methods for finding the extreme, however, often results in a number processing cycles being "lost." A lost cycle may refer to, for example, a cycle in which the PE must wait to complete a calculation because the necessary data has yet to be transferred into or out of the PK.

100111 Thus, there exists a need for a method for determining the extreme of a set of values on a parallel processor such that the resources of the parallel processing system are maximized. More specifically, there exists a need for a method for determining the extreme of a set of values on a parallel processing element of an active memory such that the resources of the active memory are maximized.

SUMMARY OF THE INVENTION

[00121 One aspect of the present invention relates to a method for finding a local extreme for a processing element having a set of values associated therewith. The method comprises separating the set of values into an odd numbered set and an even numbered set, determining an odd extreme from the odd numbered set, determining an even extreme from the even numbered set, and determining the local extreme from the odd extreme and the even extreme.

100131 The method may further include loading a value from an odd position within the set into a first register, loading a value from an even position within the set into a second register and transferring the value in the first register to a third register, loading a value from a next odd position within the set into the first register and transferring the value in the second register to a fourth register, and loading a value from a next even position within the set into the second register.

100141 The present invention enables the extreme of a set of values to be determined while maximizing the resources of a 1'E. '1'he present invention may be performed using the hardware and software (i.e., the local processing capability) of each PE within the array.

Those advantages and benefits, and others, will become apparent from description of the

invention below.

( BRIEF DESCRIPTION OF THE DRAWINGS

l0015l To enable the present invention to be easily understood and readily practiced, the present invention will now be described for purposes of illustration and not limitation, in connection with the following figures wherein: 100161 FIG. I is a block diagram illustrating an active memory according to an embodiment of the present invention.

[00171 FIG. 2 is a block diagram of a processing element for the active memory illustrated in FIG. I according to an embodiment of the present invention.

[00181 FIG. 3 is a more detailed illustration of the processing elements of FIG. 2 according to an embodiment of the present invention.

9] FIG. 4 illustrates an operational process for determining an extreme of set of values on a processing element as illustrated in FIGS. 2 and 3 according to an embodiment of the present invention.

[00201 FIG. 5 is a graphical representation of the results of the operational process illustrated in FIG. 4 according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

100211 As discussed above, parallel processing systems may be placed within one or more classifications (e.g., MISD, MIMD, SIMD, etc.). For simplicity, the present invention is discussed in the context of a SIMD parallel processing system. More specifically, the present invention is discussed in the context of a SIMD active memory. It should be noted that such discussion is for clarity only and is not intended to the limit the scope of the present invention in any way. The present invention may be used for other types and classifications of parallel processing systems.

[00221 FIG. I is a block diagram illustrating an active memory 10 according to an embodiment of the present invention. It should be noted that the active memory 10 is only one example of a device on which the methods of the present invention may be practiced and those of ordinary skill in the art will recognize that the block diagram of FICl. I is an overview of an active memory device 10 with a number of components known in the art being omitted for purposes of clarity.

[00231 Active memory 10 is intended to be one component in a computer system.

Processing within active memory 10 is initiated when the active memory 10 receives commands from a host processor (not shown), such as the computer system's CPU. A complete processing operation (i.c., data movement and processing) in the active memory 10 may consist of a sequence of many commands from the host to the active memory device 10.

( 10024] Active memory 10 is comprised of a host memory interface ("HMI") 12, a bus interface 14, a clock generator 16, a task dispatch unit ("TDU") 18, a DRAM control unit ("DCU") 20, a DRAM module 22, a programmable SRAM 24, an array control sequencer 26, and a processing element array 28, among others.

5] The HMI 12 provides an input/output channel between the host (such as a CPU, not shown) and the DRAM module 22. In the current embodiment, the HMI 12 receives command (cmd), address (addr), and data signals (among others) from and sends data and ready (ray) signals (among others) to the host. The HMI 12 approximates the operation of a standard non- active memory so that the host, without modifications, is compatible with the active memory 10.

100261 The I tMI 12 may be similar in its operation to the interface of a synchronous DRAM as is know in the art. Accordingly, the host must first activate a page of data to access data within a DRAM module 22. In the current embodiment, each page may contain 1024 bytes of data and there may be 16,384 pages in all. Once a page has been activated, it can be written and read through the HMI 12. The data in the DRAM module 22 may be updated when the page is deactivated. The HMI 12 also sends control signals (among others) to the DCU 20 and to the processing element array 28 via the task dispatch unit 18.

[00271 The HMI 12 may operate at a frequency different than that of the frequency of the master clock. For example, a 2x internal clock signal from clock generator 16 may be used.

Unlike a traditional DRAM, the access time for the HMI 12 uses a variable number of cycles to complete an internal operation, such as an activate or deactivate. Thus the ready signal (ray) is provided to allow the host to detect when a specific command has been completed.

[00281 The bus interface 14 provides an input/output channel bctwocn the host and the TDU 18. For example, the bus interface 14 receives column select (cs), write command (w), read command (r), address (addr), and data signals (among others) from and places interrupt (intr), flag, and data signals (among others) onto the system bus (not shown). The bus interface 14 also receives signals from and sends signals to TI)U 18.

10029] The clock generator 16 is operable to receive an external master clock signal (xl) and operable to provide the master clock signal (x 1) and one or more internal clock signals (x2, x4, x8) to the components of the active memory. It should be apparent to one skilled in the art that other internal clock signals may be produced by the clock generator 16.

100301 The TDU 18 communicates with the bus interface 14, the IIMI 12, the programmable SRAM 24, the array control sequencer 26, and the DCU 20. In the current embodiment, the TDU 18 functions as an interface to allow the host to issue a sequence of commands to the array control sequencer 26 and the DCU 20. Task commands from the host may be buffered in the TDIJ's FIFO buffers to allow a burst command to be issued. ('ommands may contain

( information on how the tasks in the array control sequencer 26 and the DCU 20 should be synchronized with one another, among others.

10031] The DCU 20 arbitrates between the TDU 18 and the HMI 12 and sends commands to the DRAM modules 22 and the processing element array 28. The DCU 20 also schedules refreshes within the DRAM modules 22. In one embodiment, the DRAM modules 22 of the active memory 10 may be comprised of sixteen 64k x128 eDRAM (or embedded DRAM) cores. Each eDRAM core may be connected to an array of sixteen PEs, thus requiring 256 (16 x 16) PEs in all.

100321 The programmable SRAM 24 functions as a program memory by storing commands issued by the TDU 18. For example, the TDU 18 may transmit a "write program memory address" command which sets up a start address for a write operation and a "write program memory data" command which writes a memory location and increments the program memory write address, among others. The programmable SRAM 24, in the current embodiment, has both an address register and a data output register. l 100331 The array control sequencer 26 is comprised of a simple 16 bit minimal instruction set computer (16-MISC). The array control sequencer 26 communicates with the TDU 18, the programmable SRAM 24, and the DCU 20, and is operable to generate register file addresses for the processing element array 28 and operable to sequence the array commands, among others. 100341 The processing element array 28 is comprised of a multitude of processing elements ("PEs") 30 (see FIG. 2) connected in a variety of different arrangements depending on the design requirements for the processing system. For example, processing units may be arranged in hypercubes, butterfly networks, one-dimensional strings/loops, and two dimensional meshes, among others. The processing element array 28 communicates with the DRAM module 22 and executes commands received from the programmable SRAM 24, the array control sequencer 26, the DCU 20, and the IIMI 12. Each PE in the processing element array 28 includes dedicated 11registers for communication with the HMI 12. Control of the H-registers is shared by the HMI 12 and the DCIJ 20.

100351 Referring now to laid. 2, a block diagram of a PE 30 according to one embodiment of the present invention is illustrated. PE 30 includes an arithmetic logic unit ("ALU") 32, Q registers 34, M-registers 36, a shift control and condition register 38 (also called "condition logic" 38), a result register pipeline 40, and register file 42. The PE 30 may also contain other components such as multiplexcrs 48 and logic gates (not shown), among others.

100361 In the current embodiment, the Q-registers 34 are operable to merge data into a floating point format and the M-Registers 36 are operable to de-mcrgc data from a floating point format into a single magnitude plus an exponent format, among others. I he ALU 32

i includes a multiplier-adder operable (among others) to receive information from the Q registers 34 and M-registers 36, execute tasks assigned by the TDU 18 (see FIG. 1), and transmit results to the condition logic 38 and to the result register pipeline 40. The result register pipeline 40 is operable to communicate with the register file 42, which holds data for transfer into or out of the DRAM modules 22 via a DRAM interface 44. Data is transferred between the PE and the DRAM module 22 via a pair a registers, one register being responsive to the DCU 20 and the other register being responsive to the BE 30. The DRAM interface 44 receives command information from the DCU 20. The DRAM interface 44 also permits the PE 30 to communicate with the host through the host memory access port 46.

100371 In the current embodiment, the [I-registers 42 are comprised of synchronous SRAM and each processing element within the processing element array 28 contains eight H-registers 42 so that two pages can be stored from different DRAM locations, thus allowing the interleaving of short do bursts to be more efficient. Result register pipeline 40 is also connected to one or more neighborhood connection registers ("X-register") (not shown). The l X-register links one PE 30 to its neighboring PE's 30 in the processing element array 28.

10038] FIG. 3 is a more detailed illustration of some components of the processing element of FIG. 2 according to an embodiment of the present invention. For example in FIG. 3, M registers 36 include four (4) registers Me - M3 each having an associated multiplexer MMP0 - MMP3, respectively, which receive signals from, among others, the result pipe 40 via multiplexer 54. The output of registers M0 - M3 are connected to ALU 32 via multiplexer 52. 100391 Additionally, result pipe 40 includes four (4) registers R0, Rl, R2, and X, as well as several multiplexers (i. e., RMP I, RMP2, XMP). The output of registers R0, Rl, and R2 may be sent, for example, to M-registers 36 via multiplexer 54 and to the ALU 32 via multiplexer 50 and multiplexer 52 (connections not shown). It should be noted that multiplexer 50 may also receive the output signals (connections not shown) from Q-registers 34 (not shown) among others.

100401 ALU 32 includes a 16-bit multiplier adder ("MA") and a logic unit, among others. In the current embodiment, the MA is designed to allow twoscompliment addition or subtraction and signed magnitude addition or subtraction. The logic unit is designed to allow logical functions between two arguments such as bit-wise OR and AND functions, among others. (condition logic 38 includes 7, N. and C flag registers, as well as an SCR register. As illustrated, the MA and the logic unit communicate with the C flag register via multiplexer 56 and with the SCR register and the result pipe 40 via multiplexer 58.

100411 It should be noted that the PE illustrated in FIG. 3 has a number of components, signal lines, and connections omitted for clarity. It should be apparent to those skilled in the

art that additional components, signal lines, and connections may added while remaining within the scope of the present invention. For example, QRegisters 34 (as shown in FIG. 2) including registers Q0 - Q3 and associated multiplexers QMP0 QMP3, respectively, may be added while remaining within the scope of the present invention. The output of each register Q0 - Q3 may be connected to multiplexer 50. Furthermore, it should become apparent to l those skilled in the art that, with minor changes, the present invention may be implemented using the Q-registers 34 (among others) instead of M-registers 36 while remaining within the scope of the present invention.

2] The reader desiring more information about the hardware shown in FIGs. I - 3 is directed to UK Patent application (serial no. not yet assigned) entitled "Control of Processing Elements in Parallel Processors" filed 17 September 2002, (Micron no. 02-1604) which is hereby incorporated by reference. Details about the PEs may also be found in UK Patent Application No. 021562.2 entitled "Host Memory Interface for a Parallel Processor" filed 17 September 2002, (Micron no. 02-0703) which is hereby incorporated by reference.

100431 FIG. 4 illustrates an operational process 70 for determining the local extreme of a set of values on a single PK. The position of each value within the value set may be designated as {1, 2, 3, 4, N} and thus, depending on its position within the set, a value may be designated as either "odd numbered" or "even numbered." For example, an "odd numbered value" refers to those values located at an odd numbered position within the value set. For simplicity, the value set {4, 10, 8, 9} will be used in conjunction with the discussion of operational process 70 as illustrated in FIG. 4. The odd numbered values in the current embodiment, for example, are values 4 and 8 located at positions I and 3, respectively.

Similarly, an "even numbered value" refers to those values located at an even numbered position within the value set. T he even numbered values in the current embodiment, for example, are values 10 and 9 located at positions 2 and 4, respectively.

100441 It should be noted that in the current embodiment, each value of the set is represented by 8-bits (i.e., 1-byte) of information within the PET and the values, as seen by each l'E, are in binary format. However for simplicity, the values are represented in decimal format in the instant discussion. Accordingly, the set may be represented as {byte-l, byte-2.

byte-3, byte4}, where the numerals I - 4 represent each byte's location within the set, thus byte- I = 4, byte-2 = 10, byte-3 = 8, and byte-4 = 9.

100451 It should be apparent to one skilled in the art that operational process 70 can be used to find the extreme of a PE having a larger or smaller set of values and that the length of the value may be scaled while remaining within the scope of the current invention.

10046] Operational process 70 begins with operation 71. Operation 71 may be split into sub operations 71a and 71 b. In sub-operation 7 la, the first address for an odd numbered value is

selected from the register file 42. It should be noted that in the current embodiment, the array control sequencer 26 designates the address within the register file 42 for the selected odd numbered value in increasing order (e.g., from byte-l, byte-3, N), however, another order of selection may be used while remaining within the scope of the present invention. Thus in the current embodiment, the address for byte-l is selected in sub-operation 71a.

100471 In sub-operation 70b, the first address for an even numbered value is selected from the register file 42. It should be noted that in the current embodiment, the array control sequencer 26 designates the address within the register file 42 for the selected even numbered value in increasing order (e.g., from byte-2, byte-4, N), however, another order of selection may be used while remaining within the scope of the present invention. Thus in the current embodiment, the address for byte-2 is selected in sub-operation 71b.

l0048l After operation 71 is completed, the odd numbered value located in the register file 42 at the address location selected in sub-operation 71 a is loaded into a first register and the address for the next odd numbered value is selected from the register file 42 in operation 72.

It should be noted that the first register may be referred to as the "odd input register" because only odd numbered values (e.g., byte-1, byte-3, byte-5, etc.) are stored within the first register. In the current embodiment, the value for byte-1 (i.e., 4) is loaded into register Rl (i. e., within the result pipe 40) via the multiplexer RMP 1 and the address for byte-3 is selected from the register file 42.

100491 After the odd numbered value is loaded into the first register and the address for the next odd numbered value is selected in operation 72, the following three actions take place in operation 73: the odd numbered value is transferred from the first register into a third register, the even numbered value at the address selected in sub-operation 71 b is loaded into a second register, and the address for the next even numbered value is selected from the register file 42.

The third register is used to store the odd extreme, it is initialized with the first odd value placed into the odd pipeline (e.g., byte-l). It should be noted that the second register may be referred to as the "even input register" because only even numbered values (e.g., byte-2, byte 4, byte-6, etc.) are stored within the second register.

100501 In the current embodiment, the value of byte-1 (i.e., 4) is transEcrrcd from register R1 to register M 1 via the multiplexer 52 and multiplexer MMP 1. The value of byte-2 (i.e., 10) is loaded into register R2 via the multiplexer RMP2. Additionally, the address of byte-4 is selected from register file 42. It should be noted that in the current embodiment, the register M I is initialized with the value of byte-1 (i.e. , 4).

[00511 In operation 74, the next odd numbered value is loaded into the first register, the even numbered value is transferred from the second register to the fourth register, and the address for a next odd numbered value is selected from register file 42. The fourth register is used to

( store the even extreme, it is initialized with the first even value placed into the even pipeline (e.g., byte-2).

l0052l In the current embodiment, the value of byte-3 (i.e., 8) is loaded into register Rl via the multiplexer RMP1, the value of byte-2 (i.e., 10) is transferred from register R2 to register M2 via the multiplexer 52 and multiplexer MMP2. It should be noted that in the current embodiment, the register M2 is initialized with the value of byte-2 (i.e., 10).

100531 In operation 75, the value within the first register is compared to the value within the third register to obtain an odd extreme and the next even numbered value is loaded into the second register. The values within the first register and the third register are loaded into the ALU's 32 Multiplier/Adder (MA) and Logic Unit and one value is subtracted from the other.

For example in the current embodiment, the MA subtracts the value contained in the third register from the value contained in the first register (here, the value of byte-l is subtracted from the value of byte3). If the result is negative (i.e., if the value within the third register is greater than the value within the first register), then flag C in the control logic 38 is set to zero (0). If the result is positive or zero (i.e., the value within the first register is greater than or equal to the value within the third register), then flag C in the control logic 38 is set to one (1). 10054] In the current embodiment for example, the value associated with byte-3 (i.e., 8) which is contained in register Rland the value associated with byte-1 (i.e., 4) which is contained within register Ml are loaded into the MA, and the value of byte4 (i.e., 9) is loaded into register R2 via the multiplexer RMP2. The value within M 1 is subtracted from the value within Rl, thus yielding 8 - 4 = 4, a positive value. Accordingly, flag C is set to 1.

It should be apparent to those skilled in the art that other types of comparisons may be used while remaining within the scope of the present invention, for example, subtracting the value of byte-3 from the value of byte-1.

100551 In operation 76, the value of the odd extreme is conditionally updated within the third register. The value of Oag C determined in operation 75 is used to conditionally update the odd extreme in the third register. For example in the current embodiment, if the largest value on the PE is to be found (i.e., the high cxtrcma), then the value of byte-3 will be loaded into Ml if nag C is equal to one (1), whereas the value of byte-1 will remain in Ml if flag C is equal to zero (0). In this case, register M I may be referred to as the "odd max register" because the largest odd numbered value that has thus far been found by the process is stored in register Ml. On the contrary if the smallest value on the PE is to be found (i.e., the low extreme), then the value of byte-3 will beloaded into M 1 if flag C is equal to zero (0), whereas the value of byteI will remain in M I if flag C is equal to one ( I). In this case, register M I may be referred to as the "odd min register" because the smallest odd numbered

value that has thus far been found by the process is stored in register M 1. In the current embodiment where the high extreme of the set of values within the PE is being determined, then the value of byte-3 (i.e., 8) is stored within register M I because flag C was set equal to one (1) when byte-1 was subtracted from byte-3.

l0056l Additionally in operation 76, the value within the second register is compared to the value within the fourth register to obtain another value for flag C. This new value for flag C will be used to update the values of the even extreme. The values within the second register and the fourth register are loaded into the ALU's 32 Multiplier/Adder (MA) and Logic Unit and one value is subtracted from the other. For example in the current embodiment, the MA subtracts the value contained in the fourth register from the value contained in the second register (here, the value of byte-2 is subtracted from the value of byte4). If the result is negative (i.e., if the value within the fourth register is greater than the value within the second register), then flag C in the control logic 38 is set to zero (0). If the result is positive or zero (i.e., the value within the second register is greater than or equal to the value within the fourth register), then flag C in the control logic 38 is set to one (1).

100571 In the current embodiment for example, the value associated with byte4 (i.e., 9) which is contained in register R2 and the value associated with byte-2 (i.e., 10) which is contained within register M2 are loaded into the MA. The value within M2 is subtracted from the value within R2, thus yielding 9 - 10 = -1, a negative value. Accordingly, flag C is set to zero (0). It should be apparent to those skilled in the art that other types of comparisons may be used while remaining within the scope of the present invention, for example, subtracting the value of byte4 from the value of byte-2.

100581 In operation 77, the value of the even extreme is conditionally updated within the fourth register. The value of flag C determined in operation 76 is used to conditionally update the even cxtrcma in the fourth register. For example if the largest value on the PE is to be found (i.e., the high extreme), then the value of bytc4 will be loaded into M2 if flag C is equal to one (I), whereas the value of byte-2 will remain in M2 if flag C is equal to zero (0).

In this case, register M2 may be referred to as the "even max register" because the largest even numbered value that has thus far been found by the process is stored in register M2. On the contrary if the smallest value on the PE is to be found (i.e., the low extreme), then the value of byte4 will be loaded into M2 if flag C is equal to zero (0), whereas the value of byte-2 will remain in M2 if flag C is equal to one (1). In this case, register M2 may be referred to as the "even min register" because the smallest even numbered value that has thus far been found by the process is stored in register M2. In the current embodiment where the high extreme of the set of values within the PE is being detcrmincd, the value of byte-2 (i.e.,

10) remains within register M2 because flag C was set equal to zero (O) when byte-2 was subtracted from byte 4.

100591 The above process is repeated until the (odd) extreme of the set of odd numbered values have been found, and the (even) extreme of the set of even numbered values has been found. Then, in operation 78, the local extreme for the PE is found by comparing the odd extreme to the even extreme.

l0060l The odd and even extremes, contained within the third and fourth registers, respectively, are loaded into the ALlJ-MA and one value is subtracted from the other. For example, the even extreme is subtracted from the odd extreme. If the result is negative (i.e., the even extreme is greater than the odd extreme), then flag C in the control logic 48 is set to zero (0). If the result is positive or zero(i.e., the odd extreme is greater than or equal to the even extreme), then flag C in the control logic 48 is set to one (l). In the current embodiment, the odd extreme and even extreme that are compared in operation 78 are the values remaining within registers Ml and M2, respectively. Thus for the set of values {4, 10, 8, 9}, for example, the value of the even extreme (i.e., 10) is subtracted from the value of the odd extreme (i.e., 8), thus yielding 8 10 = -2, a negative value. Accordingly, flag C is set to zero (O) 100611 It should be apparent to those skilled in the art that other types of comparisons may be used while remaining within the scope of the present invention, for example, subtracting the value of the odd extreme from the value of the even extreme. Also the input data may be loaded into other registers for the purposes of comparison within the ALU.

[00621 In the current embodiment, the odd extreme in M I is loaded into register RO. The even extreme in M2 is subtracted from RO. A flag (2 is generated. The flag C is used to conditionally update the value of the fourth register (i.e., M2), which now holds the local extreme. [00631 In operation 79, the value of flag C, as discussed in conjunction with operation 78, is used to conditionally update the value of the local extreme in the fourth register. For example if the largest value on the PE is to be found (i.e., the high cxtrema), then the odd extreme will be loaded into the fourth register if flag C is equal to one ( I), whereas the even extreme will remain in the fourth register if nag C is equal to zero (0). ()n the contrary if the smallest value on the PE is to be found (i.e., the low cxtrema), then the odd cxtrema will be loaded into the fourth register if flag C is equal to zero (0), whereas the even extreme will remain in the fourth register if flag C is equal to one (1). For example in the current embodiment where the high extreme of the set of values within the PE is being determined, then the value of the even extreme (i.e., 10) remains in register M2 because nag C was set equal to zero (0). It should be

( noted that the local extreme may be returned from register M2 to the register file 42 or sent the X register, among others.

[oO64] As previously mentioned, the discussion of operational process 70 was limited to finding the local extreme for a PE having a set of only four values (i.e., byte-l through byte 4). It should be noted, however, that operational process 70 may be scaled for any number of values stored on the PK. For example, FIG. 5 is a graphical representation of the results obtained using operational process 70 for a set of values having greater that four (4) bytes according to an embodiment of the present invention.

100651 Referring to FIG. 5, it should be noted that each row of the first several rows represent the results obtained using operational process 70 after one cycle, or clock pulse.

The first row, for example, represents the results obtained after operation 71 is completed wherein the address for the first odd and even numbered bytes (i.e., byte-l and byte-2, respectively) is selected from the register file 42. Similarly, the second row represents the results of operation 72 wherein the value of byte-1 is loaded into register Rl and the address for the next odd numbered byte (i.e., byte-3) is selected from the register file 42. Similarly, the third and fourth rows represent the results of operations 73 and 74, respectively.

6] Referring to the fourth row, in addition to the results discussed above in conjunction with operation 75, the address of the next odd byte in the set (i.e., byte-5) is selected from register file 42 for a PE having more than four values in the set. Likewise referring to the fifth row, in addition to the results discussed above in conjunction with operation 76, the value of byte4 is loaded into register R2 and the address for the next even byte of the set (i.e., byte-6) is selected from register file 42. Values for each odd and even numbered byte will be alternately fed through the PK. As operational process 70 continues, the value of each subsequent odd numbered byte is compared to the value of the odd extreme that is saved in register M I and any updated odd extreme is saved back into M 1. Additionally, the value of each subsequent even numbered byte is compared to the even extreme that is saved in register M2 and any updated even extreme is saved back into M2. I he odd extreme and even extreme are not compared to each other (i.e., as in operation 78) until the extreme for all of the odd bytes in the set and the extreme for all of the even bytes in the set have been finally determined. Thus, operational process 70 can be scaled for any number of bytes within a set.

100671 As discussed above, the length of the value may also be scaled while remaining within the scope of the current invention. For example in an alternative embodiment, operational process 70 is employed for finding the extreme of local shorts, wherein a "short" refers to a 1 6-bit value. As discussed above, the PE is an 8-bit processing element, thus each short requires two cycles to be processed. In the current alternative embodiment, each short is processed as two separate bytes, a "most significant" MS byte and a "Icast significant" (LS)

( byte. The convention used in the current alternative embodiment is known as "big-endian", that is the MS byte is stored in the LS-register file address.

100681 As the shorts are read from the register file (RF), they are separated into the odd and even data streams as discussed above. However, in the current alternative embodiment, both registers MO and Ml are used to hold a short within the even data stream (LS even byte in MO and MS even byte in Ml) and both registers M2 and M3 are used to hold a short within the odd data stream (LS odd byte in M2 and MS odd byte in M3). Additionally, registers QO and Q I are used to conditionally store the even extreme LS byte and the even extreme MS byte, respectively, and registers Q2 and Q3 are used to conditionally store the odd extreme LS byte and the odd extreme MS byte, respectively.

10069] The shorts are loaded into the ALU and a comparison of the odd extreme LS byte and MS byte to the next odd LS byte and next odd MS byte, respectively, is completed. Likewise, a comparison of the even extreme LS byte and MS byte to the next even LS byte and next even MS byte, respectively, is completed. A comparison of the LS and MS odd extreme bytes to the LS and MS even extreme bytes is then completed to determine a local extreme for the PK.

10070] In the following embodiment, short- I, short-3, etc. form the stream of odd numbered values, and short-2, shorty, etc. form the stream of even numbered values. The movement of the shorts throughout the PE can be divided into a series of clock pulse, or cycles. It should be noted that all operations within a cycle happen simultaneously. Thus if a register is being "read from" and "written to" in the same cycle, the "old" data moves out of the register at the same time that the "new" data moves into the register. Accordingly, the old data is not lost.

In the following example, the old contents of a particular register will be that value written to the register during the cycle the immediately preceding the current cycle. If a value was not written to the particular register during the cycle immediately preceding the current cycle, the old contents of the register will be the last value written to the register during the closest preceding cycle to the current cycle. During processing, certain actions take place in each cycle. 100711 In the first cycle, the I,S byte of short-l is loaded into register R 1. It should be noted that the "first cycle" assumes that the LS and MS bytes have already been read from the register file.

[00721 In the second cycle, the I,S byte of short-l is loaded from register Rl into register M2, and the MS byte of short-l is loaded into register Rl.

100731 In the third cycle, the Q2 register (which holds the I,S byte for the odd extreme) is initialized with M2 (the I,S byte of the first short for the odd stream), the MS byte of short-l

( is loaded from register Rl into register M3, and the LS byte of short-2 is loaded into register Rl. 100741 In the fourth cycle, the Q3 register (which holds the MS byte for the odd extreme) is initialized with M3 (the MS byte of the first short for the odd stream), the LS byte of short-2 is loaded from register Rl into register MO, and the MS byte of short-2 is loaded into register Rl. 100751 In the fifth cycle, the QO register (which holds the LS byte for the even extreme) is initialized with MO (the LS byte of the first short for the even stream), the MS byte of short-2 is loaded from register Rl into register Ml, and the LS byte of short-3 is loaded into Rl.

100761 In the sixth cycle, the values of Q2 and Rl are compared, the Ql register (which holds the MS byte for the even extreme) is initialized with M I (the MS byte of the first short for the even stream), the LS byte of short-3 is loaded from register Rl into register M2, and the MS byte of short-3 is loaded into Rl.

10077] In the seventh cycle, the values of registers Q3 and Rl are compared, the MS byte of short-3 is loaded from register Rl into register M3, and the LS byte of short-4 is loaded into Rl. 100781 In the eight cycle, the contents of register Q2 are conditionally updated with M2, the values of QO and Rl are compared, the LS byte of shorty is loaded from register R1 into register MO, and the MS byte of shorty is loaded into Rl.

100791 In the ninth cycle, the contents of register Q3 are conditionally updated with M3, the values of Ql and Rl are compared, and the MS byte of short-4 is loaded from register Rl into register Ml.

100801 In the tenth and eleventh cycles, the contents of registers QO and Q 1, are conditionally updated with MO and M I respectively.

100811 It should be recognized that the above-described embodiments of the invention are intended to be illustrative only. For example, the architecture could be scaled to find the extreme of any sized input value, e.g. 4 byte value ('long'), or 8 byte value('long long').

Thus, to cope with 8 byte value, the architecture would need to be extended to 16 Q registers and 16 M registers. Numerous alternative embodiments may be devised by those skilled in the art without departing from the scope of the following, claims.

Claims

( What is claimed is:

I. A method for finding a local extreme for a processimg element having a set of values associated therewith, the method comprising: separating said set of values into an odd numbered set and an even numbered set; determining an odd extreme from said odd numbered set; determining an even extreme from said even numbered set; and determining said local extreme from said odd extreme and said even extreme.
2. The method of claim I wherein said separating said set of values into an odd numbered set and an even numbered set comprises: loading a value from an odd position within said set into a first register; loading a value from an even position within said set into a second register and transferring said value in said first register to a third register; loading a value from a next odd position within said set into said first register and transferring said value in said second register to a fourth register; and loading a value from a next even position within said set into said second register.
3. The method of claim 2 wherein said determining an odd extreme from said odd numbered set comprises comparing the value in said first register to the value in said third register.
4. T he method of claim I wherein said determining further comprises: selecting the greater value from said first register and said third register if a high odd extreme is desired; and selecting the lesser value from said first register and said third register if a low odd extreme is desired.
5. The method of claim I wherein said determining an even extreme from said even set of values comprises comparing the value in said second register to the value in said fourth register.
6. The method of claim 5 wherein said determining further comprises: selecting the greater value from said second register and said fourth register if a high even extreme is desired; and selecting the lesser value from said second register and said fourth register if a low even extreme is desired.

(
7. The method of claim I wherein said determining said local extreme from said odd extreme and said even extreme further comprises: selecting the greater value from said odd extreme and said even extreme if a local high extreme is desired; and l selecting the lesser value from said odd extreme and said even extreme if the local low extreme is desired.
8. The method of claim I further comprising: storing said odd extreme in said third register; loading another value from an odd position within said set into said first register; comparing the value in said first register to the value in said third register; and repeating said storing, loading and comparing steps for remaining values within an odd position within said set.
9. The method of claim 5 further comprising: storing said even extreme in said fourth register; loading another value from an even position within said set into said second register; comparing the value in said second register to the value in said fourth register; and repeating said storing, loading and comparing steps for remaining values within an even position within said set.
10. The method of claim I wherein said separating said set of values into an odd numbered set and an even numbered set comprises: loading a f rst portion of an odd numbered value within said set into a first register; transferring said first portion of said odd numbered value from said first register into a second register and loading a second portion of said odd numbered value into said first register; transferring said second portion of said odd numbered value from said first register into a third register and loading a first portion of an even numbered value from within said set into said first register;

( transferring said first portion of said even numbered value from said first register into a fourth register and loading a second portion of said even numbered value into said first register; transferring said second portion of said even numbered value from said first register into a fifth register.
11. The method of claim I wherein said separating said set of values into an odd numbered set and an even numbered set comprises: loading said least significant byte of a short value from an odd position within said set into a first register; transferring said least significant byte of a short from an odd position in said first register to a second register and loading said most significant byte of said short value from said odd position within said set into said first register; transferring said most significant byte of a short from an odd position in said first register to a third register, loading said least significant byte of a short value from an even position within said set into said first register, and initializing a fourth register with said least significant byte of a short from an odd position in said second register; transferring said least significant byte of a short value from an even position within said set from said first register to a sixth register, loading said most significant byte of said short value from said even position within said set into said first register, and initializing a fifth register with said most significant byte of a short from said odd position in said third register; transferring said most significant byte of said short value from said even position within said set from said first register to a seventh register, loading a least significant byte of a short value from another odd position within said set into said first register, and initializing a eighth register with said Icast significant byte of a short from said even position in said sixth register; transferring said least significant byte of said short value from said another odd position within said set from said first register to said second register, loading a most significant byte of said short value from said another odd position within said set into said first register, and initializing a ninth register with said most significant byte of a short from said even position in said seventh register; transferring said most significant byte of said short value from said another odd position within said set from said first register to said third register, and loading a least significant byte of a short value from another even position w ithin said set into said first rcgistcr;

( transfemng said least significant byte of said short value from said another even position within said set from said first register to said sixth register, and loading a most significant byte of said short value from said another even position within said set into said first register; and transferring said most significant byte of said short value from said another even position within said set from said first register to said seventh register.
12. The method of claim 11 wherein said determining an odd extreme from said odd numbered set comprises comparing said least significant byte of said short value from said odd position within said set to said least significant byte of said short value from said another odd position within said set and comparing said most significant byte of said short value from said odd position within said set to said most significant byte of said short value from said another odd position within said set.
13. The method of claim I I wherein said determining an even extreme from said even numbered set comprises comparing said least significant byte of said short value from said even position within said set to said least significant byte of said short value from said another even position within said set and comparing said most significant byte of said short value from said even position within said set to said most significant byte of said short value from said another even position within said set.
14. A method comprising: identifying bytes of data within a data stream as having one of an odd or an even position; processing said bytes of data having an odd position to produce an odd extreme; processing said bytes of data having an even position to produce an even extreme; and determining a local extreme from said odd extreme and said even extreme.
15. I he method of claim 14 wherein said processing said bytes of data having an odd position and processing said bytes of data having an even position comprises: loading a byte of data having an odd position into a first register; loading a byte of data having an even position into a second register and transferring said byte of data in said first register into a third register; loading a byte from a next odd position within said data stream into said first register and transferring said byte of data in said second register into a fourth register;

comparing said byte of data in said first register to said byte of data in said third register to produce said odd extreme and loading a byte of data from a next even position within said data stream into said second register; and comparing said byte of data in said second register to said byte of data in said fourth register to produce said even extreme. l
16. The method of claim I S wherein said processing said bytes of data having an odd position to produce an odd extreme further comprises: selecting the greater valued byte from said first register and said third register if a high odd extreme is desired; and selecting the lesser valued byte from said first register and said third register if a low odd extreme is desired.
17. The method of claim I S wherein said processing said bytes of data having an even position to produce an even extreme further comprises: selecting the greater valued byte from said second register and said fourth register if a high even extreme is desired; and selecting the lesser valued byte from said second register and said fourth register if a low even extreme is desired.
18. The method of claim 15 wherein said determining a local extreme from said odd extreme and said even extreme further comprises: selecting the greater valued byte from said odd extreme and said even extreme if a local high extreme is desired; and selecting the lesser valued byte from said odd extreme and said even extreme if the local low extreme is desired.
19. The method of claim 15 further comprising: storing said odd extreme in said third register; loading another byte from an odd position within said data stream into said first register; comparing the byte within said first register to the byte within said third register; and repeating said storing, loading and comparing steps for remaining bytes within an odd position within said data stream.

l
20. The method of claim 15 further comprising: storing said even extreme in said fourth register,' loading another byte from an even position within said data stream into said second register; comparing the byte within said second register to the byte within said fourth register; and repeating said storing, loading and comparing steps for remaining bytes within an even position within said data stream.
21. A method for determining a local extreme for a processing element, comprising: loading odd numbered bytes of data into a first plurality of registers; loading even numbered bytes of data into a second plurality of registers; comparing certain of said loaded odd numbered bytes to produce an odd extreme; comparing certain of said loaded even numbered bytes to produce an even extreme; and producing a local extreme in response to said odd extreme and said even extreme.
22. The method of claim 21 wherein said loading odd numbered bytes of data into a first plurality of registers comprises: loading a byte of data having an odd position into a first register; transferring said byte of data in said first register into a third register; and loading a byte from a next odd position within said data stream into said first register.
23. The method of claim 21 wherein said loading even numbered bytes of data into a second plurality of registers comprises: loading a byte of data having an even position into a second register; transEcrring said byte of data in said second register into a fourth register; and loading a byte of data from a next even position within said data stream into said second register.
24. The method of claim 22 wherein said comparing certain of said loaded odd numbered bytes to produce an odd extreme comprises comparing said byte of data in said first register to said byte of data in said third register to produce said odd extrcma.

(
25. The method of claim 23 wherein said comparing certain of said loaded even numbered bytes to produce an even extreme comprises comparing said byte of data in said second register to said byte of data in said fourth register to produce said even extreme.
26. The method of claim 24 wherein said comparing certain of said loaded odd numbered bytes to produce an odd extreme further comprises: storing said odd extreme in said third register; loading another byte from an odd position within said data stream into said first register; comparing the byte within said first register to the byte within said third register; and repeating said storing, loading and comparing steps for remaining bytes within an odd position within said data stream.
27. The method of claim 25 wherein said comparing certain of said loaded even numbered bytes to produce an even extreme further comprises: storing said even extreme is said fourth register; loading another byte from an even position within said data stream into said second register; comparing the byte within said second register to the byte within said fourth register; and repeating said storing, loading and comparing steps for remaining bytes within an even position within said data stream.
28. 'I'he method of claim 14 wherein said processing said bytes of data having an odd position and processing said bytes of data having an even position comprises: loading said least significant byte of a short value from an odd position within said set into a first register; transferring said least significant byte of a short from an odd position in said first register to a second register and loading said most significant byte of said short value from said odd position within said set into said first register; transferring said most significant byte of a short from an odd position in said first register to a third register, loading said least significant byte of a short value from an even position within said set into said first register, and initializing a fourth register with said least significant byte ot'a short from an odd position in said second register:

( transferring said least significant byte of a short value from an even position within said set from said first register to a sixth register, loading said most significant byte of said short value from said even position within said set into said first register, and initializing a fifth register with said most significant byte of a short from said odd position in said third register; transferring said most significant byte of said short value from said even position within said set from said first register to a seventh register, loading a least significant byte of a short value from another odd position within said set into said first register, and initializing a eighth register with said least significant byte of a short from said even position in said sixth register; transferring said least significant byte of said short value from said another odd position within said set from said first register to said second register, loading a most significant byte of said short value from said another odd position within said set into said first register, and initializing a ninth register with said most significant byte of a short from said even position in said seventh register; transferring said most significant byte of said short value from said another odd position within said set from said first register to said third register, and loading a least significant byte of a short value from another even position within said set into said first register; transferring said least significant byte of said short value from said another even position within said set from said first register to said sixth register, and loading a most significant byte of said short value from said another even position within said set into said first register; and transferring said most significant byte of said short value from said another even position within said set from said first register to said seventh register.
29 The method of claim 28 wherein said determining an odd extreme from said odd numbered set comprises comparing said least significant byte of said short value from said odd position within said set to said least significant byte of said short value from said another odd position within said set and comparing said most significant byte of said short value from said odd position within said set to said most significant byte of said short value from said another odd position within said set.
30. The method of claim 28 wherein said determining an even extreme from said even numbered set comprises comparing said least significant byte of said short value from said even position within said set to said least significant byte of said short value from said another

even position within said set and comparing said most significant byte of said short value from said even position within said set to said most significant byte of said short value from: said another even position within said set.
31. A memory device carrying a set of instructions which, when executed, perform a method comprising: separating said set of values into an odd numbered set and an even numbered set; determining an odd extreme from said odd numbered set; determining an even extreme from said even numbered set; and determining said local extreme from said odd extreme and said even extreme.