GB2393272A - Controlling performance counters within a data processing system - Google Patents

Abstract

Performance counters 18, 20, 22 are provided within a data processing system 2 to count the occurrence of predetermined events during processing operation, trigger circuits 14, 16 provided within a breakpoint/watchpoint unit 6 and a tracing unit 8 are in the described example reused to also trigger the starting and stopping of the performance counters 18, 20, 22. Registers 26, 28, 30 determine how the counters respond to the trigger circuits and control register 24 determines what events the counters monitor.

Description

/ CONTROLLING PERFORMANCE COUNTERS WITHIN A DATA

PROCESSING SYSTEM

This invention relates to data processing systems. More particularly, this 5 invention relates to the control of performance counters within data processing systems. It is known within many processors, such as the Intel xB6, the Intel IA-64, the StarCore, the Alpha and the PowerPC, to provide performance counters. These 0 performance counters enable events of different types occurring within the processor during operation to be counted. The infommation provided by such performance counters is typically used during development and debugging of hardware and software, but might also be used at run-time.

5 Using performance counters the average behaviour of the system over a certain number of processing cycles or instructions can be determined. Typically the larger the portion of the program being monitored, the more coarse "rained the results become. It is often desirable to monitor the performance of specific parts of a program, for example particular performance critical software routines. In these 20 circumstances it is desirable to restrict the perfommance counting operation to only those parts of a program under consideration.

Known techniques for restricting performance counting to specific parts of a program include placing breakpoints at the start and end of the program code to be 2s profiled. When the first breakpoint is hit, the processor core enters a debug state. The debugger then enables the perfommance counters and starts the program running again.

When the second breakpoint is hit, the processor core again enters the debug state and the debugger disables the performance counters.

30 A problem with this approach is that starting and stopping of the nommal operation of the processor core is undesirable in many systems because whilst the processor core is stopped the program is unable to process data or handle interrupts.

This is especially the case when the programs concerned are perfomming real-time or hardware controlled tasks. In such circumstances, the interruption of the normal

! processing operation by the entry into and out of the debug state to switch on and off the performance counters distorts the real operation of the system to such an extent that normal operation, e.g. interrupt response, cannot be maintained.

5 Another known approach is to place breakpoints at the start and end of the code to be profiled and use a target resident monitor program, such as RealMonitor provided by ARM Limited, to enable and disable the performance counters when the breakpoints are hit. The target resident monitor program does not need to cause the processor core to enter debug state when the breakpoints are hit and accordingly can lo allow critical interrupt handlers to continue to be serviced throughout.

However, a problem with target resident monitors is that they usually require i integration with the user program before they can be properly used. They also consume valuable system resources, such as RAM and CPU time and are likely to 5 cause additional performance count events which distort the performance monitoring being performed.

A further approach is to "instrument" the program when it is compiled, either manually or automatically, to explicitly enable/disable the performance counters at the 20 particular desired points. This approach has the disadvantage that the program must be rebuilt each time the conditions are changed. Also, the instrumented image is not the same as the one the user is likely to use in their finished product and thus may exhibit different performance characteristics in a manner that compromises the performance count data which is obtained. Furthermore, access to the performance 25 counter registers is usually a privileged mode operation which may not be possible for the user program.

The present invention seeks to provide improved granularity of performance counting operation whilst avoiding the problems of the above described techniques.

Viewed from one aspect the present invention provides apparatus for processing data, said apparatus comprising:

! at least one performance counter operable when activated to count occurrences of a predetermined counted event during data processing operation of said apparatus; and at least one trigger circuit responsive to detection of a programmable condition s during data processing operation of said apparatus to control activation of said at least one performance counter.

The present technique provides trigger circuits associated with the performance counters. These trigger circuits may be programmed with user specified lo trigger conditions which can then control activation of the performance counters.

Thus, a user may set up the programmable conditions to activate the performance counters only during a specific part of a program or when other specified conditions prevail. 5 It will be appreciated that the type of event which may be counted could take a wide variety of forms. Examples of preferred types of event that may be counted include a cache miss, a processing pipeline stall, a translation lookaside buffer miss, a branch misprediction, a processing cycle, an instruction being executed, a cache access, a cache writeback, a software change of the program counter value, an 20 external memory request, a load store unit stall and the write buffer being emptied.

The type of event which a particular performance program counter is set to count may be user specified using a control value written into a counted event control register. Whilst the programmable condition which is detected by the trigger circuit could take a variety of forms, preferred embodiments of the invention trigger the performance counter based upon one, or a combination of, execution of a program instruction having an instruction address matching a programmable condition, a data 30 access to a memory address matching a programmable condition and a currently active program thread matching a programmable condition.

( The programmable conditions are conveniently held within user programmable registers. They may also advantageously be associated with mask registers that are used to qualify the programmable conditions.

s Whilst it would be possible to provide dedicated trigger circuits for controlling the performance counters, it is desirable to reduce the overhead associated with this operation by reusing trigger circuits that are associated with one or more of debug circuits or trace circuits. It is known to provide trigger circuits in association with debug circuits and trace circuits and rather than dedicate further circuit resources to lo trigger circuits for controlling the performance counters, the trigger circuits associated with existing other elements within the system can be reused.

When trigger circuits are reused as discussed above, preferred embodiments are such that a user programmable counter triggering bit is associated with each of the IS triggering circuits to control whether or not that triggering circuit controls activation of an associated performance counter or performs its normal role of controlling operation of a debug or trace system.

The flexibility of the system may be improved in embodiments in which a 20 trigger control value is associated with each performance counter to control how the performance counter responds to detection of the programmable condition by its associated trigger circuit. Examples of preferred different ways in which the performance counter may respond depending upon the trigger control value are to ignore the trigger signal, to start counting when the trigger signal indicates detection, 25 to stop counting when the trigger signal indicates non-detection, and to start counting when the trigger signal indicates detection and to stop counting when the trigger signal indicates non-detection.

Whilst it would be possible to provide a system with only a single 30 performance counter and a single trigger circuit, in order to get improved analytical information, preferred embodiments provide a plurality of performance counters, and preferably two performance counters for counting different types of events, and one performance counter dedicated to processing cycles, as well as a plurality of trigger

( circuits such that a variety of different trigger conditions may be simultaneously in place. It will be appreciated that when a plurality of trigger circuits are provided, s then there may be a conflict between one trigger condition and another. In such circumstances, if one trigger condition indicates that counting should be started and another indicates that counting should be stopped, then the system defaults to starting counting. It is considered better to capture information in such circumstances rather than to not capture information.

Viewed from another aspect the invention provides a method of controlling activation of at least one performance counter operable when activated to count occurrences of a predetermined counted event during data processing operation of an apparatus for processing data, said method comprising the step of: 5 detecting with at least one trigger circuit a programmable condition during data processing operation of said apparatus; and controlling activation of said at least one performance counter in dependence upon said detection.

20 It will be appreciated that performance counters of the type discussed above are typically used in conjunction with debugging systems. Debugging systems typically take the form of debugging software controlling a general purpose computer that is linked to the data processing system being monitored. In such circumstances, the computer program should be capable of controlling the performance counters in 25 accordance with the above described techniques.

Accordingly, a further aspect of the invention provides a computer program product for controlling a computer to configure performance counter operation within an apparatus for processing data, said apparatus including at least one performance 30 counter operable when activated to count occurrences of a predetermined counted event during data processing operation of said apparatus, said computer program product comprising: configuration code operable to program at least one programmable condition to control a trigger circuit such that said trigger circuit is responsive to detection of

( said programmable condition during data processing operation of said apparatus to control activation of said at least one performance counter.

Embodiments of the invention will now be described, by way of example only, s with reference to the accompanying drawings in which: Figure I schematically illustrates an integrated circuit including various debug, tracing and performance counting elements; lo Figure 2 schematically illustrates the relationship between triggering circuits and performance counters in accordance with one example of the present technique; Figure 3 schematically illustrates a trigger control register associated with a performance counter and how this may be used to control the response of the is associated performance counter to a trigger signal; Figure 4 is a flow diagram schematically illustrating the control of the activation of a performance counter in dependence upon a trigger control value; and 20 Figure 5 is a diagram schematically illustrating the architecture of a general purpose computer of a type which may be used to control the debugging, trace and performance counter operations upon a separate data processing apparatus under development or test.

25 Figure I shows an integrated circuit 2 including a processor core 4, a breakpoint/watchpoint unit 6, a trace unit 8, a performance counter unit 10 and a JTAG unit 12. It will be appreciated that the integrated circuit 2 will typically contain many further circuit elements, such as caches, processing pipelines within the processor core 4, translation lookaside buffers, branch prediction units, external 30 memory interfaces, load store units and write buffers. For the sake of clarity, such additional elements have not been illustrated in Figure 1.

The breakpoint/watchpoint unit 6 and the trace unit 8 are principally configured and operate in accordance with the standard form of such units, such as

( those provided by ARM Limited. The standard operation of the breakpoint/watchpoint unit 6 and the tracing unit 8 will not be described further herein other than that breakpoint/watchpoint unit 6 provides the ability to match upon a programmable context ID (e.g. a thread or process ID). The JTAG unit 12 is used to s program the breakpoint/watchpoint unit 6 and the tracing unit 8 via a serial debug interface. In particular, breakpoint values, watchpoint values and trigger values are loaded into triggering circuits 14, 16 via the JTAG unit 12. Further control registers associated with the triggering circuits 14, 16 are also loaded via the JTAG unit 12.

lo In this example embodiment, the performance counter unit 10 is provided in the form of a coprocessor (CP) to the processor core 4 (this coprocessor may also provide additional unrelated functionality). Accordingly, configuration registers within the performance counter unit 10 may be accessed and counted values read from the performance counter unit 10 via coprocessor instructions executed upon the IS processor core, possibly having been forced into the execution pipeline of the processor core via the other debug mechanisms present on the integrated circuit 2.

Figure 2 schematically illustrates the relationship between the triggering circuits 14, 16 and performance counters 18, 20, 22 within the performance counter JO unit 10. The breakpoint/watchpoint unit 6 includes sixteen user programmable condition registers for storing programmable condition values as well as a programmable mask value which is used to qualify the programmable condition. As an example, the mask value may specify that only the high order bits of an address value need to be matched in order to satisfy the trigger condition. In a similar way 2s user programmable condition registers are provided for watchpoint values. It will be appreciated that different numbers of breakpoint and watchpoint values may be supported depending upon the amount of circuit area that is dedicated to this purpose.

Associated with each of the programmable condition registers is a triggering 30 bit T which specifies whether or not, when the condition specified within its associated register is matched, the trigger signal should serve to trigger the performance counters or should serve its normal function of triggering breakpoint or watchpoint activity.

( l Further trigger circuits 16 are present within the tracing unit 8 and may also be reused in an analogous manner for controlling the performance counters 18, 20, 22.

A control register 24 is coupled to each of the performance counters 18, 20 5 and 22 and serves to control its operation. The control register 24 may be written to by a coprocessor instruction executed by the processor core 4. Similarly, the count values held by the performance counters 18, 20, 22 may be read and written by coprocessor instructions executed on the processor core 4.

lo The control register 24 serves to store a user programmable counted event value in respect of each of the general purpose counters 18 and 20 which specifies which type of event that counter is to sense. Examples of possible counted events are a cache miss, a processing pipeline stall, a translation lookaside buffer miss, a branch misprediction, a processing cycle, an instruction being executed, a cache access, a 5 cache writeback, a software change of a program counter value, an external memory request, a load store unit stall and a write buffer being emptied. Further types of event may be monitored if desired. The cycle counter 22 is dedicated to counting processing cycles as this is very often required in assessing the performance of a system and program. The control register 24 may also store other control values for 20 configuring the operation of the performance counters 18, 20, 22.

Associated with the performance counter 18 are three trigger control registers 26, 28, 30. Each of these trigger control registers stores a two-bit trigger control value associated with each predetermined condition that may be stored within a respective 25 trigger circuit of the breakpoint/watchpoint unit 6 and tracing unit 8. Thus, for what is illustrated as each line within the collection of sixteen triggering circuits of the breakpoint/watchpoint unit 6 and four triggering circuits within the tracing unit 8, a T-

bit specifies whether or not that triggering circuit will have any action upon the performance counters. If the T-bit specifies that the particular triggering circuit will 30 act upon the performance counters, then a corresponding 2-bit field within a trigger

control register 26, 28, 30 associated with each performance counter 18, 20, 22 will determine how that particular performance counter 18, 20, 22 responds to the detection of a predetermined condition by the particular triggering circuit. Each triggering circuit is coupled to all of the performance counters 18, 20, 22 in this

( particular example. Thus, a single trigger condition being met within one of the triggering circuits may start the performance counter 18 counting one type of event, the performance counter 20 counting a different type of event and the cycle counter 22 counting processing cycles. Alternatively, a single detected condition may start 5 one counter whilst stopping one or more other counters. It will be appreciated that the control arrangement illustrated in Figure 2 provides considerable flexibility in how the performance counters 18, 20, 22 may be used.

The 2-bit fields within the trigger control registers can specify values

lo indicating that a trigger signal should be ignored, used to start counting, used to stop counting or used to start counting when found and stop counting when not found as will be described later.

Given the presence of multiple triggering circuits, it is possible that one 5 triggering circuit may indicate that a particular performance counter 18, 20, 22 should start counting whilst another triggering circuit indicates that the performance counter 18, 20, 22 should stop counting. In such circumstances, the indication to start counting overrides the indication to stop counting and the performance counter 18, 20, 22 concerned will start counting. It will be appreciated that other behaviour such as 20 stopping counting, may occur - what is important is that some eontrolled/defined behaviour results.

In the example system illustrated in Figure 2, the breakpoint triggering circuits may be used to control the performance counters in dependence upon the execution of 25 an instruction with an instruction address matching a predetermined condition. The watchpoint triggering circuits may be used to control performance counters in dependence upon memory accesses to a memory address matching predetermined conditions. The breakpoint triggers and watchpoint triggers may also be used to detect when a particular program thread is being executed by being responsive to a 30 context ID and the performance counters can be controlled dependent upon whether or not a particular thread is or is not executing. The conditions specified within the trigger circuits may also be chained together to provide combinations of conditions, such as a particular instruction being executed whilst in a particular context and making an access to a particular data value.

( The triggering circuits within the tracing unit 8 may operate in a similar way to those within the breakpoint/watchpoint unit G. They may also provide different or additional possibilities for conditions that may be detected in order to control the 5 tracing and also the performance counting operation of the integrated circuit 2.

Figure 3 schematically illustrates one of the trigger control registers 26, 28 in more detail. In this example the trigger control register corresponds to eight instruction breakpoint registers. Associated with each instruction breakpoint lo triggering circuit is a 2-bit field bO;bl. Depending upon the value of this 2-bit field an

action is triggered within the associated performance counter 18, 20, 22 as specified within the table shown in Figure 3. More particularly, a transition of the triggering signal from low to high indicating the start of detection of a trigger condition starts the counter if the 2-bit value is "01". A value of "10" will stop performance counting 5 when the trigger signal indicates that the associated condition has stopped being detected. A value of "l 1" will start counting when the trigger condition indicates the start of detection and stop counting when the trigger signal indicates the stopping of detection. A value of "00" indicates that the trigger signal will be ignored even if the T-bit is set for the trigger circuit. It can be the case that the T-bit is set indicating that 20 one of the counters is responsive to that trigger circuit, but the other of the counters which are not responsive to that triggering circuit will have a value of"OO" set in their trigger control register to indicate that they should ignore the trigger signal from that triggering circuit.

25 Figure 4 is a flow diagram schematically illustrating the control discussed in relation to Figure 3. At step 32, the system waits for any watchpoint, breakpoint or other trigger derived trigger signal to change its value. When such a signal changes its value, processing proceeds to step 34 at which the corresponding T-bit is read. If the T-bit indicates that performance counters are not controlled in dependence upon 30 that trigger condition, then processing returns to step 36. If performance counters are controlled in dependence upon that trigger condition, then processing proceeds to step 36 at which reference is made to the 2-bit field for a particular performance counter.

It will be appreciated that the action illustrated in Figure 4 is separately conducted in parallel on behalf of each of the performance counters 18, 20, 22.

( At step 38, if a value of "OO" is detected, then processing returns to step 32.

If at step 40 a value of "01" is detected and the trigger signal has gone from s indicating non-detection of the trigger condition to detection of the trigger condition, then processing proceeds to step 41 at which the associated performance counter is started before processing is returned to step 32. This assumes there are not contradictor triggers occurring resolution of these effectively occurring in parallel under hardware control.

If the conditions at step 40 were not met, the processing proceeds to step 42 at which a determination is made as to whether or not the 2-bit value is "10" and the trigger signal has transitioned from a level indicating that the trigger condition was detected to one indicating that it was not detected. If both of these conditions are met, then processing proceeds to step 44 at which the associated performance counter is stopped before processing is returned to step 32. If the condition specified in step 42 are not met, the processing proceeds to step 46.

If step 46 determines that the 2-bit value is "11" then processing proceeds to 20 step 48. Alternatively, the processing proceeds to step 32. At step 48, if the trigger signal has indicated that the trigger condition has changed from not being detected, to being detected, then processing proceeds to step 40 where the counter is started, otherwise processing proceeds to step 44 where the counter is stopped. This assumes there are not contradictor triggers occurring - resolution of these effectively occurring 2s in parallel under hardware control.

It will be appreciated that the flow diagram of Figure 4 is highly schematic and in practice the determinations illustrated will be performed by hardware logic circuits rather than sequential processing. In particular, it will be noted that bit bO can 30 be used to indicate whether or not the counter should stop if the condition trigger stops being detected and the bit bl can be used to indicate whether or not the counter should start if the trigger condition starts being detected. Thus, the hardware logic is straight forward.

( an. 'T> It will be appreciated that the various predetermined conditions which are detected to control the performance counters as well as the various control register values used to control the action of the performance counters and the action of the triggering circuits need to be set up under user control. This is normally performed by s a debugger system, such as a general purpose computer executing a debugging program which controls a hardware interface which interfaces with the processing apparatus containing the integrated circuit 2. The interface circuit may communicate via the serial JTAG interface into the various debugging and performance monitoring circuit elements. The debugging software can be used to set up the control values and 0 the predetermined conditions as well as recover the diagnostic information once it has been captured. One aspect of the invention can be considered to be the software which controls a general purpose computer which in turn controls the setting up of the trigger conditions and the like for controlling the performance counters.

5 Figure 5 schematically illustrates a general purpose computer 200 of the type that may be used to implement the above described techniques. The general purpose computer 200 includes a central processing unit 202, a random access memory 204, a read only memory 206, a network interface card 208, a hard disk drive 210, a display driver 212 and monitor 214 and a user input/output circuit 216 with a keyboard 218 20 and mouse 220 all connected via a common bus 222. In operation the central processing unit 202 will execute computer program instructions that may be stored in one or more of the random access memory 204, the read only memory 206 and the hard disk drive 210 or dynamically downloaded via the network interface card 208.

The results of the processing performed may be displayed to a user via the display Is driver 212 and the monitor 214. User inputs for controlling the operation of the general purpose computer 200 may be received via the user input output circuit 216 from the keyboard 218 or the mouse 220. It will be appreciated that the computer program could be written in a variety of different computer languages. The computer program may be stored and distributed on a recording medium or dynamically 30 downloaded to the general purpose computer 200. When operating under control of an appropriate computer program, the general purpose computer 200 can perform the above described techniques and can be considered to form an apparatus for performing the above described technique. The architecture of the general purpose computer 200 could vary considerably and Figure 5 is only one example.

Claims (1)

1. Apparatus for processing data, said apparatus comprising: at least one performance counter operable when activated to count occurrences 5 of a predetermined counted event during data processing operation of said apparatus; and at least one trigger circuit responsive to detection of a programmable condition during data processing operation of said apparatus to control activation of said at least one performance counter.

2. Apparatus as claimed in claim 1, wherein said predetermined counted event is one of: a cache miss; a processing pipeline stall; 5 a translation lookaside buffer miss; a branch misprediction; a processing cycle; an instruction being executed; a cache access; 20 a cache writeback; a software change of a program counter value; an external memory request; a load store unit stall; and a write buffer being emptied.

3. Apparatus as claimed in claim 2, wherein which type of predetermined counted event is selected for counting is controlled by a user programmable counted event value stored within a counted event control register coupled to said at least one performance counter.

4. Apparatus as claimed in any one of claims 1, 2 and 3, wherein said programmable condition is at least one of: execution of a program instruction having an instruction address matching a programmable condition;

( L, a data access to a memory address matching a programmable condition; and matching a context ID to a programmable condition.

5. Apparatus as claimed in any one of the preceding claims, wherein said 5 programmable condition is specified by a condition value held within a user programmable condition register.

6. Apparatus as claimed in claim 5, wherein said programmable condition is also specified by a mask value held within a user programmable mask register, said mask lo value being used to qualify said condition value.

7. Apparatus in any one of the preceding claims, wherein said at least one trigger circuit is shared with one or more of: debug circuits operable perform software debugging operations; and 5 trace circuits operable to perform data processing tracing operations.

8. Apparatus as claimed in claim 7, wherein a user programmable counter triggering bit is associated with each of said at least one trigger circuit to control whether or not said triggering circuit controls activation of an associated performance 20 counter. 9. Apparatus as claimed in any one of the preceding claims, wherein for each of said at least one performance counter a trigger control value is stored within a trigger control register coupled to said performance counter to control how said performance 25 counter responses to a trigger signal associated with said performance counter generated by said at least one trigger circuit.

10. Apparatus as claimed in claim 9, wherein said trigger control value specifies that said performance counter should one of: 30 ignore said trigger signal; start counting when said trigger signal indicates detection of a predetermined condition; stop counting when said trigger signal indicates non-detection of a predetermined condition; and

1. start counting when said trigger signal indicates detection of a predetermined condition and stop counting when said trigger signal indicates non-detection of said predetermined condition.

5 11. Apparatus as claimed in any one of the preceding claims, comprising a plurality of performance counters.

12. Apparatus as claimed in claim 11, comprising two performance counters programmable to count different types of event and one performance counter operable lo to count processing cycles.

13. Apparatus as claimed in any one of the preceding claims, comprising a I plurality of trigger circuits, at least one of said performance counters being coupled to a plurality of trigger circuits.

14. Apparatus as claimed in claim 13, wherein if one trigger circuit indicates activation of said performance counter and another trigger circuit indicates de activation of said performance counter, then said performance counter is activated.

20 15. A method of controlling activation of at least one performance counter operable when activated to count occurrences of a predetermined counted event during data processing operation of an apparatus for processing data, said method comprising the step of: detecting with at least one trigger circuit a programmable condition during 25 data processing operation of said apparatus; and controlling activation of said at least one performance counter in dependence upon said detection.

16. A method as claimed in claim 15, wherein said predetermined counted event is 30 one of: a cache miss; a processing pipeline stall; a translation lookaside buffer miss; a branch misprediction;

a processing cycle; an instruction being executed; a cache access; a cache write-back; s a software change of a program counter value; an external memory request; a load store unit stall; and a write buffer being emptied.

lo 17. A method as claimed in claim 16, wherein which type of predetermined counted event is selected for counting is controlled by a user programmable counted event value stored within a counted event control register coupled to said at least one performance counter.

5 18. A method as claimed in any one of claims 15, 16 and 17, wherein said programmable condition is at least one of: execution of a program instruction having an instruction address matching a programmable condition; a data access to a memory address matching a programmable condition; and 20 matching a context ID to a programmable condition.

19. A method as claimed in any one claims 15 to 18, wherein said programmable condition is specified by a condition value held within a user programmable condition register. 20. A method as claimed in claim 19, wherein said programmable condition is also specified by a mask value held within a user programmable mask register, said mask value being used to qualify said condition value.

30 21. A method in any one of claims 15 to 20, wherein said at least one trigger circuit is shared with one or more of: debug circuits operable perform software debugging operations; and trace circuits operable to perform data processing tracing operations.

( 22. A method as claimed in claim 21, wherein a user programmable counter triggering bit is associated with each of said at least one trigger circuit to control whether or not said triggering circuit controls activation of an associated performance counter. 23. A method as claimed in any one of claims 15 to 22, wherein for each of said at least one performance counter a trigger control value is stored within a trigger control register coupled to said performance counter to control how said performance counter responds to a trigger signal associated with said performance counter generated by lo said at least one trigger circuit.

24. A method as claimed in claim 23, wherein said trigger control value specifies that said performance counter should one of: ignore said trigger signal; 5 start counting when said trigger signal indicates detection of a predetermined condition; stop counting when said trigger signal indicates non-detection of a predetermined condition; and start counting when said trigger signal indicates detection of a predetermined 20 condition and stop counting when said trigger signal indicates non- detection of said predetermined condition.

25. A method as claimed in any one of claims IS to 24, wherein said apparatus comprises a plurality of performance counters.

26. A method as claimed in claim 25, wherein said apparatus comprises two performance counters programmable to count di fferent types of event and one performance counter operable to count processing cycles.

30 27. A method as claimed in any one of claims 15 to 26, wherein said apparatus comprises a plurality of trigger circuits, at least one of said performance counters being coupled to a plurality of trigger circuits.

( 28. A method as claimed in claim 27, wherein if one trigger circuit indicates activation of said performance counter and another trigger circuit indicates de-

activation of said performance counter, then said performance counter is activated.

5 29. A computer program product for controlling a computer to configure performance counter operation within an apparatus for processing data, said apparatus including at least one performance counter operable when activated to count occurrences of a predetermined counted event during data processing operation of said apparatus, said computer program product comprising: lo configuration code operable to program at least one programmable condition to control a trigger circuit such that said trigger circuit is responsive to detection of said programmable condition during data processing operation of said apparatus to control activation of said at least one performance counter.

5 30. A computer program product as claimed in claim 29, wherein said predetermined counted event is one of: a cache miss; a processing pipeline stall; a translation lookaside buffer miss; 20 a branch misprediction; a processing cycle; an instruction being executed; a cache access; a cache write-back; 25 a software change of a program counter value; an external memory request; a load store unit stall; and a write buffer being emptied.

30 31. A computer program product as claimed in claim 30, wherein which type of predetermined counted event is selected for counting is controlled by a user programmable counted event value stored within a counted event control register coupled to said at least one performance counter.

( 32. A computer program product as claimed in any one of claims 29, 30 and 31, wherein said programmable condition is at least one of: execution of a program instruction having an instruction address matching a programmable condition; and 5 a data access to a memory address matching a programmable condition; and matching a context ID to a programmable condition.

33. A computer program product as claimed in any one claims 29 to 32, wherein said programmable condition is specified by a condition value held within a user lo programmable condition register.

34. A computer program product as claimed in claim 33, wherein said programmable condition is also speci fled by a mask value held within a user programmable mask register, said mask value being used to qualify said condition s value. 35. A computer program product in any one of claims 29 to 34, wherein said at least one trigger circuit is shared with one or more of: debug circuits operable perform software debugging operations; and 20 trace circuits operable to perform data processing tracing operations.

36. A computer program product as claimed in claim 35, wherein a user programmable counter triggering bit is associated with each of said at least one trigger circuit to control whether or not said triggering circuit controls activation of an 25 associated performance counter.

37. A computer program product as claimed in any one of claims 29 to 36, wherein for each of said at least one performance counter a trigger control value is stored within a trigger control register coupled to said performance counter to control 30 how said performance counter responds to a trigger signal associated with said performance counter generated by said at least one trigger circuit.

38. A computer program product as claimed in claim 37, wherein said trigger control value specifies that said performance counter should one of:

( ignore said trigger signal; start counting when said trigger signal indicates detection of a predetermined condition; stop counting when said trigger signal indicates non-detection of a s predetermined condition; and start counting when said trigger signal indicates detection of a predetermined condition and stop counting when said trigger signal indicates non-detection of said predetermined condition.

lo 39. A computer program product as claimed in any one of claims 29 to 38, wherein said apparatus comprises a plurality of performance counters.

40. A computer program product as claimed in claim 39, wherein said apparatus comprises two performance counters programmable to count different types of event 5 and one performance counter operable to count processing cycles.

41. A computer program product as claimed in any one of claims 29 to 40, wherein said apparatus comprise a plurality of trigger circuits, at least one of said performance counters being coupled to a plurality of trigger circuits.

42. A computer program product as claimed in claim 41, wherein if one trigger circuit indicates activation of said performance counter and another trigger circuit indicates de-activation of said performance counter, then said performance counter is activated. 43. Apparatus for processing data substantially as hereinbefore described with reference to the accompanying drawings.

44. A method of controlling activation of at least one performance counter 30 substantially as hereinbefore described with reference to the accompanying drawings.

45. A computer program product substantially as hereinbefore described with reference to the accompanying drawings.