GB2386485A - Modulo addressing apparatus and methods - Google Patents

Abstract

The invention generally relates to improved digital filter implementations, particularly for mobile communications systems. An address generation unit generates addresses for a plurality of circular buffers of different lengths, each said circular buffer comprising a block of memory elements 608, 610, 612, 614. The address generation unit comprises a counter 630 to provide a count, an address pointer 618 for pointing to said memory elements and a pointer controller to control said address pointer to point to each said memory block in turn, at a position dependent upon said count. A digital filter with a plurality of data delays has addresses generated by the address generation unit.

Description

MODULO ADDRESSING APPARATUS AND METHODS

This invention generally relates to digital signal processing apparatus and methods suitable for digital mobile communications systems such as third generation (3G) mobile communications systems. More particularly the invention relates to improved techniques for implementing digital filters.

Third generation mobile phone networks use CDMA (Code Division Multiple Access) spread spectrum signals for communicating across the radio interface between a mobile station and a base station. These 3G networks, (and also so-called 2.5G networks), are encompassed by the International Mobile Telecommunications IMT-2000 standard (www.ituint, hereby incorporated by reference). Third generation technology uses CDMA (Code Division Multiple Access) and the IMT-2000 standard contemplates three main modes of operation, W-CDMA (Wide band CDMA) direct spread FDD (Frequency Division Duplex) in Europe and Japan, CDMA-2000 multicarrier FDD for the USA, and TD-CDMA (Time Division Duplex CDMA) and TD-SCDMA (Time Division Synchronous CDMA) for China.

Collectively the radio access portion of a 3G network is referred to as UTRAN (Universal Terrestrial Radio Access Network) and a network comprising UTRAN access networks is known as a UMTS (Universal Mobile Telecommunications System) network. The UMTS system is the subject of standards produced by the Third Generation Partnership Project (3GPP, 3GPP2), technical specifications for which can

be found at www.3epp.org. These standards include Technical Specifications 23.101,

which describes a general UMTS architecture, and 25.101 which describes user and radio transmission and reception (FDD) versions 4.0.0 and 3.2.2 respectively of which are hereby incorporated by reference.

Figure 1 shows a generic structure of a third generation digital mobile phone system at 10. In Figure 1 a radio mast 12 is coupled to a base station 14 which in turn is

controlled by a base station controller 16. A mobile communications device 18 is shown in two-way communication with base station 14 across a radio or air interface 2O, known as a Um interface in GSM (Global Systems for Mobile Communications) networks and GPRS (General Packet Radio Service) networks and a Uu interface in CDMA2000 and W-CDMA networks. Typically at any one time a plurality of mobile devices 18 are attached to a given base station, which includes a plurality of radio transceivers to serve these devices.

Base station controller 16 is coupled, together with a plurality of other base station controllers (not shown) to a mobile switching centre (MSC) 22. A plurality of such MSCs are in turn coupled to a gateway MSC (GMSC) 24 which connects the mobile phone network to the public switched telephone network (PSTN) 26. A home location register (HLR) 28 and a visitor location register (VLR) 30 manage call routing and roaming and other systems (not shown) manage authentication, billing. An operation and maintenance centre (OMC) 29 collects the statistics from network infrastructure elements such as base stations and switches to provide network operators with a high level view of the network's performance. The OMC can be used, for example, to determine how much of the available capacity of the network or parts of the network is being used at different times of day.

The above described network infrastructure essentially manages circuit switched voice connections between a mobile communications device 18 and other mobile devices and/or PSTN 26. So-called 2.5G networks such as GPRS, and 3G networks, add packet data services to the circuit switched voice services. In broad terms a packet control unit (PCU) 32 is added to the base station controller 16 and this is connected to a packet data network such as Internet 38 by means of a hierarchical series of switches. In a GSM-

based network these comprise a serving GPRS support node (SGSN) 34 and a gateway GPRS support node (GGSM) 36. It will be appreciated that both in the system of Figure 1 and in the system described later the functionalities of elements within the network may reside on a single physical node or on separate physical nodes of the system.

Communications between the mobile device 18 and the network infrastructure generally include both data and control signals. The data may comprise digitally encoded voice data or a data modem may be employed to transparently communicate data to and from the mobile device. In a GSMtype network text and other low-bandwidth data may also be sent using the GSM Short Message Service (SMS).

In a 2.5G or 3G network mobile device 18 may provide more than a simple voice connection to another phone. For example mobile device 18 may additionally or alternatively provide access to video and/or multimedia data services, web browsing, e-

mail and other data services. Logically mobile device 18 may be considered to comprise a mobile terminal (incorporating a subscriber identity module (SIM) card) with a serial connection to terminal equipment such as a data processor or personal computer. Generally once the mobile device has attached to the network it is "always on" and user data can be transferred transparently between the device and an external data network, for example by means of standard AT commands at the mobile terminal-

terminal equipment interface. Where a conventional mobile phone is employed for mobile device 18 a terminal adapter, such as a GSM data card, may be needed.

In a CDMA spread spectrum communication system a baseband signal is spread by mixing it with a pseudorandom spreading sequence of a much higher bit rate (referred to as the chip rate) before modulating the rf carrier. At the receiver the baseband signal is recovered by feeding the received signal and the pseudorandom spreading sequence into a correlator and allowing one to slip past the other until a lock is obtained. Once code lock has been obtained, it is maintained by means of a code tracking loop such as an early-late tracking loop which detects when the input signal is early or late with respect to the spreading sequence and compensates for the change. Alternatively a matched filter may be employed for Respreading and synchronization.

Such a system is described as code division multiplexed as the baseband signal can only be recovered if the initial pseudorandom spreading sequence is known. A spread spectrum communication system allows many transmitters with different spreading sequences all to use the same part of the rf spectrum, a receiver.'tuning" to the desired signal by selecting the appropriate spreading sequence.

Figures 2a and 2b show, respectively, an exemplary front end 200 and a decoder 250 for a typical spread spectrum receiver. A receiver antenna 202 is connected to an input amplifier 204, which has a second input from an IF oscillator 208 to mix the input of rf signal down to IF. The output of mixer 206 is fed to an IF band pass filter 210 and thence to an AGC (Automatic Gain Control) stage 212. The output of AGC stage 212 provides an input to two mixers 252, 254 to be mixed with quadrature signals from an oscillator 258 and a splitter 256. This generates quadrature I and Q signals 260, 262 which are digitised by analogue to digital converters 264, which also output a control signal on line 266 to control AGC stage 212 to optimise signal quantisation.

Digitised I and Q signals 268, 270 from ADCs 264 are fed to Nyquist filters 272, 274 and thence to matched filters 276, 278, which are configured to provide a maximum output when a signal with the desired pseudorandom spreading sequence is received.

The matched filter outputs feed bit synchronization circuitry 280 which provides an error signal 286 to a delay locked loop 288 which generates sample clocks 290 to ADCs 266. Circuitry 280 also provides a second output 282 to a demodulator 284 for demodulating received data. Typically, as shown in Figure 2, the rf signal is digitised at IF although it may be digitised at other points, for example after input amplifier 204.

In a 3G mobile phone system the baseband data is spread using a spreading or channelisation code using an Orthogonal Variable Spreading Factor (OVSF) technique.

The OVSF codes allow the spreading factor to be changed whilst maintaining orthogonality between codes of different lengths. To increase the number of simultaneous users of the system the data is further spread by a scrambling code such as a Gold code. The scrambling code does not change the signal bandwidth but allows signals to or from different users to be distinguished from one another, again, because the spreading codes are substantially mutually orthogonal. The scrambling is used on top of the channelisation spreading, that is a signal at the chip rate following OVSF spreading is multiplied by the scrambling code to produce a scrambled code at the same chip rate. The chip rate is thus determined by the channelisation code and, in this system, is unaffected by the subsequent scrambling. Thus the symbol rate for a given chip rate is likewise unaffected by the scrambling.

a i 5 Different spreading factors and scrambling code links are generally employed for the down link from the base station to the mobile station and for the up link from the mobile station to the base station. Typically the channelisation codes have a length of between 4 chips and 256 chips or, equivalently, a spreading factor of between 4 and 256 (although other spreading factors may be employed). The up link and down link radio (data channel) frames generally last lOms, corresponding to a scrambling code length of 38400 chips although shorter frames, for example of 256 chips, are sometimes employed on the up link. A typical chip rate is 3.84 M chips/see (Mcps), which determines the maximum bit rate for a channel for example with a spreading factor of 16, that is 16 chips per symbol, this gives a data rate of 240 Kbps. It will be recognised that the foregoing figures are provided merely for the purposes of illustration. Where higher bit rate communications with a mobile station are required more than one such channel may be employed to create a so-called multicode transmission. In a multicode transmission a plurality of data channels are used, effectively in parallel, to increase the overall rate of data transmission to or from a mobile station. Generally the multicode data channels have the same scrambling code but different channelisation codes, albeit preferably with the same spreading factor.

In a 3G mobile phone system there are generally a number of different channels some dedicated to particular users and some common to groups of users such as all the users within a given cell or sector. Traffic is carried on a Dedicated Physical Control Channel (DPCH), or on a plurality of such channels in the case of a multicode transmission, as described above. The common channels generally transport signalling and control information and may also be utilised for the physical layer of the system's radio link.

Thus a Common Pilot Channel (CPICH) is provided comprising an unmodulated code channel scrambled with a cell-specific scrambling code to allow channel estimation and equalisation at the mobile station receiver. Similarly a Sychnronisation Channel (SCM) is provided for use by the mobile station to locate network cells. A primary SCH channel is unmodulated and is transmitted using the same channelisation spreading sequence in each cell and does not employ a cell-specific scrambling code. A similar secondary SCH channel is also provided, but with a limited number of spreading sequences. Primary and Secondary Common Control Physical Channel (PCCPCH,

SCCPCH) having known channelisation and spreading codes are also provided to carry control information. The foregoing signalling channels (CPICH, SCH and CCPCH) must generally be decoded by all the mobile stations and thus the spreading codes (channelisation codes and where appropriate, scrambling code) will generally be known by the mobile station, for example because the known codes for a network have been stored in the user-end equipment. Here the references to channels are generally references to physical channels and one or more network transport channels may be mapped to such a physical channel. In the context of 3G mobile phone networks the mobile station or mobile device is often referred to as a terminal and in this specification no distinction is drawn between these general terms.

One advantage of spread spectrum systems is that they are relatively insensitive to multipath fading. Multipath fading arises when a signal from a transmitter to a receiver takes two or more different paths and hence two or more versions of the signals arrive at the receiver at different times and interfere with one another. This typically produces a comb-like frequency response and, when a wide band signal is received over a multipath channel, the multiple delays give the multiple components of the received signal the appearance of tines of a rake. The number and position of multipath channels generally changes over time, particularly when the transmitter or receiver is moving.

As the skilled person will understand; a correlator in a spread spectrum receiver will tend to lock onto one of the multipath components, normally the direct signal which is the strongest. However a plurality of correlators may be provided to allow the spread spectrum receiver to lock onto a corresponding plurality of separate multipath components of the received signal. Such a spread spectrum receiver is known as a rake receiver and the elements of the receiver comprising the correlators are often referred to as "fingers" of the rake receiver. The separate outputs from each finger of the rake receiver are combined to provide an improved signal to noise ratio (or bit error rate) generally either by weighting each output equally or by estimating weights which maximise the signal to noise ratio of the combined output. This latter technique is known as Maximal Ratio Combining (MRC).

Figure 3 shows the main components of a typical rake receiver 300. A bank of correlators 302 comprises, in this example, three correlators 302, 302 and 302 each of

which receives a CDMA signal from input 304. The correlators are known as the fingers of the rake; in the illustrated example the rake has three fingers. The CDMA signal may be at baseband or at IF (Intermediate Frequency). Each correlator locks to a separate multipath component which is delayed by at least one chip with respect to the other multipath components. More or fewer correlators can be provided according to a quality-cost/complexity trade off. The outputs of all the correlators go to a combiner 306 such as an MRC combiner, which adds the outputs in a weighted sum, generally giving greater weight to the stronger signals. The weighting may be determined based upon signal strength before or after correlation, according to conventional algorithms.

The combined signal is then fed to a discriminator 308 which makes a decision as to whether a bit is a 1 or a 0 and provides a baseband output. The discriminator may include additional filtering, integration or other processing. The rake receiver 300 may be implemented in either hardware or software or a mixture of both.

Referring now to Figure 4, this shows in more detail an example of W-CDMA rake receiver 400 according to the prior art. The receiver 400 has an antenna 402 to receive

the spread spectrum signal for the DPCH (Dedicated Physical Data Channel), PCCPCH, and CPICH channels. The signal received by antenna 402 is input to a down converter 404 which down converts the signal to either IF (Intermediate Frequency) or base band for despreading. Typically at this point the signal will be digitised by an analogue-to-

digital converter for processing in the digital domain by either dedicated or programmable digital signal processors. To preserve both magnitude and phase information the signal normally comprises I and Q channels although for simplicity these are not shown in Figure 4. In this receiver, and generally in the receiver's described below, the signal processing in either the analogue or the digital domain or in both domains may be employed. However since normally much of the processing is carried out digitally the functional element drawn as blocks in Figure 4 will generally be implemented by appropriate software or, where specialized integrated circuits are available for some of the functions, by appropriately programming registers in these integrated circuits to configure their architectural and/or functionality for performing the required functions.

Referring again to Figure 4, the receiver 400 comprises 3 rake fingers 406, 408 and 410 each having an output to rake combiner 412 which provides a combined demodulated signal output 414 for further processing in the mobile terminal. The main elements of each rake finger correspond and, for simplicity, only the elements of rake finger 406 are shown. A code tracker 416 is coupled to the input of rake finger 406 to track the spread spectrum codes for Respreading. Conventional means such as a snatched filter or an early-late tracking loop may be employed for code tracker 416 and since the DPCH, PCCPCH and CPICH channels are generally synchronized the code tracker 416 need only log on to one of these signals but normally CPICH because this generally has a relatively high signal level. The output of the code tracker 416 controls code generators for PCCPCH 418, CPICH 420, and DPCH 422 which generate spreading codes for cross-correlation with their corresponding channel signals to despread the spread spectrum signals. Thus three despreaders 424, 426, 428 are provided, each coupled to the rake finger input, and each receiving an output from one of the code generators 418 420, 422 to despread the appropriate signal (both channelisation and scrambling codes) .

As the skilled person would appreciate these despreaders will generally comprise a cross-correlator such as a multiplier and summer.

The CPICH pilot signal is unmodulated so that when it is despread the result is a signal with a magnitude and phase corresponding to the attenuation and phase shift of the multipath channel through which the CPICH signal locked onto by the finger of the rake receiver has been transmitted. This signal thus comprises a channel estimate for the CPICH channel, in particular for the multipath component of this channel the rake finger has despread. The estimate may be used without further processing but, preferably the estimate is averaged over time, over one or more symbol intervals, to reduce noise on the estimate and increase its accuracy. This function is performed by channel estimate 430. It will be appreciated although averaging over a long period will reduce the level of noise, this will also reduce the ability of the receiver to respond quickly to changing channel conditions such as are encountered when, for example, the receiver is operating in a terminal in a car on a motorway.

The channel estimate is conjugated to invert the phase and if necessary normalised so that zero attenuation corresponds to a magnitude of unity, and in this form the conjugated signal can simply be used to multiply another received signal to apply or compensate for the channel estimate. Thus multipliers 432 and 434 apply the channel estimate from channel estimate block 430 to the broadcast control channel PCCPCH and to the desired data channel DPCH respectively. The desired data channels are then combined by rake combiner 412 in any conventional fashion and the broadcast channel outputs from each finger, such as broadcast channel output 436 from rake finger 406, are also combined in a second rake combiner (not shown in Figure 4) to output a demodulated PCCPCH control channel signal.

To perform initial synchronization in a W-CDMA mobile telecommunications system a matched filter is used to identify the timing offset of a known synchronization sequence This matched filter can be efficiently implemented using a Golay correlator 500 as shown in Figure 5. The structure and operation of such a Golay correlator is described in more detail in 3GPP technical document Tdoc TSGR1#4(99)373 (TSGRAN WG1 Meeting #4 Yokohama Japan, 18-20 April 1999) and in particular in sections 2.0 to 2.3, which are hereby incorporated by reference.

The Golay correlator of Figure 5 provides an efficient matched filter for correlating to primary and secondary synchronization code words based upon Golay sequences and is sometimes called an Efficient Golay Correlator. The filter 500 comprises a plurality of delay lines 502a- 502h each with Dn memory elements to provide an n unit delay, typically an e-clock cycle delay. The correlator further comprises a plurality of adders 504 and subtracters 506 and provides an output signal on line 508. Such a Golay correlator may be implemented in either hardware or software.

As previously described an rf front end provides incoming data comprising I and Q samples, each generally comprising a plurality of bits. In one common configuration 6 bits are used for each of I and Q. to provide 12 bit wide (complex-valued) data samples.

These data samples are applied to an input 510 of Golay correlator 500. As these data traverse the filter the data becomes wider because of the effects of the addition and subtraction operations, as will be understood by those skilled in the art.

The delays in the Golay correlator are typically implemented using a circular buffer, and the majority of digital signal processors (DSPs) are provided with specially adapted addressing modes for controlling such buffers, known as modulo addressing modes.

Modulo n arithmetic operates with integers between 0 and n-1 and a modulo n operation on a number provides the remainder when the number is divided by n. Thus, for example, 10 (binary 1010) = 2 (binary 010) modulo 8 and 28 (binary 11100) = 12 (binary 1100) modulo 16. It will be appreciated that determining a value modulo a power of two is simply a question of masking off any unwanted bits. A counter arranged to count modulo n will count from 0 to n-1 and then wrap around to 0 again, and is thus suited to providing addresses for a circular buffer.

In a matched or lattice filter, such as an efficient Golay correlator, there is often a plurality of data delay units, such as delay units 502ah of Figure 5, each of which is best accessed using a modulo addressing scheme. If each delay unit is implemented as a circular buffer one modulo addressing address register is needed for each delay unit and, where the number of delay units is large, the number of required registers may exceed the number available. In this case it may be necessary to manually code the buffer control function rather than relying on modulo addressing functions built into the digital signal processor which, in turn, leads to significant computational inefficiencies.

A conventional DSP address generation unit comprises an index register, a modifier register and a length register. The index register provides a circular buffer memory element address which, after a data access operation, is adjusted by adding the contents of the modifier register modulo a buffer length stored in the length register. A variant of such an address generation unit in which there is a plurality of index registers is described in 'Minimization of data address computation overhead in DSP programs", Wess, B. & Gotschlich, M; Inst. fur Nachrichtentech. und Hochfrequenztech., Tech.

Univ. Wein, Austria; Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, 1998. Other background information can be

found in "Modulo address generators for DSPs", Prasad, M.K. & Kolagotia, R.K., Sony Personal Mobile Commun. of America, San Diego, CA. USA; Electronic Letters 20 Aug 1988, 34(17), pl653-1654 and in US 5,765,218 which describes an address

generating circuit for generating addresses separated by a prescribed step value in circular addressing.

These prior art modulo addressing schemes do not however help to reduce the large

number of modulo address registers required to implement a digital filter such as a lattice filter.

According to one aspect of the present invention there is therefore provided an address generation unit for generating addresses for a plurality of circular buffers of different lengths, each said circular buffer comprising a block of memory elements, the address generation unit comprising, a counter to provide a count, an address pointer for pointing to said memory elements, and a pointer controller to control said address pointer to point to each said memory block in turn, at a position dependent upon said count.

A single, common address pointer is used to provide addresses for a plurality of different modulo addressing ranges, and thus the number of address registers required may be significantly reduced. Preferably the counter is configured to count modulo a lowest common multiple of the circular buffer lengths and preferably, therefore, the circular buffers have lengths in powers of two. In this way the counter may provide a circular count up to the lowest common multiple of the individual modulo elements to facilitate addressing for a number of different modulo addressing ranges. Here "lowest common multiple" has its conventional meaning, that is, the smallest multiple that is exactly divisible by every member of a set of numbers. For example, the lowest common multiple of 12 and 18 is 36.

The pointer controller preferably has a second pointer for pointing to.or accessing a table of the circular buffer lengths. This table may be stored in external memory such as standard program memory or in internal processor memory, such as in a scratchpad area. The pointer controller can then read the circular buffer lengths from the table to control the address pointer. Preferably the table includes a length entry for each of the plurality of circular buffers and the pointer controller controls a second pointer to point to each of these entries in turn, for example incrementing or dec.rementing the second pointer, using a counter, modulo the number of circular buffers. Preferably the counter

controller determines, for each of the circular buffers, an offset for the address pointer from the start of the buffer and a residual distance to the end of the buffer, for moving the address pointer from buffer to buffer.

The invention also provides a data delay structure comprising set of data delay units for providing a plurality of delays of different lengths, each data delay unit comprising a plurality of memory elements, the delay structure further comprising a common memory element address pointer for addressing memory elements in each of said data delay units.

Again by sharing a single address pointer between a plurality of data delay structures the demand on address registers within a controlling digital signalling processor is reduced. Preferably the delays are synchronized, for example by being driven from a common clock, and preferably the delay units are separated in memory by a fixed distance, or occupy substantially contiguous memory blocks, to simplify addressing calculations. In a related aspect the invention provides a method of generating addresses for a plurality of different modulo addressing ranges, the method comprising, controlling an address pointer to point to an address within each of said ranges in turn at a range offset determined by a count, and then adjusting said count.

The count may be adjusted by either incrementing or decrementing a counter, for example by a fixed quantity such as 1. The address offset within each range is determined by this count and thus a single address pointer may be used to provide module addressing for a plurality of different ranges, for example for. circular buffers of different lengths. Preferably the count is adjusted module a lowest common multiple of the spans of the ranges and, where these ranges define circular buffers, preferably these buffers are arranged sequentially in memory addressing space and, more preferably, are contiguous. A table of lengths of thesecircular buffers may be provided in another portion of memory addressing space.

In a further aspect the invention provides a method of generating addresses for a plurality of circular buffers of different lengths using a common counter register to provide a count, the method comprising (i) determining a base address of a said circular buffer; (ii) writing said base address into a buffer pointer; (iii) reading a buffer length for the said buffer from a table of buffer lengths for the plurality of circular buffers, (iv) determining an offset for said buffer pointer by determining a value of said count module said buffer length; and (v) adding said offset to said buffer pointer to generate a buffer address for the said circular buffer; and then (vi) repeating (i) to (v) for each of said plurality of circular buffers.

Preferably this method further comprises adjusting the count module a lowest common multiple of the circular buffer lengths and repeating (i) to (vi). Preferably the method also includes initializing the buffer pointer. The base address may be determined by adding a residual value to a previous buffer address, the residual value being determined using the offset added to generate the previous buffer address.

In another related aspect the invention provides digital signal processing apparatus comprising, processor control code memory storing code for controlling the processing apparatus, a memory interface for accessing data to be processed; and a processor operable to access and process said data in accordance with stored instructions; and wherein the processor control code comprises code for controlling the processor to generate addresses for a plurality of different module addressing ranges.

Preferably the processor control code comprises code for controlling the processor to control an address pointer to point to an address within each of said ranges in turn at a range offset determined by a count, and then to adjust the count. The memory interface may comprise for example, an interface to external memory and the stored instructions may comprise, for example external stored program code. The processor control code may be implemented internally, for example as microcode instructions or microinstructions" and stored, for example, in firmware.

The invention further provides code, and a carrier medium carrying the code, to implement the above-described address generators, delay data structures, and methods.

This code may comprise microcode for a processor such as a DSP, or conventional program code.

The carrier may comprise a data carrier or storage medium such as a hard or floppy disk, CD-or DVD-ROM or programmed memory such as read-only memory (firmware), or an optical or electrical signal carrier. As the skilled person will appreciate the code may be distributed between a plurality of coupled components for example over a network.

The skilled person will recognise that embodiments of the invention may be implemented in software/firmware or in hardware, for example an ASIC, or in a combination of both. For example, embodiments of the address generation unit, delay structure, or methods may be incorporated in a processor such as a DSP to enhance the processor's instruction set to provide for more efficient implementation of digital filters such as lattice filters. Alternatively embodiments of the invention may be incorporated in dedicated digital filters such as matched filters, lattice filters, or correlators, for example Golay correlators. The skilled person will further recognise that the invention is able to provide particular benefits in applications such as mobile phones/terminals and base stations for CDMA-based mobile communications systems and networks.

These and other aspects of the invention will now be further described, by way of example only, with reference to the accompanying figures in which: Figure 1 shows the structure of a generic 3G mobile phone system; Figures 2a and 2b show, respectively, an example of a front end for a. spread spectrum receiver, and a spread spectrum decoder according to the prior art;

Figure shows the main elements of a spread spectrum rake receiver; Figure 4 shows an exemplary W-CDMA rake receiver for a digital mobile phone network; and

Figure 5 shows a block diagram of a Golay correlator for a 3G mobile phone system; Figure 6 shows a memory map and registers for a module addressing scheme according to an embodiment of the present invention; Figure 7 shows a flow diagram of a table-based module addressing procedure according to an embodiment of the present invention; and Figure 8 shows a memory map of circular buffers for the Golay correlator of Figure 5.

Referring to Figure 6, this shows a memory map 600 and a set of registers 602 for implementing a module addressing scheme according to an embodiment of the present invention. The memory map 600 comprises a first area 604 in which is stored a table of N delay values or lengths for a plurality N of circular buffers, and a second area 606 providing storage to implement the buffers themselves. Second memory area 606 comprises a first circular buffer storage area 608, a second circular buffer storage area 610, a third circular buffer storage area 612, and so on up to Nth circular buffer storage area 614.

Preferably these circular buffer storage areas are arranged in contiguous memory blocks. Each of these storage areas provides memory elements for implementing a FIFO (first in first out) circular shift register or buffer for a data delay. To implement a delay using a circular buffer a data sample is read from a memory location indicated by a circular pointer and then a new data sample is written into this location. The pointer is then incremented to point to the following memory location, which holds the next oldest data sample (i.e. the sample with the greatest delays) which is read from and written to next.

The delay provided by such a circular buffer is n clock (read/write) cycles, where n is the length of the shift register, since n clock cycles are required for the pointer to loop around the buffer. The delay may be varied by varying the length n of the circular shift register or, alternatively, by varying an offset between buffer write and read positions.

Generally the circular buffers 608, 610, 612, 614 will have different lengths, as can be

seen by inspection of the delays 502 in the correlator of Figure 5 and, generally speaking, the sequence of buffer lengths is not monotonic.

The registers 602 for the module addressing scheme comprise a table index address pointer 616 (rl) for indexing into the table in first memory area 604 and a delay (circular buffer) memory element address pointer 618 (rO) for accessing the delay memory elements of the circular buffers in second memory area 606. Also provided are a plurality of user writable control registers 620 and an internal control register 622.

The user writable control registers 620 comprise a lowest common multiple register 624 (rLCM) which contains the lowest common multiple (LCM) of the delays of all the delay structures or elements 608, 610, 612, 614 (that is, the LCM of the circular buffer lengths); a base value register 626 (rB) which contains a base address 607 of second memory area 606; a top value register 628 (rT) which contains a top address 615 of second memory area 606; and a current delay count register 630 (rCDC), an accumulator for holding a current delay count for forming a memory element address using address pointer 618 (rO).

The internal control register 622 comprises a current delay value residual register 632 (rCDVR) which contains a temporary value used to calculate the next address to be accessed, which will be pointed to by memory element address pointer 618 (rO). The table index pointer 616 operates as a module address counter, pointing to each entry in table 604 in turn and then looping back to the start. The current delay count register 630 is incremented module the value in lowest common multiple register 624 (rLCM).

Figure 7 shows a flow diagram of a table-based module addressing scheme for addressing a plurality of circular buffers using a single counter, current delay count register 630 (rCDC). The procedure of Figure 7 may be implemented by conventional program code but preferably is implemented in microcode for a DSP, to provide an enhancement to the DSP's instruction set for more efficient implementation of a filter comprising a plurality of delays Di.

Broadly speaking a counter counts module a lowest common multiple of the delays D which, where the delays are in powers of two, is simply the length of the maximum delay. A base address for delay D (the longest delay), and the count, are used to determine a read/write access address for delay D and then a new base address for the next delay is calculated, by adding on the distance to the end of the buffer for D For each delay Di the count module the length of the circular buffer for delay Di is added to the base address for Di to provide a read/write access address. In this way an address is provided for each delay Di in turn and the count is then incremented.

In more detail and referring to Figure 7, at step S700 registers rO 618, rl 616, rCDC 630 and rCDVR 632 are initialized. Then, at step S702, the address pointed to by rO 618 is used in an overlying filter calculation, for example by reading data from or writing data to this address. Immediately after initialization rO 618 will normally point to the buffer area 608 for filter delay Do, but on subsequent passes rO 618 will have been updated to point to subsequent delay blocks, such as buffer areas 610j 612 and 614 of Figure 6. It will be recognised that step S700 will not generally be embodied in DSP microcode but may instead be implemented by part of a user program.

At step S704 register rO 618 is updated to point at the base of the next set of delay elements, for example the base of second circular buffer area 610, by adding the value in the Current Delay Value Residual register 632, rCDVR. This may be performed module the difference between top value register rT 628 and base value register rB 616 of the complete buffer area 606.

Register rl 616 points at a table of delay stage lengths and more particularly points at the length of the next delay stage. Thus if rO 618 is pointing at delay element block D then rl is pointing at the second element in the table which holds the size of delay block DO The offset (OFFSET) into the next delay block is calculated at step 706, from the current delay count register rCDC 630 and the contents of the table at the point indicated by rl, denoted by *rl. The offset is equal to rCDC module *rl and, at step S708, this is added to rO 618. Optionally the calculation at step S708 may be performed module (rT-rB), although there should be no wrap-around at this point.

A new value for the Current Delay Value Residual register 632 rCDVR is then calculated at step S710, by subtracting the offset determined at step S706 from *rl (that is, the length of the circular buffer rO now points at). Register rl 616 is then incremented, at step S712, module N (the total number of delays/circular buffers) to point to the next delay length in the table in first memory area 604. The table pointer rl is incremented using a conventional module addressing mechanism.

Where the procedure of Figure 7 is implemented in DSP microcode, the instruction may complete following step S712 or the procedure may loop back to step S702 to access data at the updated address pointed to by rO 618. This loop may be repeated to automatically address each of the filter delays Di before the instruction terminates.

The procedure may be continued with step S714 in which the Current Delay Count register rCDC is incremented module the lowest common multiple of the delay lengths.

Again the procedure may terminate here or may loop back to step S702, for example in a continuous loop, to access the next delay memory element in each of the filter delays.

It will be recognised that where there are delays of length, say, 128, 64, 32, 16 whilst the counter counts from O to 127 the offset into the 64length delay loops through this buffer twice, the offset into the 32 length delay loops through this buffer four times and the offset into the 16-length delay loops through this buffer eight times.

Optionally, after step 714 register rO 618 may be reset to the address in base value register 626 rB, although this should not be necessary where adjustments to rO are wrapped around according to a conventional modulo addressing scheme based upon the base 626 and top 628 value registers rB and rT. It will be appreciated that in other embodiments registers rO and/or rl may be decremented rather than incremented.

It is helpful to consider a concrete application of the procedure of Figure 7, such as its application to the efficient Golay correlator of Figure 5. To implement this filter the second memory area 606 comprises 255 contiguous memory locations that are allocated to the delays DO to D7 (502a - 502h in Figure 5). The first memory area 604 holds a table of eight delay values, as set out below, where n is the delay length of each delay stage:

Di,i = | rlI *rl,n= _ O O128

1 164 _ 2 216 3 332 4 48 5 51 _ 4 7 72 TABLE 1

Register rl 616 points to this table which, for convenience, is assumed to have a base address of 0. Likewise, for convenience, the second memory area 606 will also be assumed to have a base address of O (rB = 0), but in a different region of the memory space. Register rO 618 is initially set equal to rB, that is to 0, register rl 616 is initially set to 1, and rCDVP is initially set to 128, the length of D . The top value register 628 rT is set to 255, that is 1 beyond the maximum address which will be pointed to by rO.

The Current Delay Count register 630 rCDC is also initialised to O and the Lowest Common Multiple register 624 rLCM is set to 128.

Figure 8 shows a memory map of the second memory area 606, as arranged for implementing the efficient Golay correlator of Figure 5. The memory map comprises eight areas 800, 802, 804, 806, 808, 810, 812, 814 each providing storage for a circular buffer for a respective one of delays 502a to 502h. Memory 800 comprises 128 storage locations, memory area 802, 64 storage locations, and so forth.. The address 816 of the initial storage location of each of memory areas 800-814 is shown and the corresponding storage location is indicated by a respective dashed line. Thus, for example, memory 814 has 2 storage elements for the 2 unit (n=2) delay 502h, the first of which has address 253, the second having address 254.

Table 2 shows the values of rO, rl, rCDVR, and the accessed read/write address for each of delay stages Do to D7 as the procedure of Figure 7 is implemented. Table 2 shows a first cycle through the procedure in which the current delay count is O (rCDC=O) so that there is zero offset (OFFSET = 0) for each delay stage.

DELAY ADDRESS

STAGE rO rl rCDVR ACCESSED D 128 64

t, 192} Polo 128 D 208 2DS

D3 240 5 8

D4 248 6 I

i Alp / 248 t10 2:1 0 2 9 D I I.G 25

TABLE 2

Referring to Table 2, initially address O is accessed and then rO is updated by adding rCDVR to 128, the base address for Do. Register rl initially points to the second entry in Table 1, that is to 64, and thus rCDVR is updated to 64; then rl is incremented to 2.

Address 128 of Di is then accessed and rO is once again updated. At delay D7 rO is

Pi updated to 255 (253 + 2; see step S704 of Figure 7) which is equal to O module 255 (rT - rB). Register 632, rCDVR is updated to 128 (*rl = 128 as rl = 0; OFFSET = 0) and register rl 616 is incremented to 1. Thus when the procedure loops back to point to the buffer for delay DO the value of rO, rl and rCDR are as they were initially. The Current Delay Count register 630 rCDC is incremented (step S714 of Figure 7) at this point so that this time around the next memory storage element in each delay is addressed, and so forth.

It can therefore be seen that the filter of Figure 5, which has eight separate delay stages, may be implemented using only two address pointers, register rO 618 and register rl 616, as compared with the eight which would be conventionally required. Furthermore only five other temporary and control registers are required as compared with the sixteen which would be needed in a conventional approach.

The invention has been described with reference to digital mobile phone networks but the skilled person will appreciate that it has applications in other radio communications systems, such as Hiperlan 2, and also in more general signal processing systems. Many effective alternatives to those described will no doubt occur to the skilled person and will be understood that the invention is not limited to the described embodiments but encompasses modifications apparent to those skilled in the art lying within the spirit and scope of the claims appended hereto.

Claims (29)

CLAIMS:

1. An address generation unit for generating addresses for a plurality of circular buffers of different lengths, each said circular buffer comprising a block of memory elements, the address generation unit comprising: a counter to provide a count; an address pointer for pointing to said memory elements; and a pointer controller to control said address pointer to point to each said memory block in turn, at a position dependent upon said count.

2. An address generation unit as claimed in claim 1 wherein said counter is configured to count module a lowest common multiple of said circular buffer lengths.

3. An address generation unit as claimed in claim 1 or 2 wherein said pointer controller comprises a second pointer for pointing to a table of said circular buffer lengths, and wherein the pointer controller is configured to read said circular buffer lengths from said table to control said address pointer.

4. An address generation unit as claimed in claim 3 wherein said table has a length entry for each of said plurality of circular buffers, and wherein said pointer controller is configured to control said second pointer to point to each said entry in turn.

5. An address generation unit as claimed in any one of claims 1 to 4 wherein said pointer controller is configured to determine, for a said memory block, an offset for said address pointer from the start of the block and a residual distance to the end of the block, for controlling said address pointer to point to each said memory block in turn.

6. A digital filter including the address generation unit of any one of claims 1 to 5 for generating addresses for a plurality of data delays each comprising a said circular buffer.

7. A microprocessor including the address generation unit of any one of claims 1 to 5 or the digital filter of claim 6.

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8. A data delay structure comprising set of data delay units for providing a plurality of delays of different lengths, each data delay unit comprising a plurality of memory elements, the delay structure further comprising a common memory element address pointer for addressing memory elements in each of said data delay units.

9. A data delay structure as claimed in claim 8 further comprising a counter to provide a delay count, and means to determine an offset for said address pointer for each said delay unit by determining a value of said delay count modulo a delay length of the delay unit.

10. A data delay structure as claimed in claim 9 wherein said counter is configured to count module a lowest common multiple of said delay lengths.

11. A data delay structure as claimed in any one of claims 8 to 10 wherein said memory elements of said set of data delay units comprise sequential memory elements of a block of memory elements.

12. A data delay structure as claimed in claim 11 further comprising means to determine a distance from said address pointer to an end of a block of memory elements comprising a said delay unit; and means to modify said address pointer to point at memory elements of a subsequent data delay unit using said determined distance.

13. A method of generating addresses for a plurality of different module addressing ranges, the method comprising: controlling an address pointer to point to an address within each of said ranges in turn at a range offset determined by a count; and then adjusting said count.

14. A method as claimed in claim 13 wherein each of said modulo addressing ranges has a span, and wherein said count is adjusted module a lowest common multiple of said range spans.

]5. A method as claimed in claim 13 or 14 wherein said controlling of said address pointer to point to an address within each of said ranges in turn further comprises determining a residual length of a said range span using said range offset.

16. A method as claimed in claim 13 wherein said determination of said range offset comprises reading a span for the range from a table storing a span for each of said ranges, and determining said offset by determining a value of said count modulo said range span.

17. A method as claimed in any one of claims 13 to 16 further comprising: initialising said address pointer; and initialising said count.

18. A method as claimed in any one of claims 13 to 17 wherein said addressing ranges each define a circular buffer.

19. A method as claimed in claim 18 wherein said circular buffers are arranged sequentially in memory addressing space and have substantially the same mutual spacing.

20. A method as claimed in claim 19 wherein said circular buffers occupy a substantially contiguous portion of memory addressing space.

21. A method of digitally filtering data including generating address for a plurality of different module addressing ranges as claimed in any one of claims 13 to 17, each of said module addressing ranges defining an addressing range of a delay unit for said filtering.

22. A method of generating addresses for a plurality of circular buffers of different lengths using a common counter register to provide a count, the method comprising: (i) determining a base address of a said circular buffer; (ii) writing said base address into a buffer pointer;

(iii) reading a buffer length for the said buffer from a table of buffer lengths for the plurality of circular buffers; (iv) determining an offset for said buffer pointer by determining a value of said count module said buffer length; and (v) adding said offset to said buffer pointer to generate a buffer address for the said circular buffer; and then (vi) repeating (i) to (v) for each of said plurality of circular buffers.

23. A method as claimed in claim 22 further comprising: (vii) adjusting said counter register count module a lowest common multiple of said circular buffer lengths; and (viii) repeating (i) to (vi).

24. A method as claimed in claim 22 or 23 wherein said determining of a base address comprises adding a residual value to a previous buffer address, said residual value being determined using the offset added to generate said previous buffer address.

25. A method as claimed in any one of claims 22 to 24 further comprising initialising said count.

26. Digital signal processing apparatus comprising: processor control code memory storing code for controlling the processing apparatus; a memory interface for accessing data to be processed; and a processor operable to access and process said data in accordance with stored instructions; and wherein the processor control code comprises code for controlling the processor to generate addresses for a plurality of different module addressing ranges.

27. Digital signal processing apparatus as claimed in claim 26 wherein the processor control code comprises code for controlling the processor to: control an address pointer to point to an address within each of said ranges in turn at a range offset determined by a count; and then

adjust said count.

28. Processor control code to, when running, implement the address generator of any one of claims 1 to 5, the delay data structure of any one of claims 8 to 12 or the method of any one of claims 13 to 25.

29. A carrier carrying the processor control code of claim 28.