GB2382891A

GB2382891A - Apparatus for hardware revision identification

Info

Publication number: GB2382891A
Application number: GB0129259A
Authority: GB
Inventors: Nicholas Craig Bowdler
Original assignee: NEC Technologies UK Ltd
Current assignee: NEC Technologies UK Ltd
Priority date: 2001-12-06
Filing date: 2001-12-06
Publication date: 2003-06-11
Anticipated expiration: 2021-12-06
Also published as: GB0129259D0; GB2382891B

Abstract

An apparatus for hardware revision identification in an electronic device comprising a CPU 10 including a plurality of data input-output lines (12, 14, 16, 18, 20, 22, 24, 26) coupled to the CPU (10), means for supplying a binary signal to the data input-output lines in dependence on the present hardware state of the device and means for loading software suitable for operating the present hardware state of the electronic device in dependence on the binary signal received from the data input-output lines.

Description

Apparatus for Hardware Revision Identification This invention relates to an apparatus for hardware revision identification using data bus resistors.

Modern electronic products are frequently updated or changed resulting in different revisions or versions of the product. These revisions may be variations in the hardware state of the product. An example of a system in which hardware revisions are frequent is a mobile telephone device. The revisions are typically introduced to improve the performance of the device or to expel the effects of bugs.

Within a device, multiple hardware revisions need to be supported by a common software build. The software for operating multiple versions or hardware revisions of the device will typically be programmed into the microprocessor during manufacture. Each hardware revision will require unique software. Therefore the CPU must identify the hardware state of the device and then run the software associated with that particular hardware state.

Typically an identity signal is associated with each hardware state. The CPU contains a look up table which associates each identity signal with a particular hardware state and corresponding software. On receiving a particular identification signal the CPU recognises and identifies the signal. The CPU then executes the software required to operate that version of the device.

Typically the identity signal for a hardware revision is implemented by use of dedicated CPU I/O ports. This approach requires few components but adds additional pins to the CPU which will increase the cost of the package. A

CPU typically dedicates four pins to hardware identification although other numbers are possible. Each pin can be set to high or low. Therefore four pins can support 16 different combinations. Each combination corresponds to a particular hardware state of the device.

In this example the device can support 16 hardware states.

In modern systems it is beneficial to support a large number of hardware revisions. However increasing the number of pins available for hardware revision is problematic since both size and cost are important factors in production of electronic devices.

Many systems include resistors added in parallel to the data bus. These resistors are used during normal operation to prevent quiescent current due to leakage currents switching input buffers. Normally the resistors are arranged to give all high or all low values.

The present invention uses the resistors in parallel with the data bus to define a static value when no other peripheral device is active. These resistors can be arranged so that some of the data lines are set high and others low. The combined binary signal produced by the resistors can be read by the CPU when all other peripherals on the bus are deselected.

A look up table is programmed into the CPU which associates a given binary signal with a particular hardware state of the system. On receiving a particular binary signal the ASIC will identify the present hardware state of the device and then load the software suitable for operating the system in its present hardware state.

The present invention has the advantage that no additional components or CPU pins are required. The ASIC can support

a number of hardware configurations equal to the number of binary combinations from the data lines.

According to the present invention there is provided an apparatus for hardware revision identification in an electronic device comprising; a CPU including a plurality of data input-output lines coupled to the CPU, means for supplying a binary signal to the data lines in dependence on the present hardware state of the device and means for loading software suitable for operating the present hardware state of the electronic device in dependence on the binary signal received from the data input-output lines.

According to the present invention there is further provided a method for hardware revision identification in an electronic device including a CPU with a plurality of data input-output lines, comprising the steps of; applying a binary signal to the data input-output lines, identifying the binary signal from the data input-output lines, and loading software for operating the present hardware state of the electronic device in dependence on the identified binary signal.

Preferred embodiments of the present invention will now be described with reference to the accompanying drawings in which; Figure 1 shows an embodiment of the present invention.

Figure 2 shows a further embodiment of the present invention.

Figure 3 is a flow diagram showing the procedure for updating the hardware state of a device.

Figure 1 shows an embodiment of the present invention.

The device includes eight resistors 28,30, 32,34, 36, 38,40 and 42. The CPU includes eight data input-output lines, 12,14, 16,18, 20,22, 24 and 26. Each data input-output line is connected to a different resistor.

The resistors are generally high value, typically 100kOhm, although in practice any value of resistor can be used.

The individual values of the resistors within the device can also vary.

Each resistor is further connected to either ground 46 or Vdd 44. Therefore each resistor is connected between a data input-output line from the CPU and either ground 46 or Vdd 44. Vdd 44 is the internal voltage supply of the system although other voltage sources can be used.

Electrical connections are made by soldering or by alternative methods suitable for producing electrical connections.

After connecting the resistors the power supply Vdd 44 is initiated. Each data input-output line will carry either a high or a low signal to the CPU 10. The data inputoutput lines connected via a resistor to Vdd 44 present a high signal to the CPU and the data input-output lines connected via a resistor to ground present a low signal to the CPU. The combination of signals will produce a binary value. The CPU then compares the binary value received with a stored look up table in order to identify the present hardware state of the device.

In figure 1 data input-output line DO 12 is connected to resistor R1 28 which is subsequently connected to Vdd 44.

Therefore data input-output line DO 12 will present a high value to the CPU 10. Data input-output line D1 14 is connected to resistor R2 30 which is subsequently connected to ground 46. Data input-output line D1 14 will present a low value to the CPU 10. Data input-output

lines D2 16, D3 18, D4 20, D5 22, D6 24 and D7 26 are connected to ground 46 via R3 32, R4 34, R5 36, R6 38, R7 40 and R8 42 respectively and therefore each of these data input-output lines will present a low signal to the CPU.

The eight bit implementation of figure 1 will present a binary signal of 00000001 to the CPU 10; an ID value = 1.

Figure 2 shows a further embodiment of the present invention. This embodiment includes eight resistors.

Each resistor is connected to a different data inputoutput line. Data input-output lines DO 52, D2 56, D4 60 and D6 64 are connected to ground 86 via resistors R1 68, R3 72, R5 76 and R7 80 respectively. Each of these data input-output lines will provide a low signal to the CPU.

Data input-output lines D1 54, D3 58, D5 62, D7 66 are connected to Vdd 84 via resistors R2 70, R4 74, R6 78 and R8 82 respectively. Each of these data input-output lines provides a high signal to the CPU. Upon activating the voltage supply Vdd 84, the eight bit implementation of figure 2 will present a binary signal of 10101010 to the CPU; an ID value = 170.

Figure 3 is a flow diagram showing the procedure for revising the PCB hardware in a device. At 100 a look up table is programmed into the CPU. The look up table associates each binary signal with a corresponding hardware build of the system. The look up table further identifies the software required for each hardware build.

At 102 a first end of each resistor is connected to a different data input-output line of the CPU. At 104 the second end of each resistor is connected to either ground or to a voltage supply. These electrical connections may be made manually or by another means, and are typically effected at time of manufacture, although could be changed at a later stage. This could allow a mass produced device to be altered to specific variants.

When all data input-output lines have been connected to Vdd or ground via a resistor the voltage supply is activated at 106. The signal from each data input-output line is registered by the CPU at 108. At 110 the CPU compares the combined binary signal received from all data input-output lines with the programmed look up table and identifies the present hardware state of the system. At 122 the CPU loads suitable software to operate the present hardware state of the system.

At any time after the binary signal has been registered by the CPU, the voltage source can be de-activated and resistors disconnected from the voltage source. The resistors can then be used for other purposes. However, in other cases the circuit is maintained until the hardware state of the system is revised.

In further embodiments of the present invention at least one data input-output line may be connected directly to either ground or Vdd and therefore not require a resistor in series.

It is clear from the above description that the present invention provides a means for hardware revision identification using data input-output bus resistors. In general no additional components are required.

Furthermore the invention does not require pins to be dedicated to hardware revision.

It will be clear to those skilled in the art that many variations to the embodiments described are possible without departing from the scope of the invention which is limited solely by the claims attached.

Claims

Claims 1. A method for hardware revision identification in an electronic device including a CPU with a plurality of data input-output lines, comprising the steps of; applying a binary signal to the data input-output lines, identifying the binary signal from the data input-output lines, and loading software for operating the present hardware state of the electronic device in dependence on the identified binary signal.
2. A method according to claim 1 wherein the binary signal is applied to the data input-output lines by connecting each data input-output line either to ground or to a voltage supply.
3. A method according to claim 1 or 2 wherein the identified binary signal is compared with a look up table to determine the present hardware state of the electronic device.
4. A method according to claims 1,2 or 3 wherein the determined current hardware state of the electronic device is compared with a look up table to identify the software required to be loaded to operate the determined present hardware state of the electronic device.
5. A method according to claim 1,2, 3 or 4 wherein at least one resistor is connected in series with each data input-output line.
6. A method for hardware revision identification in an electronic device as claimed in claim 1 substantially as herein described, with reference to the accompanying drawings.

<Desc/Clms Page number 8>
7. An apparatus for hardware revision identification in an electronic device comprising; a CPU including a plurality of data input-output lines coupled to the CPU, means for supplying a binary signal to the data inputoutput lines in dependence on the present hardware state of the device and means for loading software suitable for operating the present hardware state of the electronic device in dependence on the binary signal received from the data input-output lines.
8. An apparatus according to claim 7 wherein the binary signal is applied to the data input-output lines by connecting each data input-output line either to ground or to a voltage supply.
9. An apparatus according to claim 7 or 8 wherein the identified binary signal is compared with a look up table to determine the current hardware state of the electronic device.
10. An apparatus according to claim 7,8 or 9 wherein the determined current hardware state of the device is compared with a look up table to identify the software required to be loaded to operate the determined current hardware state of the device.
11. A method according to claim 7,8, 9 or 10 wherein at least one resistor is connected in series with each data input-output line.
12. An apparatus for hardware revision identification in an electronic device as claimed in claim 7 substantially as herein described, with reference to the accompanying drawings.