GB2370733A

GB2370733A - Clock regeneration in an Orthogonal Frequency Division Multiplex (OFDM) receiver

Info

Publication number: GB2370733A
Application number: GB0122038A
Authority: GB
Inventors: Akiko Maeno; Takashi Fujiwara; Jun Ido
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 2000-09-13
Filing date: 2001-09-12
Publication date: 2002-07-03
Anticipated expiration: 2021-09-12
Also published as: CN101729487A; JP2002094480A; CN101729487B; CN1344073A; GB2370733B; GB0122038D0; JP4003386B2

Abstract

Received OFDM signals are subjected to discrete Fast Fourier transformation (FFT). Frequency component data of a pilot sub-carrier and those of a previous pilot sub-carrier temporarily stored in RAMs 6, 7 are subjected to complex multiplication 11 and fed to ROM 12. The ROM reads out phase fluctuations between adjoining pilot signals (see figure 4) in a common symbol to an adder 15 which accumulates the phase fluctuation data for one symbol period. An offset adder 16 adds a predetermined offset to the accumulated phase fluctuation to align the FFT time window. The result is used to control the frequency of the sampling clock signal (166, figure 2). The circuit is able to generate a clock signal having neither a frequency error nor a phase error.

Description

S P E C I F I C A T I O N

TITLE OF THE INVENTION

Clock Signal Regeneration System and Receiver System, and Clock signal Regeneration Method and Receiving Method BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a clock regeneration system and a clock regeneration method, and a receiver system and a receiving method, as used in a system for receiving a modulated signal modulated on the basis of the OFDM system.

2. Description of the Prior Art

In recent years, as a method for transmitting digital signals,therehas been proposed a modulation system,as celled the "Orthogonal Frequency Division Multiplexing" (as will be abbreviated into the "OFDM system't).

In this OFDM system, a number of orthogonal subcarriers are generated in a transmission band, and data are assigned to the amplitudes and phases of the individual subcarriers so that the digital modulations are made by using the technique such as the PSK (Phase Shift Keying) or the CAM (Quadrature Amplitude Modulation).

In this OFDM system, the transmission band is divided

by the numerous subcarriers, and these numerous subcarriers are transmitted in parallel, so that the transmission band to be assigned to one subcarrier is narrowed.

On the other hand, the transmission speed for one subcarrier is lowered, but the number of carriers is so large that the synthetic transmission speed is unvaried from that of the conventional modulation system (e.g., the QPSK: Quadrature Phase Shift Keying or the CAM).

According to this OFDM system, on the other hand, the numerous subcarriers are transmitted in parallel so that the signal amount of one symbol (or one OFDM symbol)' as contained in en arbitrary unit time, is reduced to lower the transmission speed of the symbol.

In the transmission path haying the so-called''multipath disturbance", however, the time length of the multipath can be shortened relative to the time length of the symbol so that the OFDM system can be expected as one strong against the multipath disturbance.

From the features thus far described, the OFDM system is advantageous for the case of performing the digital signal transmission of ground waves, as might otherwise be seriously influenced by the multipath disturbance of the topography or the buildings, so that it is also adopted in the Japanese digital ground wave broadcasting system.

Here, in order to demodulate the OFDM modulated signal

correctly in the receiver of the OFDM type, it is necessary to make the various synchronizations in a demodulation circuit, and a clock signal or the reference for all the actions in the demodulations has to be synchronized with a clock signal on the sending side.

Herewillbedescribedaclocksignalreproducingmethod, as has been proposed in the prior art as a method for

synchronizing the clock signal, as generated on the receiving side, with the clock signal on the sending side.

Fig. 1 is a block diagram of a clock signal regeneration circuit in the OFDM receiver, as disclosed in Japanese Patent Laid-open No. 308715/1998.

A regeneration circuit 115 of a clock signal is constructed, as shown, to include: a differential demodulator 3 for a differential demodulation (for demodulating a phase difference between a carrier received before and a carrier being received); a ROM (Read Only Memory) 12; a gate circuit 14; a cumulative adder 15 (cumulative addition means); an averaging circuit 23; a comparator 18; a control circuit 20; a sign reversing circuit 21; a selector 22; and a clock oscillation control circuit 60 (or control means).

The differential demodulator 3 includes RAMs (Random Access Memories) 6 and 7 (or storage means), a sign reversing circuit 10 and a complex multiplier 11.

Here will be described the actions.

A subcarrier frequency signal (or an intermediate frequency (IF) signal) of an analog signal, as subjected to a primary demodulation by a main carrier frequency signal, is digitized by an analog/digital (A/D) conversion circuit contained in the OFDM receiver.

An I-channel demodulated data IR(as will be abbreviated into "IR") and a Q-channel demodulated data QR (as will be abbreviated into "QR") for each symbol, as generated in a demodulator of a subcarrier frequency signal (or a base-band signal) from the digitized IF signal, are inputted to the differential demodulator 3.

On the basis oftheseIR and QRinputted,the differential demodulator 3 computes rear component data RN and imaginary component data JN.

Here, the date IR and QR are outputted from a fast Fourier transformation (FFT) circuit for executing the discrete Fourier transformation, as contained in the demodulator of the base-band signal.

The RAMs 6 and 7 in the differential demodulator 3 store the inputted data IR or QR at the symbol unit in response to a control signal c, as outputted from the later-described control circuit 20, and outputs the stored data (IR or QR) for each symbolwithadelayofonesymboltime. The sign reversing circuit 10 reverses the plus/minus sign of the data outputted from the RAM 7, and outputs the reversed data.

For the data IR and QR left undelayed, the complex multiplier 11 in the differential demodulator 3 performs the complex computations, as expressed by the following Formula (1), on the basis of the data dIR and dQR delayed by the RAM 6 and the RAM 7, respectively.

Here, the computation result is outputted separately into real component data RN and imaginary component data JN.

In the following description, letter j indicates an imaginary

number. (IR + jQR)(dIR - jdQR) - - - - - - - - - - (1).

This Formula (1) is developed to obtain: Real Component Data RN = IR dIR + QR dQR; and Imaginary Component Data JN = dIR QR - IR dQR.

The ROM (Read Only Memory) 12 is stored with arc tangent (are tangent function)data,and outputs phase fluctuation date PS (which indicate the phase fluctuations between IR, QR and dIR and dQR) corresponding to the real component data RN and imaginary component data JN inputted.

Here, a computation circuit 13 is constructed to include the complex multiplier 11 and the ROM 12.

One symbol in the OFDM system is composed of a plurality of (several hundreds to thousands) subcarrier frequency signals, a plurality of which are assigned to a pilot signal.

In accordance with a control signal from the control

circuit 20, therefore, the gate circuit 14 selects only the component of the phase fluctuation data PS outputted from the ROM 12 that corresponds to the pilot signal inserted on the sending side, and feeds the selected component to the sign reversing circuit 21 and the selector 22 (in the following, the phase fluctuation data PS corresponding to the frequency of the pilot signal will be called the "phase fluctuation data PPS") The sign reversing circuit 21 reverses the sign of the phase fluctuation data PPS inputted, and feeds the reversed data to the selector 22.

The selector 22 is controlled with the control signal from the control circuit 20 to select the phase fluctuation data PPS, as inputted directly from the gate circuit 14, if the data PPS have a plus value (or a plus frequency), and to select the phase fluctuation data PPS, as inputted from the sign reversing circuit 21, if the data PPS have a minus value (or a minus frequency), and feeds the selected data to the cumulative adder 15.

The cumulative adder 15 is initialized with a control signal b which is fed from the control circuit 20 just before the phase fluctuation data PS for each symbol are inputted.

After this,the phase fluctuation data PPS outputted from the selector 22 are cumulatively added, and the cumulatively added value (or the phase error) is outputted for each symbol.

The averaging circuit 23 averages the cumulatively added phase error, as outputted for each symbol from the cumulative adder 15, and outputs the averaged phase error for each symbol so that it outputs a phase error PSO from which the Gaussian noises (or the white noises) contained in the phase error are filtered out.

In this case, the Gaussian noises are generated at random with time so that their time-averaged value is 0 (as may be arithmetically averaged. If the phase errors of the individual symbols containing the Gaussian noises are averaged, therefore, the Gaussian noises contained in the phase errors are 0 while leaving only the average value of the signals other than the Gaussian noises.

The comparator 18 detects that the frequency of the clock signal outputted from a clock oscillator for the OFDM receiver has been fixed (or locked in), and informs the control circuit 20 of it.

This lock-in occurs in the case where the differential demodulated data between the individual symbols are 0 so that the outputs for the individual symbols of the averaging circuit 23 have no difference (the state of this case is detected).

The comparator 18 compares a standard value SV equal to the output value of the averaging circuit of the case, in which the differentially demodulated data between the symbols are 0, and the phase error PSO or the prevailing output of the

averaging circuit 23, and outputs the comparison result for each symbol to the control circuit 20.

The control circuit 20 receives the comparison result for each symbol of the comparator 18 and controls the gate circuit 14 and the selector 22 in a manner to match the timing of the phase fluctuation data PS for each pilot signal.

On the other hand, the control circuit 20 outputs the control signal b to the cumulative adder 15 and the control signal c to the RAM 6 and the RAM 7 so that it may control the signals to be inputted end outputted to and from the cumulative adder 15, the RAM 6 and the RAM 7 for the individual symbol periods. On the basis of the output data PSO of the averaging circuit 23, the clock oscillation control signal 60 outputs a control signal CS for controlling the oscillation frequency of the clock signal transmitter for the OFDM receiver.

In the OFDM -receiver disclosed in Japanese Patent Laid-Open No. 308715/1998, the aforementioned clock signal regeneration circuit is used to synchronize the clock signal, as oscillated by the clock oscillation circuit in the OFDM receiver, with the clock signal on the sending side.

Where the subcarrier signal of the OFDM receiver is to be demodulated, the discrete Fourier transformation is executed in a fast Fourier transformation circuit so that a time domain signal is transformed into a frequency domain

signal. At this transformation, the domain for specifying the range of transformation in the time domain is called the "time window''. This time window is dislocated where the crock signal has the frequency error and the phase error.

Where the clock signal has only the phase error but no frequency error, for example, the time window is dislocated by a predetermined time with respect to all the symbols so that a predetermined phase rotation is given to the frequency components of the subcarriers of all symbols.

Where the clock signal has only the frequency error, on the other hand, the time window is dislocated with different times for the individual symbols so that the phase rotation fluctuating with time is given to the frequency components of the subcarriers.

As in the aforementioned OFDM receiver disclosed in Japanese Patent LaidOpen No. 308715/1998, the construction is made to detect the phase fluctuation PPS of the frequency component (i.e., the subcarrier frequency signal in the frequency space after the FFT) which corresponds to the pilot signal series in the subcarriers one symbol before and the suboarriers in the prevailing symbol.

Here, the phase error accompanying the clock signal frequency error is an error of the phase, as appearing in the phase of the subcarrier frequency signal when an error occurs

in the frequency of the clock signal. In this case, the frequency of the clock signal is controlled by using the computation result of the phase error.

Where the clock signal is regenerated according to the detected phase fluctuation PPS (i.e., the phase difference between the subcarrier frequency signals in the common frequency between the different symbols), the detected phase error (i.e., the value prepared by cumulatively adding the phase fluctuation PPSof the frequency component corresponding the plurality of pilot signal series for one symbol period) contains the phase error accompanying the frequency error of the clock signal but not the phase error accompanying the clock signal signal phase error.

This is because, when the frequency error is contained in the clock signal to be regenerated, the subcarriers causes the phase rotation fluctuating with time, so that the phase of the subcarriers fluctuates between the individual symbols, but when the clock signal has the phase error, the phase of the subcarriers does not fluctuate between the symbols so that it cannot be detected as the phase fluctuation between the symbols. As a result, in the clock signal regeneration circuit disclosedin the above-specified PatentApplication,thephase error of the clock signal cannot be controlled to raise a problem that the drawing performance of the crock signalcannot

be improved.

If the clock signal has the frequency error in the OFDM receiver, the orthogonality between the individual subcarriers is lost to cause the disturbances due to the interference between the subcarriers. Since the drawing performance of the crock signal is not enhanced, the frequency error is left in the clock signal to raise a problem that the bit error percentage of the regenerated signal is poor On the other hand, the clock signal regeneration technique, as disclosed in the above-specified Patent Application, cannot defect the phase error of the crock signal.

Under the condition that the frequency of the clock signal is completely synchronized, therefore, the detected outputs are not different between the case, in which the time window is completely coincident to the effective symbol position, and the case in which the same is dislocated forward with time, for example.

Where the time window fails to coincide with the effective symbol position, however, the effective guard interval length is reduced to lower the resistance to the multipath (or multipath noises to be caused by the multipath) of the transmission path or the fading in the frequency selectivity. Therefore, a highly precise control is required for the location of the time window.

For the control of the time window location, there is

a method for calculating the effective symbol position from the correlation between the guard interval and the data of the corresponding last symbol portion. However, this method is troubled by a problem that the defection precision of the phase error is deteriorated by the drop in the correlation value, when a delay is caused to raise a problem by the multipath transmission. Therefore, it has been desired to realize the control by detecting the time window, the crock frequency and the phase error highly precisely.

SUMMARY OF THE INVENTION

The present invention has been conceived to solve the aforementioned problems and has an object to provide a clock signal regeneration circuit for an OFDM receiver, which can generate a clock signal precisely with neither the frequency error nor the phase error, and a clock regeneration method.

Moreover, the clock signal regeneration circuit of the OFDM receiver system in the invention is mainly constructed such that the frequency of the clock signal is controlled on the basis of the output of the phase fluctuation between the pilot signals, as contained for one symbol period of an OFDM modulated signal. This construction controls the frequency of the clock signal on the basis of the output of the phase fluctuation between the pilot signals, as contained for one

symbol period of the OFDM modulated signal, which are obtained on the basis of two signals: the demodulated signal digitized by the clock signal of a predetermined frequency from a signal of a subcarrier frequency band obtained by demodulating the OFDM modulated signal for a main carrier frequency; and the delayed demodulated signal obtained by delaying the demodulated signal.

As a result, it is possible to generate the clock signal having neither the frequency error nor the phase error precisely, and to improve the drawing performance of the crock signal of the OFDM receiver system.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a block diagram showing a receiver system of the prior art;

Fig. 2 is a block diagram showing an OFDM receiver using a clock signal regeneration circuit of Embodiment 1 of the invention; Fig. 3 is a block diagram showing the clock signal regeneration circuit according to Embodiment 1 of the invention; Figs. 4A and 4B are diagrams illustrating the phase errors which appear in the frequency components ofsubcarriers outputted from a fast Fourier transformation circuit (or transformation means)whena crock signal has a frequency error

in the clock signal regeneration circuit according to Embodiment 1 of the invention; Figs. 5A, 5B and 5C are diagrams showing the action principle of Embodiment 1 of the invention; Fig. 6 is a flow chart showing the actions of Embodiment 1 of the invention; Fig. 7 is a block diagram showing a clock signal regeneration circuit according to Embodiment 2 of the invention; Fig. 8 is a block diagram showing a clock signal regeneration circuit according to Embodiment 3 of the invention; and Fig. 9 is a block diagram showing a clock signal regeneration circuit according to Embodiment 4 of the invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiment 1 (OFDM Receiver) Fig. 2 is a block diagram showing a construction of an OFDM receiver using a clock signal regeneration circuit (or a clock signal regeneration system) of Embodiment 1 of the invention. As shown in Fig. 2, an OFDM receiver 150 is constructed to include: a receiving antenna 101, a multiplier 102; a main

carrier oscillator 103 to be used for station selections; a band-pass filter (BPF) 104; an analog/digital (A/D) converter 105; a subcarrier frequency signal demodulator 120 for demodulating asubcarrier frequency signalof the OFDM;a clock signal oscillator 116; and a crock signal regeneration circuit 130. Here, the clock signal oscillator 116 is active to regenerate the clock, as used when modulated in a modulator, and is constructed to include a VCXO or the like, for example.

In this case, the clock signal oscillator 116 is used to determine a phase fluctuation in a common symbol from the phase information of the suboarrier frequency signal.

Here, the crock signal oscillator 116 is controlled with a control signal outputted from the clock signal regeneration circuit 130.

On the other hand, the subcarrier frequency signal demodulator 120 is constructed to include a demultiplexer 106, anumericalcontroloscillatorll0,anadderlll,afastFourier transformation circuit (FFT) 112, a correlation computing circuit 113 and a carrier frequency error computing circuit 114, the actions of which will be described hereinafter.

The receiving antenna 101 receives the OFDM-modulated radio signal (or the OFDM-modulated signal). The multiplier 102 multiplies a predetermined main carrier frequency signal, asoutputtedfromthemaincarrieroscillatorl03, andtheradio

signal received.

The band-pass filter (BPF) 104 extracts (i.e., a primary demodulation: a primary demodulation step) an intermediate frequency (IF) in a subcarrier frequency band from the output of the multiplier 102. The A/D converter 105 converts the analog IF signal,as extracted from the BPF 104, into a digital signal. In short, the primary demodulation is made, and the OFDM signal is digitized by using a clock signal of a predetermined frequency (these actions are made by primary demodulation means). The demultiplexer 106 separates the I-channel IF data and the Q-channel IF data from the digitized IF signal and outputs the separated data (or the demodulated data for each channel). A low-pass filter (LPF) 107 filters out the unnecessary high-frequency components (e.g., the signals of adjoining channels, or the noises), as contained in the I-

channel IF data, and an LPF 108 filters out the unnecessary highfrequency components contained in the Q-channel IF data.

A multiplier 109 generates the I-channel demodulated data and the Qchannel demodulated data while eliminating the frequency errors, by multiplying the I-channel IF data and the Q-channel IF data inputted, by the subcarrier frequency signal which is fed while being controlled by the numerical control oscillator llO.

The fast Fourier transformation circuit (FFT) 112 generates the I-channel IF demodulated data IR and the Q-

channel demodulated data QR, as having been subjected to discrete Fourier transformations, by transforming the I-

channel demodulated data and the Q-channel demodulated data or the time signals inputted from the complex multiplier 109, into frequency components.

The correlation computing circuit 113 inputs the I-

channel demodulated data and the Q-channel demodulated data of the time signals, and computes and outputs the correlations between signals, as discrete from each other for an effective symbol period, from a guard interval period where those . demodulated data are adopted as they are and a guard interval period where the demodulated date are delayed for the effective symbol period.

The carrier frequency error computing circuit 114 detects the frequency errors of the demodulated data IR and QR, which have been subjected to the discrete Fourier transformations, by defecting the offset of the output for each frequency from the output of the FFT 112, and outputs the frequency errors to the adder 111.

The adder 111 adds the correlation output of the correlation computing circuit 113 and the frequency error output of the carrier frequency error computing circuit 114, and feeds the sum to the numerical control oscillator 110.

The guard interval period in the OFDM signal is made by adding to it a signal of the same content as one portion near the trailing end of the effective symbol, and this guard interval period appears for the symbol period To the signal for the guard interval period, there is added the signal of the content identical to one portion near the trailing end of the effective symbol, so that the correlation between the effective symbol and the signal for the guard interval period takes the maximum.

By finding out the portion where the correlation between the effective symbol and the signal for the guard interval period takes the maximum, therefore, it is possible to specify not only the guard interval period in that effective symbol but also the effective symbol period.

In short, the FFT can be practiced for the duration of the effective symbol period by specifying the effective symbol period.. In the subcarrier frequency signal demodulator 120, the computation of the FFT 112 at the downstream stage is started by the complex multiplier 109 at the timing to maximize the correlation, as described hereinbefore, so that the frequency error between the demodulated data IR and OR outputted from the FFT 112 can be minimized (these actions after the A/D conversion are the secondary demodulation (or a secondary demodulation step), end the primary end secondary demodulation

means are totally called the "demodulation means").

On the basis of the I-channel demodulated IR and the Q-channel demodulated data QR, the clock signal regeneration circuit 130 generates a control signal CS for controlling the oscillation frequency of the clock signal oscillator 116.

Here, the control signal CS is different in the contained information from the control signal which has been described in connection with the prior art.

In response to the control signal CS outputted from the clock signal regeneration circuit 130, the clock signal oscillator 116 outputs the clock signal to the A/D converter 105 and another circuit.

The A/D converter 105, the subcarrier frequency signal demodulator 120, the crock signal regeneration circuit 130 and the clock signal oscillator 11, as shown in Fig. 2, construct altogether a PLL circuit 1000 for controlling the frequency of the clock signal.

(Clock Signal Regeneration circuit) Fig. 3 is a block diagram showing a construction of the clock signal regeneration circuit 130 according to Embodiment 1 of the invention.

Here in the clock signal regeneration circuit 130 shown in Fig. 3, the portions for making the same actions as those of the clock signal regeneration circuit 115 of the prior art,

as shown in Fig. 1, will be omitted on their descriptions by

designating them by the common numerals.

A selector 30 is constructed to include: a switch 31 for selecting only the data (IR), as corresponding to the pilot signal, from the I-channel demodulated data IR; and a phase correction circuit 32 for eliminating the phase value (because the pilot signal in the OFDM signal is specified in its phase by the standards and is known so that how far the phase is dislocated can be decided in the regeneration on the receiving side)' as specified on the sending side, from the data selected by the switch 31 (this action step is the phase correction step). Likewise, a selector 40 is constructed to include: a switch 41 for selecting only data (PQR), as corresponding to the pilot signal, from the Q-channel demodulated data QR; and a phase correction circuit 42 for eliminating the phase value, as specified on the sending side, from the data selected by the switch 41.

The phase value corresponding to the pilot signal specified on the sending side is the phase value which is specified according to Japanese digital ground wave broadcasting standards, for example.

In Japanese digital ground wave broadcasting standards, the amplitude and phase of the subcarriers corresponding to the pilot signal are specified in advance on the sending side, and the specified values are also known to the receiving side

(the phase specified on the sending side will be called the "known phase') .

Where the phase of the pilot signal is specified at O or on the seeding side, for example, it is informed in advance to the receiving side whether the phase of the subcarriers corresponding to the received pilot signal is O or (the informing time is set in advance according to the standards).

Where the known phase of the subcarriers corresponding to the pilot signal is x, the phase correction circuits 32 and 42 correct (or subtract in this case) the from the phase of the pilot signal, and output the corrected value.

In a differential demodulator 3, a differential demodulationis mace only on the date corresponding to the pilot signals adjoining in a common symbol. In RAMs 6 and 7, on the other hand, there are stored the Ichannel demodulated data IR and the Q-channel demodulated data QR which are outputted from the phase correction circuits 32 and 42 (which function as phase correction means for correcting the phases of the demodulated signals).

At this time, the data (of which the data corresponding to the pilot signal in the I-channel demodulated data IR are called the "demodulated data PIR", and only the data corresponding to the pilot signal in the Qchannel demodulated data OR are called the "demodulated data PQR") corresponding to the pilot signals in the I-channel demodulated data IR and

the Q-channel demodulated data OR are stored, and delay demodulated data dIR and dQR are outputted by making delays bythetime period corresponding to one interval for generating the pilot signal (here, the delayed demodulated data of the I-channel demodulated dataIR corresponding to the pilot signal will be called the "delayed demodulated data PdIR", and the delayed demodulated data of the Q-channel demodulated data OR corresponding to the pilot signal will be called the "delayed demodulated data PdQR"). In short, the RAMs 6 and 7 function as the delay means, and the delayed

demodulated data PdIR and PdQR outputted from the RAMs 6 and 7 will also be called undelayed demodulated signals"). A sign reversing circuit 10 reverses the sign of the delayed demodulated data dQR, as outputted from the RAM 7, and outputs only the reversed one, i.e., the delayed demodulated data PdQR corresponding to the pilot signal.

One symbol (or period) in the OFDM signal contains several hundreds to thousands subcarrier frequency signals, which contain a plurality of pilot signals. The time period corresponding to the aforementioned one interval for generating the pilot signals means the time period from one pilot signal to an adjoining pilot signal.

A complex multiplier 11 performs complex multiplications between the demodulated data PIR and PQR of

the undelayed pilot signals and the delayed demodulated data PdIR and PdQR of the pilot signals delayed by the RAMs 6 and The results of the complex computations by the complex multiplier 11 are separated into real component data PRN of the pilot signals end imaginary component data PJN of the pilot signals and are outputted.

A ROM 12 reads out the data corresponding to the rear component data PRN and the imaginary component data PJN of the pilot signals inputted, fromarctangent(arctangentfunction) data stored, and outputs the read data as phase fluctuation data PS of the pilot signals.

A cumulative adder 15 (or cumulative adding means) adds cumulatively adds the phase fluctuation data PS of the pilot signals, as outputted from the ROM 12, over one symbol period.

On the other hand, an offset adder 16 (or offset adding means) adds en offset value to the cumulatively added date of the phase fluctuation data PS of the pilot signals outputted from the cumulative adder 15.

Aloop filter50(orfiltermeans)eliminates (or fillers out) the noise components from phase fluctuation data PS2 of the pilot signals outputted from the offset adder 16.

Aclockoscillationcontrolcircuit60(orcontrolmeans) outputs the control signal CS for controlling the oscillation frequency of the clock signal oscillator 116 with the output

data (i.e., the phase fluctuation data PS2 which are the sum of the offset value end cumulatively added date PSlof the phase fluctuation data PS of the pilot signals).

Figs. 4A and 4B are diagrams for explaining the phase errors which appear in the frequency components of the I-

channel demodulated date IR and the Q-channel demodulated data OR inputted to the clock signal regeneration circuit 130 of Fig. 3, when the frequency errors are in the clock signal generated in the clock signal oscillator il6 of Fig. 2.

Fig. 4A is a diagram illustrating the frequency components of the Ichannel demodulated data IR and the Q-

channel demodulated data QR, and Fig. 4B is a diagram illustrating the phase errors of the frequency components of the pilot signals in the Ichannel demodulated data IR and the Q-channeldemodulated data QRof the casein which the frequency errors are in the clock signals.

In Fig. 4A: SPO designate a pilot signal of the minimum frequency in one symbol; SP1 and SP2 designate pilot signals which are in the same symbol as that of the pilot signal SPO but have higher frequencies; and SP3 designate a pilot signal which has the highest frequency in the same symbol as that of the pilot signal SPO.

In Fig. 4B, numeral 91 designates a phase fluctuation (01 - 00) between the phase 00 of the pilot signal SPO of the minimum frequency and the phase 01 of the pilot signal SP1.

Numeral 92 designates the phase fluctuation (02 - 01) between the phase 01 of the pilot signal SP1 and the phase 02 of the pilot signal SP2, and numeral 93 designates the phase fluctuation (03 - 02) between the phase 02 of the pilot signal SP2 and the phase H3 of the pilot signal SP3.

On the other hand, numeral 94 designates en cumulatively added phase fluctuation 7(0f -0f-l) of the phase fluctuations 91 to 93 between the adjoining pilot signals in the common symbol. This cumulatively added phase fluctuation 94 coincides with the phase fluctuation from the pilot signal SP0 of the minimum frequency to the pilot signal SP3 of the maximum frequency in the common symbol.

Therefore,the phase fluctuation94 is equalto the phase fluctuation between the pilot signal of the minimum frequency and the pilot signal of the maximum frequency in the common symbol,when the phase fluctuations oftheindividualfrequency components of the adjoining pilot signals in the common symbol are to be cumulatively added for one symbol period.

Fig. 6 is a flow chart showing the actions of Embodiment 1. Of the Ichannel demodulated data IR and the Q-channel demodulated data QR outputted (at a demodulation step) from the FFT112 of the subcarrier frequency signaldemodulator120, the data of the subcarrier$ corresponding to the pilot signals

specified on the sending side are selectively outputted (at Step S1) to the selectors 30 and 40.

The demodulated data PIR of the pilot signals, as outputted from the selectors 30 and 40, are fed to the RAM 6 and the RAM 7. In this case, the RAM 6 stores the I-channel demodulated data PIRof the pilot signals, and the RAM 7 stores the Q-channel demodulated data PQR of the pilot signals.

Moreover,theRAM6 and the RAM7 latch the aforementioned stored data till the I-channel demodulated data PIR and the Q-channel demodulated data PQR corresponding to the next pilot signals are fed.

Specifically, the RAM 6 and the RAM 7 delay the stored I-channel demodulated data PIR and Q-channel demodulated data PQR for the time period corresponding to one interval for generating theindividualpilotsignals,and output the delayed data as the I-channel delayed demodulated data PdIR and the Q-channel delayed demodulated data PdQR (at Step S2: a delay step). On the other hand, the delayed demodulated data PdQR, as outputted from the RAM 7, are reversed in their plus and minussignsbythesignreversingcircuitl0,andareoutputted. The demodulated data PIR, the demodulated data PQR, the delayed demodulated data PdIR and the sign-reversed delayed demodulated data PdQR of the pilot signals are fed to the complex multiplier 11 and are subjected to the complex

multiplications. The computation result (or the multiplication result) of the complex multiplier 11 is outputted (at Step S3) as real component data RN and imaginary component data JN from the complex multiplier 11.

In the ROM 12, the arc tangent (arc tangent function) data corresponding to the real component data RN and the imaginary component data JN, as outputted from the complex multiplier ll, are read out. On the basis of those read data, the phase fluctuations PS between the adjoining pilot signals (which belong to the common symbol and adjoin each other) are computed and outputted (at Step S4: a phase fluctuation outputting step).

The cumulative adder 15 adds the individual phase fluctuation data PS between the adjoining pilot signals, as outputted from the ROM 12, in the common symbol (or in the identical symbol), cumulatively for one symbol period. When the cumulative addition of one symbol is ended, the cumulative addition result PSlis outputted toinitialize the cumulatively added value (at Step S5: a cumulative addition step).

The cumulative addition result, as outputted at each end of the processing of one symbol from the cumulative adder 15, is fed to the offset adder 16. This offset adder 16 outputs the offset addition data PS2, in which the offset valueis added to the cumulative addition result (at Step S6: an offset

addition step).

The offset addition data PS2 are fed to the loop filter 50, so that they are outputted as phase fluctuation data PS3, from which the unnecessary noise components are filtered out (at Step S7: a filter step).

The clock oscillation control circuit 60 detects the frequency error and the phase error of the clock signal from the phase fluctuation data PS3 or the cumulative addition result of the phase fluctuations of the individual pilot signals, as detected, in the common symbol. On the basis of the frequency error and the phase error of the clock signal, the clock oscillation control circuit 60 outputs the control signal CS for controlling the oscillation frequency of the clock signal oscillator 116 (at Step S8: a control step).

In this embodiment, as described above, the complex multiplication after the pilot signals were selected is executed to obtain the data having the phase fluctuations between the pilot signals adjoining in the common symbol, as a parameter.

In other words, this embodiment computes the phase fluctuations of the subcarrier frequency components corresponding to the pilot signals in the common symbol, as shown in Fig. 4B.

Even when the phases of the subcarriers between the individual symbols do not fluctuate, therefore, the phase

fluctuations due to the frequency errors and the phase errors of the clock signals can be detected to improve the drawing effect of the clock signals.

If it is assumed that the phase fluctuation 94 which has cumulatively accumulated the pilot signals in the common symbol from the pilot signal SPO of the minimum frequency to the pilot signal SP3 of the maximum frequency is exemplified by + 3, it is also conceivable not to cumulatively add but to compute the phase fluctuation 94.

However, the maximum of the phase fluctuations to be computed all at once by a computation circuit 13 is + 2. When the phase fluctuations of + 3 are computed all at once, the phase fluctuation of+xis falsely computed so that the correct phase fluctuation cannot be attained.

Generally, a number of pilot signals are in the symbol so that the phase fluctuations 91 to 93 between the adjoining pilot signals will-not exceed + 2. It is practically conceivable that the phase fluctuation 94 in the common symbol may exceed + 2, e.g., + 3.

In this ease where the frequency or phase of the sampling clock contains an error, the phase fluctuation occurs in the FFT output (although the fluctuation in the phase in one symbol depends upon the magnitude of the error of the frequency or phase). Intheconstructionofthisembodiment, ontheotherhand,

if the phase fluctuations 91 to 93 between the adjoining pilot signals are individually + 2x or less, the phase fluctuation 94 in the common symbol can be correctly computed by cumulatively adding the phase fluctuations 91 to 93 between the adjoining pilot signals for one symbol period, even if the total phase fluctuation 94 of the pilot signals in the common symbol from the pilot signal SP0 of the minimum frequency to the pilot signal SP3 of the maximum frequency is + 2x or more.

Moreover, the range for detecting the phase fluctuation 94 of the pilot signals in the common symbol from the pilot signal SP0 of the minimum frequency to the pilot signal SP3 of the highest frequency can be widened to + 2n or more.

(Addition of Offset Value) In this embodiment, on the other hand, it is conceivab e to add the offset value of the phase fluctuation SP which has been cumulatively added in the common symbol, as described hereinbefore. Figs. 5A, 5B and 5C are diagrams showing the relations among the effective symbolsignals intheOFDMsignal,theguard interval signals and the time windows for the discrete Fourier transformations. The OFDM signal has the guard interval signals on the time axis on the sending side. This is a device for enlarging the symbol length while considering the delay time of a delay wave estimated, without charging the frequency interval of the

subcarriers. As shown in Fig. 5, the guard interval signal in the OFDM signal is produced by copying the data of the trailing portion of the effective symbol signal on the time axis and by adding the copied data to the front of the effective symbol.

On the receiving side, the data of the guard interval portion, as imagined to cause the inter-sign interference by the delay wave, are ignored, and the time window for the OFDM demodulation is formed of the remaining data, so that the data within the range of the time window are subjected to the discrete Fourier transformation by the fast Fourier transformation circuit.

Where the frequency error and the phase error are not in the clock signals generated by the clock signal oscillator 116 of Fig. 2, the time window of the fast Fourier transformation is not dislocated. Where the frequency error and the phase error are caused in the clock signal by the detection errors of the phase fluctuation in the symbol, however, the time dislocation is caused in the time window.

The following two cases [1] and [2] are conceived for the dislocation of the time window.

[1] If the dislocation occurs forward of the time axis, the data of the guard interval are contained in the range of the time window so that the trailing data of the effective symbol are deleted (or the trailing data extrude from the time window

range so that they are not contained in the period of the time window). Ifthetimewindow is dislocated forward on the time axis, the data of the guard interval are contained in the range of the time window so that the trailing data of the effective symbol are deleted Since the guard interval is prepared by copying the trailing data of the effective symbol and by adding the copied data to the front of the effective symbol, so that the orthogonality can be retained between the subcarriers to be transformed.

In this case, the orthogonality is naturally broken between the subcarriers but can be equivalently retained between the suboarriers to be transformed, because the guard interval is made by copying the trailing data of the effective symbol and by adding the copied data to the front of the effective symbol [2] If the time window is dislocated backward on the time axis, the data at the front of the effective symbol are deleted from the range of the time window (or the data extrude from the range of the time window so that they are not contained in the period of the time window), but the data of the guard interval, as prepared by copying the data of the adjoining subsequent effective symbol and by adding the copied data, are contained. In this case, the data of the adjoining symbol take the

place of the intrinsic data, and the inter-sign interference occurs in the signals which have been subjected to the discrete Fourier transformation,so that a serious influence is exerted on the bit error percentage of the regenerated signals.

In order that the time window may not be dislocated to the trailing side on the time axis even if the frequency error and the phase error are left in the clock signals, therefore, an offset may be made to locate the time window at the position which is dislocated forward from the intrinsic position.

The time window is dislocated if the frequency error and the phase error are in the clock signals. In order to offset the time window, on the contrary, a constant offset value may be given to the phase of the regenerated clock signal. Here, this offset value may be selected to an arbitrary value (or an optimum value) according to the system.

In this embodiment,thecontrolsignalCS for controlling the oscillation frequency of the clock oscillator 116 is obtained from the result that the offset value is added to the cumulatively added phase fluctuation. As a result, the clock signal to be oscillated in the clock signal oscillator 116 is given a predetermined phase offset.

As aresult,the time windowis dislocated to the position containing the predetermined phase offset. Even where the frequency error end the phase error areleft in the crock signal, the time window can be dislocated within the adjoining symbol

to prevent the inter-sign interference thereby to improve the bit error percentage of the regenerated signal.

According to the embodiment thus far described, the phase fluctuation due to the frequency error and the phase error of the clock signals can be detected to enhance the drawing performance of the clock signals.

On the other hand, the phase fluctuation value between the adjoining pilot signals to be computed all at once is + 2, but the detection range of the phase fluctuation in the symbol can be widened by adding them cumulatively.

Since the pilot signals are numerously contained in the symbol, on the other hand, the phase fluctuation in the symbol can be computed highly precisely to raise the drawing rate and performance of the clock signals.

Embodiment 2 The foregoing Embodiment 1 has been described on the ease where the predetermined offset value is added to the cumulatively added symbol phase fluctuations.

InEmbodiment2, here will be described a receiver system for receiving the OFDM signal which can be transmitted by varying the length of an effective symbol (i.e., the effective symbol length) and the length of a guard interval length (i.e., the guard interval length), as in the OFDM transmission in the Japanese digital ground wave broadcasting standards. The

receiver system comprises offset changing means for changing the offset value to be added to the symbol phase fluctuation to be outputted by cumulative adder means for cumulatively adding the phase fluctuation in an identical symbol, in accordance with the effective symbol length and the guard interval length.

In the OFDM transmission of the Japanese digital ground wave broadcasting standards, for example, the subcarriers in one effective symbol can be transmitted by changing their numbers to three stages, and the guard intervals can also be transmitted by changing their lengths to several stages.

With a phase difference in the clock signals, the time window of the discrete Fourier transformation is dislocated.

Where the length of the transmission effective symbol (or the transmitted effective symbol) and the length of the guard interval are different, even if the clock signals have a phase error of the same magnitude, the ratio between the resultant dislocation of the time widow and the effective symbol length becomes different.

By dislocating the time window position of the discrete Fourier transformation on the time axis forward by a predetermined position from theintrinsicpositionras has been described in connection with Embodiment 1, the inter-sign interference can be made reluctant to occur, even where the clock signals have the frequency errors and the phase errors.

Embodiment 2 will be described on the construction in which the optimum time window for the individual effective symbollengthsandtheindividualquardintervallengths(i.e,, the positions of the optimum time window on the time axis) is obtained by making the dislocation (or the shift) of the time window of the discrete Fourier transformation on the time axis thelarger for thelarger effective symbol length and thelarger guardintervallength end the smeller for the smeller effective symbol length and the smaller guard interval length (or by setting the dislocation (or the shift) of the time window of the discrete Fourier transformation on the time axis adaptively according to the effective symbollength end the guard interval length). Fig. 7 is a block diagram showing a clock signal regeneration circuit according to Embodiment 2 of the invention. Here in a clock signal regeneration circuit 131 shown in Fig. 7, the portions for the same actions as those of the clock signal regeneration circuit 115 of the prior art shown

in Fig. 1 and the clock signal regeneration circuit 130 of Embodiment 1 shown in Fig. 3 will be omitted on their descriptions by designating them by the common numerals.

On the other hand, the construction of the OFDM receiver using the clock signal regeneration circuit 131 of Embodiment 2 of the invention is similar to the construction of Fig. 2

used inEmbodimentland corresponds to the portion of the crock signal regeneration circuit 130 in Embodiment 1.

The points where the clock signal regeneration circuit 131 of this embodiment shown in Fig. 7 and clock signal regeneration circuitl30OfEmbodimentlofFig.3 are different will be described in the following.

Specifically, the crock signal regeneration circuit 130 in Embodiment 1 is constructed to add a predetermined offset value to the cumulatively added phase fluctuation. However, the clock signal regeneration circuit 131 in Embodiment 2 is constructed to include: a symbol length deciding circuit (or symbol length deciding means) 17 for deciding the effective symbol length and the guard interval length; and an offset changing circuit 18 for changing the offset value to be added according to the decision result.

Here will be described the actions.

The symbol length deciding circuit 17 decides the effective symbol length and the guard interval length in the OFDM signal inputted, and outputs the decision result.

The offset changing circuit 18 changes the magnitude of the offset on the basis of the decision result outputted from the symbol length deciding circuit 17. The offset adder 16 feeds the loop filter 50 with the cumulative addition result PS2 which is obtained by adding the offset value given by the offset changing circuit 18, to the cumulative addition result

PSI of the symbol phase fluctuations.

The cumulative addition result PS2 of the symbol phase fluctuations, to which the offset value is added, is outputted es the phase fluctuations PS3, from which the unnecessary noise components (e.g., the signals of the adjoining channels) are filtered out by the loop filter 50.

As described above, the magnitude of the offset to be added is changed on the basis of the effective symbol length and the guard interval length. Therefore, the optimum location of the time window for the individualeffective symbol lengths and the individual guard interval lengths can be set so that the inter-sign interference is hardly caused to exert no influence on the bit error percentage of the regenerated signals. By changing the gain of the amplifier arbitrarily by the effective symbol length, the guard interval length, the differential modulator and the synchronous modulator, on the other hand, the errors of the clock signals and the control signals can be adjusted to a predetermined relation so that the crock signals can be drawn independently of the modulators and the symbol lengths.

Since the drawing performance of the clock signals can be enhanced, moreover, the disturbances by the inter-

subcarrier interferences can be suppressed to improve the characteristics of the bit error percentage of the regenerated

signals. By giving the offset value to the phases of the clock signals to dislocate the position of the time window of the discrete Fourier transformation forward by a predetermined position from the intrinsic position, on the other hand, the inter-sign interference is reluctant to occur thereby to exert an influence on the bit error percentage of the regenerated signals, even when the clock signals have the frequency errors and the phase errors.

Embodiment 3 In Embodiment 3, the cumulative addition results of the phase fluctuations, to which the offset value is added, as has been described in connection with Embodiment 2, are averaged over several symbols (or a plurality of symbols) and are then fed to the loop filter.

. Fig. 8 is a block diagram showing a clock signal regeneration circuit according to Embodiment 3 of the invention. Here in a clock signal regeneration circuit 132 shown in Fig. 8, the portions for the same actions as those of the clock signal regeneration circuit 115 shown in Fig. 1 and the clock signal regeneration circuit 130 of Embodiment shown in Fig. 3 will- be omitted on their descriptions by designating

them by the common numerals.

On the other hand, the construction of the OFDM receiver using the clock signal regeneration circuit 132 of Embodiment 3 is similar to that used in Embodiment 1 and shown in Fig. 2, and corresponds to the portion of the clock signal regeneration circuit 130 in Embodiment 1.

In Fig. 8, numeral 21 designates an averaging circuit for averaging the cumulative addition results PS2 of the phase fluctuations in the common symbol, to which the offset outputted from the offset adder 16 is added, over at least several symbols.

The cumulative addition result of the phase fluctuations, as averaged by the averaging circuit 21, is fed to the loop filter 50.

Here will be described the actions.

The aforementioned phase fluctuations PS contain the computation errors or the Gaussian noises, as might otherwise occur at their computations.

The cumulative addition results of the phase fluctuations of one symbol, as containing those computation errors, are inputted to the cumulative adder 15 so that they are averaged over at least several symbols.

By thus averaging the cumulative addition results over severalsymbolsor more,the computation errors or the Gaussian noises are filtered out so that the symbol phase fluctuations containing no error or such few errors as to exert no influence

upon the actions are fed to the loop filter 50.

By adopting the construction in which the computation errors or the Gaussian errors are filtered out by averaging the cumulative addition results over several symbols, as described above, it is possible to enhance the performance of drawing the clock signals.

Embodiment 4 InEmbodiment4, here willbe described a receiver system for receiving the OFDM signal which can be transmitted by varying the number of subcarriers in one effective symbol, as in the OFDM transmission in the Japanese digital ground wave broadcasting standards, The receiver system comprises a (loop) filter gain changing circuit (or filter gain changing means) for changing the gain of the loop filter 50, which filters the cumulative addition value PSI of the phase fluctuations in the common symbol, as cumulatively added by the cumulative adder 15, according to the length of the effective symbol or the length of the guard interval.

Fig. 9 is a block diagram showing a clock signal regeneration circuit according to Embodiment 4 of the invention. Here in clock signal regeneration circuit 133 shown in Fig. 9, the-portions for the same actions as those of the clock signal regeneration circuit 115 of the prior art shown in Fig.

1 and the clock signal regeneration circuit 130 of Embodiment 1 shown in Fig. 3 will be omitted on their descriptions by

designating them by the common numerals.

On the other hand, the construction of the OFDM receiver using the clock signal regeneration circuit 133 of Embodiment 4 is similar to that used in Embodiment 1 and shown in Fig. 2, and corresponds to the portion of the clock signal regeneration circuit 130 in Embodiment In Fig. 9, numeral 51 designates a loop filter gain changing circuit for changing the gain of the loop filter 50 according to the length of the effective symbol or the length of the guard interval.

Here will be described the actions.

Asymbollength decision circuitl9 decides the effective symbol length and the guard interval length in the OFDM signal inputted, and outputs its decision result.

In accordance with this decision result, the filter gain changing circuit 51 changes the filter gain of the loop filter 50. The phase fluctuations in the common symbol, as fed from the cumulative adder 15, are filtered out in the loop filter 50 with the gain set by the filter gain changing circuit 51, so that the they are outputted as the phase fluctuation data having the unnecessary noise components (e.g., the signals of the adjoining channels) filtered out.

In the OFDM transmissions according to the Japanese

digital ground wave broadcasting standards, forexample,there are specified three kinds of modes which are different in the number of subcarriers contained in one effective symbol.

Since the effective symbol lengths are different for the individual modes, the phase fluctuations in the common symbol are different among the individual modes even if the OFDM signals are regenerated with the clocksignals having the identical phase error.

For example, the phase fluctuations in the common symbol in mode 3, in which an effective symbol length of four times as large as that of mode 1, are larger than the phase fluctuations in the common symbol in mode 1 (that is, the phase fluctuations to occur for the effective symbol period are enlarged by the effective symbol length).

Thus, the relations of the control signals to the errors of the clock signals are different for the modes so that the drawing performances of the clock signals are not stabilized.

By changing the gain of the loop filter in accordance with the effective symbollength end the guard intervallength, therefore, the errors of the clock signals and the control signals of the crock signals can tee adjusted to a predetermined relation in all the modes so that the crock signals can tee drawn independently of the difference in the modes.

The invention may be embodied in other specific forms without departing from the spirit or essential parts thereof.

The above embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, all changes which come within

the meaning end range of equivalency of the claims are therefore intended to be embraced therein.

The entire disclosure of Japanese Patent Laid-Open No.

278212/2000 filed on September 13, 2000 including specification, claims, drawings and summary are incorporated

herein by reference in its entirety.

Claims

CLAIMS:

1. A clock signal regeneration system comprising: demodulation means for outputting a demodulated signal which is digitized with a clock signal of a predetermined frequency from a signal of a suboarrier frequency band, as obtained by demodulating an OFDM modulation signal for a main carrier frequency; delay means for delaying said demodulated signal outputted from said demodulation means, to output a delayed demodulated signal; phase fluctuation output means for outputting phase fluctuations between pilot signals, as contained in one symbol period of said OFDM modulated signal, on the basis of both said demodulated signal and said delayed modulated signal; and controlmeans for controlling the frequency of said clock signal on the basis of the output of said phase fluctuation output means.

2. A clock signal regeneration system according to Claim

1, further comprising: cumulative addition means for adding the outputs of said phase fluctuation output means cumulatively.

3. A clock signal regeneration system according to Claim

2, further comprising: offset addition means for adding an offset to the output of said cumulative addition means.

4. A clock signal regeneration system according to Claim 3, further comprising: symbol length decision means for deciding the effective symbollength and the guard interval length of the demodulated signal, wherein the magnitude of the offset is changed according to the output of said symbol length decision means.

5. A clock signal regeneration system according to Claim 3, wherein the outputs of said offset addition means are averaged over a plurality of symbols of the OFDM signal.

6. A clock signal regeneration system according to Claim 3, further comprising: filter means for filtering the output of said offset addition means.

7. A clock signal regeneration system according to Claim 6, further comprising: symbol length decision means for deciding the effective

symbol length and the guard interval length of the demodulated signal, wherein the magnitude of the filter gain is changed according to the output of said symbol length decision means.

8. A receiver system comprising: primary demodulation means for digitizing with a clock signal of a predetermined frequency from a signal of a subcarrier frequency band, as obtained by demodulating en OFDM modulation signal for a main carrier frequency; secondary demodulation means for outputting a demodulated signal for each channel on the basis of the output of said primary modulation means; phase correction means for correcting the phase of the demodulated signal of said secondary demodulation means; delay means for delaying the output of said phase correction means to output a delayed demodulated signal) phase fluctuation output means for outputting phase fluctuations between pilot signals, as contained in one symbol period of said OFDM modulated signal, on the basis of both said demodulated signal and said delayed demodulated signal; and controlmeans for controlling the frequency of said crock signal on the basis of the output of said phase fluctuation output means.

9. A receiver system according to Claim 8, further comprising: cumulative addition means for adding the outputs ofeaid phase fluctuation output means cumulatively.

10. A receiver system according to Claim 9, further comprising: offset addition means for adding an offset to the output of said cumulative addition means.

A receiver system according to Claim 10, further comprising: symbol length decision means for deciding the effective symbol length and the guard interval length of the demodulated signal, wherein the magnitude of the offset is changed according to the output of said symbol length decision means.

12. A receiver system according to Claim 10, wherein the outputs of said offset addition means are averaged over a plurality of symbols of the OFDM signal.

13. A receiver system according to Claim 10, further . comprising: filter means for filtering the output of said offset

addition means.

14. A receiver system according to Claim 13, further comprising: symbol length decision means for deciding the effective symbol length and the guard interval length of the demodulated signal, wherein the magnitude of the filter gain is changed according to the output of said symbol length decision means.

15. A clock signal regenerating method comprising: the demodulation step of outputting a demodulated signal which is digitized with a clock signal of a predetermined frequency from a signal of a subcarrier frequency band, as obtained by demodulating an OFDM modulation signal for a main carrier frequency; the delay step of delaying said demodulated signalobtained at said demodulation step, to obtain a delayed demodulated signal; the phase fluctuation output step of outputting phase fluctuations between pilot signals, as contained in one symbol period of said OFDM modulated signal, on the basis of both said demodulated signal and said delayed demodulated signal; and the control step of controlling the frequency of said clock signal on the basis of the output obtained at said phase

fluctuation output step.

16. A receiving method comprising: the primary demodulation step of digitizing with a clock signal of a predetermined frequency from a signal of a subcarrier frequency band. as obtained at demodulating an OFDM modulation signal for a main carrier frequency; the secondary demodulation step of outputting a demodulated signal for each channel on the basis of the output obtained at said primary modulation step; the phase correction step of correcting the phase of the demodulated signal obtained at said secondary demodulation step; the delay step of delaying the output obtained at said phase correction step to output a delayed demodulated signal; the phase fluctuation outputting step of outputting phase fluctuations between pilot signals, as contained in one symbol period of said OFDM modulated signal, on the basis of both said demodulated signal and said delayed demodulated signal; and the control step of controlling the frequency of said clock signal on the basis of the output obtained at said phase fluctuation output step.

17. A clock signal regeneration system substantially as hereinbefore described as an embodiment and as shown in the corresponding accompanying drawings.

18. A receiver system substantially as hereinbefore described as an embodiment and as shown in the corresponding accompanying drawings.

10

19. A clock regeneration, method substantially as hereinbefore described as an embodiment and as shown in the corresponding accompanying drawings.

20. A method of determining an error in a clock 15 signal used for demodulating an OFDM signal containing pilot subcarriers, in which the error is calculated from the difference between phase variations of different pilot subcarriers.