GB2364172A - Flip Chip Bonding Arrangement - Google Patents

Abstract

A flip-chip bonding arrangement for use with for example, a GaAs monolithic microwave integrated circuit (MMIC) 42, or an opto-electronic device, has one or more metal under-bump portions 44 attached to a first substrate 40. Corresponding bump portions 52 of an interconnecting metal are attached to the surface of the under bump portions 44 remote from the first substrate. The arrangement is characterised in that the sides of the under-bump portions are non-wettable by the interconnecting metal, and the height of the under-bump portion substantially determines the overall separation between the first and a second substrates when the two are bonded. The under bump portions 44 may be made from nickel or copper, and have a height of at least 10 žm, and of at most 100 žm. A method of providing a flip-chip bonding arrangement uses a seed layer, photoresist, under bumps and bumps formed in openings in the photoresist (Figures 5a-5g). A further method of bonding two substrates uses a plurality of solder bumps and contact means. A thin layer of gold is deposited on the solder bumps. Without the application of a flux, the temperature of the solder-bumps is raised so that a solder connection is made between the bumps and the contact means.

Description

2364172 FLIP-CHIP BONDING ARRANGEMENT The invention relates to a flip-chip

bonding arrangement, a flip-chip bonded circuit arrangement incorporating such a flip-chip bonding arrangement, a method for providing a flip-chip bonding arrangement and a method for the flip-chip bonding of two substrates.

Flip-chip bonding is one of a number of known methods of interconnecting two electronic components or circuits, another method being, for example, tape automated bonding Flip-chip bonding basically involves the application of an "under- bump" metal to the surface to be bonded and the subsequent application of a pillar or sphere of an "interconnect metal" (so-called "bumps") onto the under-bump metal One of the components may lack the bumps, in which case it is simply provided with bond pads for mating with the bumps on the other component Such a situation is shown in Figure 1, in which an electronic chip 10 is seen to be provided with an array of hemispherical bumps 12 on its mating side, while a substrate 14 on which the chip is to be mounted has a corresponding array of bonding pads 16 connected to respective interconnection tracks 18 The connection between the chip and the substrate is made either by heating so as to melt the interconnect metal of the bumps or by pressing the two components together to form a cold compression weld The former is termed "solder-bump bonding", whereas the latter is known as "indium-bump bonding", due to the common use of indium as the interconnect metal in that case.

Flip-chip technology is commonly used in the manufacture of, e g, pixel detector arrays, and in the attachment of ball-grid array (BGA) packages to printed-circuit boards (PC Bs) and, more recently, in the assembly and attachment of some forms of chip-scale package (CSP).

Flip-chip techniques lend themselves particularly well to applications requiring either a high density of interconnections (e g large optical arrays) or very low parasitic capacitance and inductance (e g microwave applications) With regard to microwave circuitry, above a frequency of around 1 OG Hz all the features of a microwave circuit must conform to exacting physical rules in order to function correctly For example, the spacing between two adjacent interconnects is critical in determining the impedance of the transmission line so formed A further difficulty with microwave circuitry is that the inductance of conventional wire and tape interconnects between components becomes progressively more difficult to accommodate by design as the frequency of operation increases The minimum practical wire or tape length simply presents too large a series inductance By comparison, flip-chip bump bonds are inherently short and squat and are thereby ideally suited for interconnects at microwave frequencies Specifically, the series inductance of a bump bond can be as much as a thousand times smaller than that of a ware or tape interconnect, making this technology indispensable for, for example, the recently released 77 G Hz automotive band and the 124 G Hz imaging band.

The active component of most microwave circuits is a gallium arsenide (Ga As) semiconductor chip, often in the form of a monolithic microwave integrated circuit (MMC) All of the active circuitry on an MIC is on one face of the chip, referred to as the top or active face or side An MMIC is designed to function with a substantial thickness of dry air or inert gas over the circuitry If an Mi IC is to be mounted on a substrate by flip-chip interconnection, this necessitates placing the chip upside down with its active face toward the substrate Therefore control of the standoff gap between the NMIC and the substrate is an essential prerequisite for successful operation at microwave frequencies As a general guide, this gap needs to be a minimum of 35 Pm and preferably much larger In traditional flip-chip solder interconnects the size of the gap is directly related to the volume and hence the diameter of the solder element used to make the interconnect There is therefore a conflict between the requirement for a minimum stand-off height and the need for a sufficiently small interconnect diameter at a given fixed spacing between interconnects (typically 5 Ojm) in order to achieve the desired electrical function.

US 4466635, as shown with reference to Figures 2 a-2 c, discloses an interconnect bump for flip-chip bonding which includes an integral stand-off The interconnect bump comprises a stand-off in the form of a cylindrical column 22 of copper which is bonded to a solder wettable metal pad 24 on a substrate 26 The pad 24 has a diameter greater than that of the column such that a peripheral portion 24 a extends laterally and externally of the cylindrical stand-off 26 A solder cap 28 is formed on an upper surface of the stand-off 22 and has a peripheral portion 28 a that extends laterally and externally of the stand-off During flip-chip bonding the solder cap 28 melts over and coats the outer surface of the stand-off (Figure 2 b) Due to surface tension the solder forms a generally hourglass shape over the outer surface of the stand-off as it bonds to the peripheral portion of the pad 24 and a corresponding solder wettable pad 30 on the device/circuit 32 being bonded Although such an interconnect bump provides a predetermined stand-off it requires a relatively large volume of interconnect metal to achieve stand-off distances of any size which in itself causes problems during bonding.

It has also been proposed in US 5508561 to use a spherical stand-off rather than a column Again solder flows over the outer surface of the stand-off during bonding.

According to the present invention a flip-chip bonding arrangement for bonding a first and second substrate comprises one or more metal under-bump portions attached to the first substrate and corresponding bump portions of an interconnecting metal attached to the surface of the under-bump portions remote to the first substrate, characterised in that sides of the under-bump portions are non-wettable by the interconnecting metal and wherein the height of the under-bump portion substantially determines the overall separation between the first and second substrates when the two are bonded.

Preferably the under-bump portions have a height of at least 1 Ogm and preferably a height of at most 10 Opm.

Advantageously the height of the bump portions is less than or equal to a width of the under-bump portions.

Preferably the first substrate comprises a tile Alternatively it can comprise an electronic device to be attached to a tile.

In a preferred arrangement the under-bump portions comprise a seed layer and an overlying layer, the overlying layer being metallurgically compatible with the seed layer and the bump layer Preferably the bump portions are a composition selected from a group consisting of lead/tin, gold/tin and indium.

According to second aspect of the invention a flip-chip bonded circuit arrangement comprises a flip-chip bonding arrangement as described above and an electronic device mounted to said tile by way of said flip-chip bonding arrangement.

Preferably the electronic device is a Ga As monolithic microwave integrated circuit or an opto-electronic device.

According to a further aspect of the invention a method for providing a flip-chip bonding arrangement on a substrate having one or more bond pads comprises the steps of:

a) depositing a seed layer of conductive metal on the substrate; b) depositing a layer of photoresist on the substrate; c) providing in the photoresist layer respective openings above the pads; d) depositing into the openings an under-bump layer which will adhere to the seed layer and also be metallurgically compatible with a bump layer to be applied; e) depositing into the openings and onto the under-bump metal the bump layer, and f) removing the excess photoresist and seed layers.

Advantageously step (d) and/or step (e) is achieved by way of an electroplating process.

Preferably the seed layer is composed of gold and the under-bump metal is selected from a group consisting of nickel, copper, gold and silver.

Advantageously a width dimension of the under-bump layer is substantially equal to that of its corresponding bond pad.

Advantageously the method further includes following step (f) and prior to mounting a second substrate on the bumps of the first substrate, a step (g): depositing a thin layer of gold onto the bump surfaces Preferably the thin layer of gold has a thickness less than that of the removed seed layer and advantageously has a thickness of between approximately 0 1 gum and 0 2 plm.

Advantageously the bumps are solder-bumps for solder-interconnection to the further substrate and the interconnection operation is performed without flux in an atmosphere denuded of oxygen and water vapour Preferably the atmosphere in which the interconnection operation is performed contains dry nitrogen Preferably the bump layer is deposited as at least two separate layers to form a multi-layer structure and, between steps (f) and (g), a flux is applied to the multi-layer structure, the layers are melted to create an alloy and flux residues are cleaned away.

According to yet a further aspect of the invention a method for the flipchip bonding of a first substrate to a second substrate, comprises the steps of:

(a) providing on the first substrate a plurality of solder-bumps and on the second substrate a corresponding plurality of contact means; (b) depositing on the solder-bumps a thin layer of gold; (c) bringing the solder-bumps of the first substrate into substantial alignment and into contact with the contact means of the second substrate, and (d) without the application of a flux to either the solder-bumps or the contact means, raising the temperature of the solder-bumps so that a solder interconnection is made between the bumps and the contact means.

An embodiment of the invention will now be described, by way of example only, with the aid of the drawings, of which:

Figure 1 illustrates the mating of a conventional flip-chip electronic device to a substrate; Figure 2 a-2 c are schematic sectional representations of a known flip- chip bonding process which includes an integral stand-off; Figure 3 a and 3 b are schematic sectional representations of a flip-chip bonding process in accordance with the invention; Figure 4 is a diagram showing part of an MMIC, and Figures 5 a-5 g depict the processing steps involved in manufacturing the under-bump portion and interconnect in accordance with the invention.

The basis of the present invention involves a fundamental reconsideration of the function of the under-bump metal and the interconnect metal In the conventional process, the under bump metal is not a single metal but a sequence of up to three metals.

The first metal is called the "adhesion metal" and its role is to provide an ohmic contact and strong physical bond to the surfaces to be joined The choice of adhesion metal varies with the nature of the components being joined and the method of deposition.

Common examples are titanium and chromium, if applied by a vapour phase technique, and zinc if applied by wet plating The second metal is the "barrier metal" that is included to prevent metallurgical reaction between the adhesion metal and the interconnect metal The choice of barrier metal is extremely wide and includes both pure elements such as platinum, nickel and copper and mixtures of metals like titanium- tungsten Finally, it is common practice to complete the under-bump metal with a "sacrificial metal" (often gold) which serves to improve shelf-life and wetting and/or aid visual inspection.

Conventionally also, the under-bump metal is always thin, most usually less than 1 Im thick In conventional flip-chip bonding it is the interconnect metal applied on top of the under-bump metal that provides the stand-off height through being made sufficiently thick The present invention substantially increases the thickness (i e height above the surface of the substrate) of the under-bump portion to as much as l O Ojim and applies only a small (relative to the conventional arrangement) thickness of interconnect metal on top By this means, the stand-off gap is mostly provided by the thick under-bump metal, while the interconnect diameter and pitch can be independently optimised by the geometry of the interconnect metal.

Referring to Figures 3 a and 3 b there is shown a flip-chip bonding arrangement in accordance with the invention for bonding and interconnecting a substrate 40 to a MMIC 42 The bonding arrangement comprises a cylindrical metal under-bump 44 which comprises in order from the surface of the substrate 40, an adhesion metal layer 46, a metal barrier layer 48 and a sacrificial metal layer 50 The barrier layer 48 is much thicker than the other two layers 46, 50 and is made of a material which is not wettable by the interconnect metal On an upper surface of the under-bump 44 there is provided an interconnect metal bump 52 which is typically generally hemispherical in shape The barrier layer 48, which will hereinafter be referred to as spacing metal, substantially determines the stand-off gap between the substrate 40 and MMIC 42 when the two are bonded It is to be noted that the volume of the interconnect metal bump 52 is selected such that when the substrate 40 and MMNIC 42 are bonded together (Figure 3 b) there is sufficient to provide a good bond between the sacrificial layer 50 a corresponding wettable pad 54 though as will be seen from the Figure the stand-off is primarily determined by the height of the layer 48 It should be further noted that since the spacing member is made of a material which is non wettable there is no flow of the interconnect metal down the sides of the under-bump 44.

The use of a thick metal under-bump which is non-wettable on its sides requires a different method of application to achieve the desired result with high yield at low cost.

An embodiment of the process is now described.

A typical implementation of the process is the attachment of a Ga As MMIC to an alumina tile The Ga As MMIC (see Figure 4) will have two types of track, namely RF tracks (ground-signal-ground) 60 and DC tracks (power-line and bias) 62 (Only two of the latter type are shown) These tracks terminate in respective exposed gold bond pads 64 which are suitable for wire bonding In order that standard MMI Cs can be used, the bumps on the tile are positioned so as to mate with the pads 64 on the MMIC The RF pads are typically l O Ogm square on a 150 pm pitch for the ground-signal- ground microwave connections The alumina tile (not shown in Figure 4) will have a polished surface onto which have been deposited gold tracks to route microwave signals, power and control lines to the MMIC These are all industry-standard presentations The interconnect process to be described can in fact be applied to any substrate, including silicon wafers with standard aluminium bond pads, provided that the bond pads are converted to expose a gold finish This is dealt with later Suffice it to say that many methods are available for achieving this and are known to those skilled in the art.

In the preferred realisation of the invention the under-bump and interconnect metals are applied to the alumina (A 1203) tile rather than to the MIMC, for reasons that will be elaborated upon later Thus this realisation is the opposite of the more conventional arrangement of Figure 1, in which the electronic chip module 10 has the bumps 12 and the substrate 14 has the exposed contact pads 16 Referring now to Figure 5 a, a thin layer of conductive metal 70, the "seed metal", is first deposited over the entire tile 72.

Gold (Au) is the preferred choice for the seed metal as it will form a homogeneous bond with the existing gold tracks 74 and pads 76 This gold layer 70 needs to be of just sufficient thickness to ensure uniform current distribution during the following electroplating processes Methods for calculating a suitable thickness are well established and will not be elaborated here The gold layer 70 will likely be in the region of O 5 ugm thick and is preferably deposited by a vapour phase method.

A thick layer of photoresist 78 (see Figure Sb) is then applied to the tile 72 and is exposed and developed in accordance with the manufacturers' directions The objective of this process step is to coat the surface of the tile with an inert material that has near- vertical openings 80 through to the gold layer at desired locations, e g over the pad 76 connected to the track 74 The location of the openings 80 (only one is shown in Figures S Sb-Se) will mirror the openings of the bond pads on the MMIC (not shown) The depth of the openings (i e the thickness of the photoresist) must exceed the combined height of the under-bump metal and interconnect metal The diameter of the openings will fix the diameter of the under-bump metal and will also have an influence on the diameter of the final interconnects, as will be explained shortly.

Nickel, copper or other metallurgically compatible metal 82 is then deposited by electroplating down the openings 80 using commercially available chemical solutions (Figure Sc) This "spacing" metal 80 is ideally selected to provide the dual functions of the adhesion metal and the barrier metal but, if necessary, layers of different metals can be used to perform the required functions Nickel is a good first choice as it is compatible with the lead/tin and gold/tin solders commonly used as well as with indium interconnects The thickness of the spacing metal 80 should be such as to provide a significant proportion of the overall desired stand-off height, and preferably the majority of it, the remainder being provided by the thickness of the interconnect metal that will be deposited next.

On top of the spacing metal 82 there is then deposited the interconnect metal which in Figures Sd and Se comprises a layer 84 of gold followed by a layer 86 of tin (Sn) The interconnect metal is preferably deposited by electroplating, though other methods may be employed, such as thermal evaporation Lead/tin solder and indium can be deposited from a single plating solution as a single layer, whereas other solders must be deposited as a bi or tri-layer of the constituent elements The relative thicknesses of gold 84 and tin 86 are selected so that, on melting, the composition of the melt conforms to the required 80 wt% gold 20 wt% tin eutectic composition Because the gold/tin solder is metallurgically compatible with the gold bond pads on MMI Cs, this solder is the preferred choice for flip-chip solder interconnection of microwave components Indium is the preferred choice for flip-chip compression interconnection for the same reason.

The photoresist 78 and gold seed 70 layers are then removed (Figure Sf) using standard chemical treatments As is described in detail below the alumina tile 72 is then heat treated such that the one or more interconnect metal layers 84, 86 melt to form an interconnect metal bump 52 on the upper surface of the spacing metal 82 (Figure 5 g).

It will be appreciated that the overall thickness of the interconnect metal layer/s 46, 48 determines the volume and so height of the interconnect solder or compression bump 52 In the case of a volume of interconnect metal which is greater than that of a hemisphere of diameter corresponding to that of the spacing member, the interconnect bump will have a height and diameter which exceeds the spacing member In order to preserve the entire interconnect to as near a uniform pillar as possible, the diameter of the spacing metal should ideally match the diameter of the bond pad on the MIC and the thickness of the interconnect metal layer/s should not exceed this dimension For solder interconnects, this is the optimum thickness, as it maximises the surface-area-to- volume ratio However, the spacing metal 82 can be arranged to be of larger or even smaller diameter than the bump, if desired, although if it is too small, the mechanical stability of the structure is compromised For compression bonds, the interconnect metal should be as thin as possible, compatible with process requirements, in order to minimise lateral spread of the interconnect beyond the profile of the spacing metal when bonding occurs.

It will be appreciated that by virtue of the present inventive process a set of interconnects 44 (i e interconnect bumps 84, 86 plus spacing metal 82) are provided which are taller and narrower than usual and consequently exhibit a superior microwave performance Flip-chip interconnection of the MMIC to the alumina tile can then be made in the conventional manner A particular advantage of the interconnect arrangement of the present invention is that the stand-off is substantially determined by the spacing metal portion of the under-bump and is largely independent of the volume of the solder bump.

In order to convert a bi-layer deposit of gold and tin to a eutectic mixture with a melting point of 280 TC, it must be flash-heated to a minimum temperature of 419 TC This step, which takes place after the stage shown in Figure 5 f, is necessary to destabilise the congruently melting Au Sn intermetallic compound that would otherwise prevent the reaction from proceeding to completion in an acceptable timescale Exposure of a Ga As MIC to this temperature would be highly undesirable and it is for this reason that the spacing metal 82 and interconnect metal 84, 86 are preferably applied to the alumina tile rather than to the MMIC In addition, the MTIC bond pads are surrounded by an anti scratch coating which acts to constrain the solder interconnect on the substrate to the NMIC bond pad If the interconnect metal were applied to the MMIC, then a solder stop would have to be applied to the alumina tile and this would require an additional process step for that component, which would increase cost Hence the alumina tile is the preferred component for the application of the spacing and interconnect metals An advantageous spin-off of this is that completely standard MM Cs can be used, rather than ones which have to be specially processed.

On account of the general incompatibility between Ga As MMI Cs and the fluxes that are normally essential to effect flip-chip soldering, it is desirable to provide a soldering process that does not involve flux agents The processing method hereinbefore described lends itself to a modification that permits the subsequent flip-chip process to be fluxless.

The novel technique herein proposed is to take the alumina tile and, immediately after removal of the photoresist and gold seed layer, coat all metallic surfaces with a thin layer of gold This is simply achieved using a standard immersion plating process By the nature of the plating process, the gold deposit is essentially self- limiting in thickness (typically not exceeding 0 1 pgm thick) This additional gold forms a homogeneous bond with all the exposed gold tracks On the solder-bump this newly applied gold, due to the noble character of this element, restricts contact between the solder and air and thereby greatly diminishes the oxidation that can occur The reduction in the propensity for oxidation is such that flip-chip interconnects can be formed without flux for up to three months after fabrication of the alumina tile When the solder is melted to form the interconnect, the gold completely and rapidly dissolves in the solder This means that the joint is best made in an atmosphere denuded of oxygen and water vapour A suitable atmosphere is dry nitrogen of industrial quality.

In the case of the gold/tin and other multi-layer solders, which must first be melted to create the alloy, fusion is performed using flux to prevent the formation of an oxide skin The flux residues are then removed using standard treatments and the solder- bumps coated with gold before use, as described in the last paragraph.

Where the substrate on which the spacing metal and interconnect metal are to be applied does not already have gold bond pads, e g it may have aluminium pads, it will be necessary to make a conversion to gold This may be done using a conventional under- bump metal process as described earlier and would involve, firstly, applying a photolithographic mask to the substrate with a pattern corresponding to that of the bond- pad layout; secondly, depositing a layer of titanium, followed by a layer of platinum, finally followed by a layer of gold, all of which are preferably carried out using the vapour-phase technique Finally, the mask is removed, leaving a substrate which can be processed as described above to produce the required spacing and interconnect-metal thicknesses.

It should be appreciated that the invention is not restricted to the bonding of NMI Cs to substrates Other electronic devices may be bonded as well, including optical devices It is, however, necessary that the devices have bond pads finished in a metal for which a compatible seed is available.

Claims (24)

1 Flip-chip bonding arrangement for bonding a first and second substrate comprising one or more metal under-bump portions attached to the first substrate and corresponding bump portions of an interconnecting metal attached to the surface of the under-bump portions remote to the first substrate, characterised in that sides of the under-bump portions are non-wettable by the interconnecting metal and wherein the height of the under-bump portion substantially determines the overall separation between the first and second substrates when the two are bonded.

2 Arrangement according to Claim 1, wherein the under-bump portions have a height of at least 1 Oum.

3 Arrangement according to Claim 2, wherein the under-bump portions have a height of at most 100 Jim.

4 Arrangement according to any one of the preceding claims, wherein a height of the bump portions is less than or equal to a width of the under-bump portions.

Arrangement according to any one of the preceding claims, wherein the first substrate comprises a tile.

6 Arrangement according to any one of Claims 1 to 4, wherein the first substrate comprises an electronic device to be attached to a tile.

7 Arrangement according to any one of the preceding claims, wherein the under- bump portions comprise a seed layer and an overlying layer, the overlying layer being metallurgically compatible with the seed layer and the bump layer.

8 Arrangement according to any one of the preceding claims, wherein the bump portions are a composition selected from a group consisting of lead/tin, gold/tin and indium.

9 Flip-chip bonded circuit arrangement, comprising a flip-chip bonding arrangement as claimed in Claim 6 and an electronic device mounted to said tile by way of said flip-chip bonding arrangement.

Circuit arrangement according to Claim 9, wherein the electronic device is a Ga As monolithic microwave integrated circuit.

11 Circuit arrangement according to Claim 9 or Claim 10, wherein the electronic device is an opto-electronic device.

12 Method for providing a flip-chip bonding arrangement on a substrate having one or more bond pads, comprising the steps of:(a) depositing a seed layer of conductive metal on the substrate;(b) depositing a layer of photoresist on the substrate;(c) providing in the photoresist layer respective openings above the pads; (d) depositing into the openings an under-bump layer which will adhere to the seed layer and also be metallurgically compatible with a bump layer to be applied; (e) depositing into the openings and onto the under-bump metal the bump layer, and (f) removing the excess photoresist and seed layers.

13 Method according to Claim 12, wherein step (d) and/or step (e) is achieved by way of an electroplating process.

14 Method according to Claim 12 or Claim 13, wherein the seed layer is composed of gold.

Method according to any one of Claims 12 to 14, wherein the under-bump metal is selected from a group consisting of nickel, copper, gold and silver.

16 Method according to any one of Claims 12 to 15, wherein a width dimension of the under-bump layer is substantially equal to that of its corresponding bond pad.

17 Method according to any one of Claims 12 to 16, including, following step (f) and prior to mounting a second substrate on the bumps of the first substrate, a step (g):

depositing a thin layer of gold onto the bump surfaces.

18 Method according to Claim 17, wherein the thin layer of gold has a thickness less than that of the removed seed layer.

19 Method according to Claim 18, wherein the thin layer of gold has a maximum thickness of approximately O 2 pm.

Method according to any one of Claims 17 to 29, wherein the bumps are solder- bumps for solder-interconnection to the further substrate and the interconnection operation is performed without flux in an atmosphere denuded of oxygen and water vapour.

21 Method according to Claim 20, wherein the atmosphere in which the interconnection operation is performed contains dry nitrogen.

22 Method according to any one of Claims 17 to 21, wherein the bump layer is deposited as at least two separate layers to form a multi-layer structure and, between steps (f) and (g), a flux is applied to the multi-layer structure, the layers are melted to create an alloy and flux residues are cleaned away.

23 Method for the flip-chip bonding of a first substrate to a second substrate, comprising the steps of: (a) providing on the first substrate a plurality of solder- bumps and on the second substrate a corresponding plurality of contact means; (b) depositing on the solder-bumps a thin layer of gold; (c) bringing the solder-bumps of the first substrate into substantial alignment and into contact with the contact means of the second substrate, and (d) without the application of a flux to either the solder-bumps or the contact means, raising the temperature of the solderbumps so that a solder interconnection is made between the bumps and the contact means.

24 Method for providing a flip-chip bonding arrangement on a substrate having one or more bond pads, substantially as shown in, or substantially as hereinbefore described with reference to, Figures 3 a and 3 b or Figures 5 a-5 g of the accompanying drawings.