GB2362790A

GB2362790A - Time tracking a pilot signal

Info

Publication number: GB2362790A
Application number: GB0012402A
Authority: GB
Inventors: Menkang Peng; Lewis Antony Balfour
Original assignee: Telefonaktiebolaget LM Ericsson AB
Current assignee: Telefonaktiebolaget LM Ericsson AB
Priority date: 2000-05-22
Filing date: 2000-05-22
Publication date: 2001-11-28
Anticipated expiration: 2020-05-22
Also published as: GB2362790B; GB0012402D0

Abstract

A method of synchronizing an acquired pilot signal of a digital spread spectrum signal with a reference pseudo-noise signal. The method comprising receiving an input signal, obtaining a plurality of samples of the input signal, and outputting samples of the input signal. An additional sample is inserted into the output samples if the received signal is early with respect to the reference PN signal but a sample is deleted from the output samples if the received signal is late with respect to the reference signal. Time tracking means, comprising an early correlator and a late correlator, are used to determine if the received signal is early or late. The method can reduce the required data storage area compared to known techniques.

Description

2362790 RADIO FREQUENCY RECEIVERS The present invention relates to radio

frequency receivers, and in particular to radio frequency receivers for use in a code division multiple access (CDMA) telecommunications system using pilot signal synchronization.

BACKGROUND OF THE PRESENT INVENTION is Digital spread spectrum telecommunications systems, for example code division multiple access (CDMA) telecommunications systems, use pilot signals to determine the timing of an incoming signal to a receiver in order to enable correct reception of that incoming signal. The pilot signal must first be acquired, and then must be time tracked to ensure that the incoming signal is correctly received. Acquisition and time tracking are described, for example, in "Digital Communication" by Proakis, McGraw Hill third edition 1995. Acquisition generally includes comparing the received signal with a known pilot signal in order to determine where in the received signal the pilot signal occurs, and hence the relative timing of the received signal. When the timing of the pilot signal has been determined it is then necessary to track any small variations in the timing of that received signal so that synchronization with the received signal can be maintained. In previously considered systems, and such as that described in the book mentioned above, a delay lock loop (DLL) is used to maintain the receiver pilot code generator in synchronism with the received pilot signal. Alternatively, a so-called tau-dither loop (TDL) can be used to maintain time tracking of the acquired pilot signal.

However, such conventional methods require data storage buffers to be provided in the receiving station which can result in the relatively large amount of data storage being required. This is obviously undesirable, particularly in a mobile receiving station. Accordingly, it is desirable to provide a method of time tracking the acquired pilot signal that does not require the use of large buffer storage areas.

SUMMARY OF THE PRESENT INVENTION

According to one aspect of the present invention, there is provided a method of time tracking an acquired pilot signal in a digital spread spectrum telecommunications system, the method comprising receiving an input signal, obtaining a plurality of samples of the input signal, and outputting samples of the input signal, characterised by inserting an additional sample into the output samples if the received signal is early with reference a reference signal, and deleting a sample from the output samples if the received signal is late with respect to the reference signal.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a block diagram illustrating a time tracking device embodying the present invention; and Figure 2 illustrates one possible implementation of parts of the device of Figure 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Figure 1 illustrates an embodiment of the present invention which includes a sample collection unit 1, a sample processing unit 2, and a sample decimation unit 3. The sample collection and processing unit 1 and 2 are controlled by a time tracking unit 4.

is The time tracking unit 4 aims to provide a measure of chip timing change. Chip timing can be assumed to change slowly with respect to the sample timing, and the time tracking unit operates to detect the timing drift, its direction and whether it is large enough to require a timing adjustment. Timing adjustments are made by the sample collection and processing units 1 and 2. The time tracking unit 4 provides closed loop control which ensures that slow changes in received chip timing are tracked, thereby maintaining synchronisation with chip timing. Time tracking can be performed using DLL or TDL as described above, for example.

The tracking unit 4 operates assuming that initial synchronisation has already been gained with an input PN sequence. Two correlation outputs are calculated and are used to determine whether to output a "retard", "advance,, or "normal" control signal to the units 1 and 2. The calculation is made once every I'LI1PN code chip periods, as described below.

A locally generated version of the PN sequence is correlated with the sequence of samples that is M samples before that expected to be synchronised with the PN sequence. This correlation gives an early correlator output as given by:

Early correlator output = L-1 1 1PiV(y). Sample ((Ry + S) - M)j Y = 0 2 is -4 The locally generated version of the PN sequence is correlated with the sequence of samples that is M samples after that expected to be synchronised with the PN sequence. This correlation gives a late correlator output as given by:

Late correlator output = L-1 E PN(y). Sample ((Ry + S) + Y = 0 In the expressions for the early and late correlation outputs, L is a number of PN chips, chosen to be large enough to provide sufficient Signal to Noise ratio for the correlation outputs, but small enough to allow time tracking of the maximum expected rate of timing drift; PN(y) is element y of the PN sequence; R is the number of samples per chip; S is the sample number, within the R samples for a chip, which is expected to be synchronised with the PN sequence; Samples (Ry+S) are therefore the samples which are expected to be synchronised with the PN sequence, and Inj ref ers to the magnitude of n.

If the ratio of the early correlator output to late correlator output is greater than a first threshold value, then a "retard" control signal is output.

If the ratio of the late correlator output to early correlator output is greater than the first threshold value, then an "advance" control signal is output.

If the ratio of the early carrelator output to late correlator output is not greater than the first threshold value and the ratio of late correlator output to early correlator output is not greater than the first threshold value, then a "normal" control signal is output.

In one particular embodiment, the time tracking unit 4 generates one "advance", "retard" or "normal" signal per I'Ll' PN chip period. For the remainder of the 11LI1PN chip period the "normal" signal will be output.

In the following example, R=8, S=4 and M=4 so a "normal" condition utilizes sets of eight samples. It will be readily appreciated that these numbers are arbitrarily chosen to optimise the performance of the DLL in the telecommunications system in which the invention is utilised.

The sample collection unit 1 is responsive to the control signal output by the tracking unit 4. The control signal determines how many samples are collected and passed by the collection unit 1 to the processing unit 2. When a "normal" control signal is received the collection unit 1 passes 8 samples to the processing unit 2. A "retard" control signal causes the collection unit to pass 7 samples to the processing unit 2, and an "advance" control signal causes 9 samples to be passed to the processing unit 2.

The sample processing unit 2 accepts the set of 7, 8 or 9 samples and passes 8 samples forward to the decimator unit 3. If 7 samples are input then the last sample from the previous 8 samples will be reused together with the 7 new ones and passed forward. If 8 samples are input from block 1 then these are passed unaltered to block 3. If 9 samples are input from block 1 then only the first of the 9 samples is discarded and the last 8 samples are passed forward.

Figure 2 illustrates a shift register implementation of the collection and processing units 1 and 2.

is In a "retard" mode, seven samples are clocked into the Shift register s(n- 6) to s(n). Then the 8 samples currently in the register are given as the output to be used as the input to the decimation block 3. Since only seven new samples are shifted into the shift.register, the last sample of the previous set (s(n-7)) is passed to the decimation unit 3 for a second time. The eight samples are passed in parallel to the decimation unit 3.

In an "advance" mode, nine new samples are clocked into the Shift register s(n-8) to s(n). As the shift register is only 8 samples long the first sample (i.e. s(n-8)) is discarded. The 8 samples in the register are given as the output to be used as the input to the decimation block 3. In this case the previous set of 8 samples passed to the decimation block were s(n-16) to s(n-9) and the new set are s(n-7) to s(n), losing s(n8).

In a "normal" mode, eight new samples are clocked into Shift register s(n7) to s(n). These 8 samples are then passed to the decimation block unchanged.

The sample decimation unit 3 takes 8 samples from -7 the processing unit 2 and passes one sample forward to be used by the receiver/demodulator and two to the time tracking unit 4. The sample passed to the receiver will be that synchronised to the PN sequence and those passed to the tracking unit 4 will be those samples that are M samples before and after that synchronised to the PN sequence. The decimation unit 3 operates to output the sample which is time adjusted by the other units in the apparatus.

It will be readily appreciated that the "normal" number of samples (eight in the example embodiment) can be any required number. For example, four samples can be the normal case, with three and five samples then representing the retard and advance cases respectively. The invention is not restricted by the number of samples used.

Claims

CLAIMS:

is A method of time tracking an acquired pilot signal in a digital spread spectrum telecommunications system, the method comprising receiving an input signal, obtaining a plurality of samples of the input signal, and outputting samples of the input signal, characterised by inserting an additional sample into the output samples if the received signal is early with reference to a reference signal, and deleting a sample from the output samples if the received signal is late with respect to the reference signal.
2. A method as claimed in claim 1, wherein the input samples are clocked into a shift register of predetermined length, the insertion and deletion of output samples being achieved by clocking one fewer or one extra sample into the shift register respectively.
3. A device for time tracking an acquired pilot signal in a digital spread spectrum telecommunications system, the device comprising a sample collection unit operable to receive an input signal and to output a predetermined number of input signal samples, a sample processing unit which is operable to receive samples from the sample collection unit and is operable to process the samples on the basis of a received time tracking signal, characterised in that the sample processing unit outputs an additional sample if the received signal is indicated to be ear ly with reference to a reference signal, and deletes a sample from the output samples if the received signal is late with respect to the reference signal.
4. A device as claimed in claim 3, wherein the sample collection unit and the sample processing unit are provided with a shift register having a predetermined number of entries.
5. A device as claimed in claim 3 or 4, further comprising a sample decimation unit which is operable to extract two samples from the output samples for provision to a time tracking unit, and to extract a further sample for transfer to a demodulation unit.
6. A device as claimed in claim 5, comprising a time tracking unit for receiving selected samples from the sample decimation unit for outputting the time tracking signals.