This object is achieved by the invention by means of a circuit
configuration with the features of Claim 1. A procedure for detecting control states of at least one operating means is given in Claim 9.
In this case, any change to the control state of one or more switches is monitored so that an operator error, such as a door which inadvertently remains open for a long time and after whose closure a change in the control state of the door contact takes place, generates a wake-up signal. A wake-up signal can also be generated if despite proper closure of the door the door contact remains stuck in its previous control state (open door) and is released by re-actuation, so that door closure is signalled.
According to one embodiment of the invention, the wake-up signal can be generated by a change in the control state of at least two switches independent of each other. In this way it can be guaranteed that even in the event of complete failure or permanent malfunction of a switch, a wake-up signal can be reliably generated as before.
3 According to the invention, the closedcircuit current in sleep mode is limited to a value of almost zero. In the active mode, a switched or pulsed power supply can be used instead of a permanent power supply, to save power and adv antageously reduce the power consumption.
This advantageous effect also occurs without monitoring any change in the control state of at least one switch, but in the following is described only within the context of such a circuit configuration. It is also conceivable to limit the power consumption of a conventional circuit configuration to almost zero in a sleep mode in a corresponding manner.
Further advantageous embodiments of the invention are given in the subclaims.
The invention is further explained in the following using the examples shown in the drawings. The drawing are as follows.
Fig. 1 A block diagram showing the general functioning of a circuit configuration in accordance with the invention.
Fig. 2 A circuit diagram of the circuit configuration for realisation of a block diagram in accordance with Fig. 1.
Fig. 3 A schematic signal flow diagram of the signal path in a circuit according to Fig. 2. - The circuit configuration in accordance with Fig. 1 has two pulse shapers 11 and 12 and ajunction D1 for monitoring input signals Xl, X2 and X3. Signals X I, X2 and X3 are present independent of each other at the inputs of junction D 1, which outputs any change of input signal X 1, X2 or X3 as signal Xe.
The output of junction D I is connected to both inputs of pulse shapers I I and 12, so that signal Xe is present both at the input of pulse shaper 11 and also the 4 input of pulse shaper 12. Pulse shaper 11 then converts a rising edge to a defined impulse and pulse shaper 12 converts a falling edge to an impulse corresponding to the impulse of II, i.e. to a positive impulse Xpl, Xp2 as shown in the drawing.
This positive impulse Xp I and Xp2 is combined in each case in OR gate D2 to form signal Y, i.e. the wake-up impulse. Naturally, instead of using two pulse shapers 11 and 12 and combining their outputs by means of gate D2, this function can be described in an equivalent manner as an equivalent circuit diagram with only one pulse shaper which converts a positive or a negative edge in each case into an impulse of the same shape.
According to the invention, input signals Xl, X2 and X3 are generated by a change in the control state of an operating means, as described in the following. Naturally, the number of input signals is not limited to X I to X3, so that, depending on the requirements and application, any number of input signals can be combined by D1 to form signal Xe without additional pulse shapers being necessary for the purpose.
Fig. 2 shows the realisation of the block diagram in accordance with Fig. 1 as a circuit diagram.
At input X l, the circuit configuration has a switch S I, one side of which is connected to ground and the other side of which is connected at point 1 with both cathodes of decoupling diodes D12 and D13. The anode side of diode D 12 is connected to one side of a capacitor at point 1' and at the same time via resistor R1 2 to a power supply, e.g. 12 V. The other side of capacitor Cl 1 is connected as point 1 - via resistor RO 1 with the + 12 V power supply and at the same time with point 2" of one side of capacitor C21, a collector of an NPN transistor TO 1 and, via base resistor R02, to the base of PNP transistor T02.
The emitter side of transistor T01 is connected to ground and the emitter side of transistor T02 is connected to the +12 V power supply. The collector of T02 forms the output for output signal Y, with this collector being connected to ground via resistor R03. At input X2, the circuit configuration has a switch S2 one side of which is connected to ground, and the other to point 2... and is connected at point 2 with both cathodes of diodes D22 and D23.
The anode side of diode D22 at point 2' is connected to the side of capacitor C21 opposite point 2" and at the same time via resistor R22 to the +12 V power supply. This means that R01 provides the resistance via which capacitors C11 and C21 respectively are charged, and R12 provides the discharge resistance for C11 and resistor R22 the discharge resistance for capacitor C2 1. Switch S2 is connected via point 2... with one side of capacitor C22, the other side of which is connected to the base of transistor TO I via resistor R26. This base is in turn connected to ground via resistor R27.
At input X3, the circuit configuration has a switch S3, one side of which is connected to the + 12 V power supply and the other side, at point 3, to one side of capacitor C32, and at the same time to ground via resistor R3 1. The other side of capacitor C32 is connected via resistor R32, the same as R26 and R27, with the base of transistor TO 1.
The function of this circuit configuration, shown in Fig. 2, is explained in the following using the signal flow diagram shown in Fig. 3.
Input signals XI and X2 are configured as switches which connect to ground when closed, so that when switch 1 is closed a negative edge is produced at the junction of the cathodes of D12 and D13, and when the switch is opened a positive edge is generated as signal X1. In a similar manner, signal X2 is generated at junction 2 of cathodes D22 and D23. The switch for input signal 6 X3 is, on the contrary, is designed as a switch which when closed connects to MGH, e.g. +12 V, so that its closure generates a positive edge at point 3 and its opening a negative edge.
If the switch for X2 is closed to ground, e.g. by actuation of the door contact when the door is opened, a negative edge is produced at points 2 and 2' in accordance with signal 2a in Fig. 3, which via the capacitor is differentiated to a negative Dirac impulse 2a2. This negative Dirac impulse is applied via base resistor R02 to the base of the PNP transistor T02 and switches this on, until capacitor C21 through its charging restricts the current to a level such that at point 2" a value greater than the threshold value of transistor T02 is created and the transistor again switches off. The charge time is in this case determined essentially by RC element RO I -C2 1, because the current flow via the emitter of transistor T02 to its base is comparatively low through base resistor R02. The switching on and off of transistor T02 generates a positive impulse 2a3 at output Y, Fig. 3, which is normally connected to ground via R03.
If the switch at X2 remains closed for a longer time, points 2 and 2' remain LOW (ground), as previously described, and point 2" goes to + 12 V when the charging of C21 is completed. If the switch at X2 is now reopened, this brings points 2, 2' to 12 V level and point 2" also remains at this level, which means that capacitor C21 again discharges via R22.
The opening, however, also causes the level of point 2"', which on closing was at 0 V, to change to +12 V (signal 2bl). Capacitor C22, which discharged to ground via switch X2 when it closed, now recharges, mainly via R26 and R27, and to a insignificantly lesser extent via the base emitter current of transistor TO I, so that a positive level then results at the base of NPN transistor TO I and this switches on until capacitor C22 is again charged to a point where 7 the base voltage drops below the threshold value of transistor TO 1 (signal 2b2). This then causes a negative pulse 2b3 to be produced at the collector of transistor TO 1 which switches transistor T02 on and off via base resistor R025 thus inverting signal 2b3 and producing a signal in the form of 2a3 at output Y.
The path of the signal from Xl is different from the signal from X2 already described only in that in this case there is no junction corresponding to point 2... to the base of transistor TO 1 or of the preceding RC element. Points 1, F and 1---on the contrary correspond to points 2, 2' and 2---. Accordingly, the levels at 1, F and l- when the switch at X1 closes correspond to level 2, 2, and 2" when the switch at X2 closes and thus also produces a positive impulse in the form of 20 at output Y. Because there is no point corresponding to 2-, there is no corresponding switching on and off of transistor TO1 when the status of the switch at X2 changes from closed to open. It is, of course, conceivable for a junction corresponding to point 2... to be provided and also to generate a wake-up signal for XI on both a tailing and rising edge.
With the switch at X3 open, 0 V level is present at point 3 via R3 1, which when the switch is closed, thus connecting to +12 V, changes to this level (signal 3al). Capacitor C32 discharged in the sleep mode is now charged via R32 and R27 and thus at the base of NPN transistor TOI, previously at zero through R27, a positive level is present which switches on transistor TOL Transistor TOI remains switched on until capacitor C32 is charged to a point (signal 3a2) where the level at the base of TO I drops below the threshold and TOI again switches off. In this way, a negative pulse in the form of 2b3 is generated at the collector of TOI which, as previously described, is inverted at output Y to a positive impulse in the form of 20. When the switch at X3 is opened, the base of T01 goes to 0 V via R27 and the previously charged capacitor C32 discharges to ground via resistor R3 1.
8 In the circuit shown in Fig. 2, the generation of a wake-up signal at any change in the control state of the switch at X2 is shown only by way of example, whereby at X1 and X3 only a change in the negative edge in the case of X1 and the positive edge in the case of X3 serves to generate a wake-up signal. Of course, several switches of the X2 type, or also several of the X1 and/or X3 type, could be provided depending on the application of a such a circuit. Equally, the number of input signals or switches can be increased or reduced, but diodes corresponding to D12 and D22 would have to be used to decouple the circuits. This results in a circuit configuration which can be expanded and modified as required to suit a variety of applications.
As shown in Fig. 2, the circuit configuration has an additional +I 2VGESCH (SWITCHED) power supply, which can be advantageously switched or pulsed. This is decoupled from the circuit previously described and the + 12 V power supply via diodes D 11, D21 and D13 and D23 and is switched on only in the active mode. The switch on can, for example, be created by the application of the wake-up signal via a switching device, for instance a microprocessor.
Decoupling, the power supplies does not affect the function of the circuit configuration, so that in the active mode the control state of the switch of X1 can be interrogated at Xal via voltage divider R14 and R15, for instance by means of a microprocessor, because with switch X I open, a positive level, for example in the form of a pulse which changes to a zero signal when the switch of X1 is closed (for example in the form of a LOW pulse), is present at Xal. The signals present at Xal and Xa2 depend in this case on the power source used in the active mode and are present in the example in the form of a pulse (MGH or LOW) only because of the pulsed power source +12V-GESCH. It is also conceivable to generate a constant level (FUGH or LOW) for Xa I and Xa2 by using a permanent power source in the active mode.
9 The signal at Xa2 behaves in the same way as the switch at X2. On the other hand, X3 is to be regarded as a special case whose circuit in the active mode is not supplied from the pulsed power source. In this case, a constant FUGH is present at Xa3 via voltage divider R33 and R34, only when switch S3 is closed. The purpose of X3 is to show that a detailed interrogation of the state of a switch with a permanent power source is also possible, whereby instead of a switch connecting to ground when closed, a variant using a switch which connects to +12 V when closed can also be used. In this case, power, apart from negligible leaks, is consumed only when the switch is closed, as already shown for the sleep mode for circuits X I, X2 and X3.
The individual circuits shown by way of example for X1, X2 and X3, may of course be combined as required in any circuit configuration and thus matched to the particular requirements of various fields.
In the circuit configurations with individual overlapping circuits shown in the example, the power consumption in sleep mode is almost zero because in a normal case - all switches open - no current flows apart from leakage currents through diodes, capacitors and transistors. In this mode, the switch which generates a wake-up signal is not precisely detected.
This wake-up signal can be used to switch on the power supply of a microprocessor, for example by means of a voltage regulator. In this way, the power consumption of a circuit configuration is advantageously limited to almost zero because the circuit configuration consumes no energy in the sleep mode.
An increased power consumption by the circuit configuration does not take place until the active mode, in which case the circuit now detects the control states of the particular switches in detail. This increased power consumption can, however, be kept advantageously low by the use of a pulsed power source with pauses between the impulses which are longer than the pulse width. In this case, the pauses can amount to several ms, for instance 10 ms. The value for the pulse width can for this purpose, for instance, be selected from a 50 to 500 ts range.
Claims 1. Circuit configuration for detecting control states of at least one operating means (S 1, S2, S3), particularly switches for activating a motor vehicle electronic device, with a sleep mode and an active mode, whereby the circuit configuration generates a wake-up signal (Y, 20) in the sleep mode, if at least one operating means (S 1, S2, S3) changes from a first defined control state to a second defined control state, whereby the circuit configuration is arranged so that it also generates the wake-up signal (Y, 20) on a change from the second control state to the first control state and whereby the circuit configuration is arranged such that it has a power consumption of almost zero in the sleep mode.
2. Circuit configuration in accordance with Claim 1, characterised in that the wake-up signal (Y, 20) can be generated by a change in a control state of at least one of several operating means (S 1, S2, S3) regardless of the control state of the other operating means (S 1, S2, S3).
3. Circuit configuration in accordance with Claim 1 or 2, characterised in that the circuit configuration has an active mode for detecting the control state of each individual operating means (S 1, S2, S3), which is activated by the wake-up signal (Y, 20).
4. Circuit configuration in accordance with Claim 3, characterised in that a pulsed power source'(+ 1 2V-GESCH) is activated in the active mode.
12 5. Circuit configuration in accordance with Claim 4, characterised in that the impulses of the power source (+12V-GESCH) have a pulse width in the 50 to 500 [is range and pauses between individual impulses in the 5 to 20 ms range.
6. Circuit configuration in accordance with one of the preceding Claims, characterised in that the circuit configuration for at least one operating means (S1, S2, S3) has a first circuit with a first pulse shaper (11), in order to generate a wake-up signal (Y, 20) on a changeover from the first control state, to the second control state, and has a second pulse shaper (12) in a second circuit with an inverter, so that the wake-up signal (Y, 20) is generated on a change of the second control state to the first control state.
7. Circuit configuration in accordance with Claim 6, characterised in that the first and second circuits partly overlap.
8. Circuit configuration in accordance with Claim 7, characterised in that the second circuit includes the pulse shaper (11) of the first circuit.
9. Method for detecting control states of at least one operating means (S 1, S2y S3), particularly switches for activating a vehicle electronic device whereby a different value (0, + 12 V) is assigned to at least one operating means (S 1, S2, S3), to each control state where there are at least two control states. characterised in that each change in the values (0-12 V, 12-0 V) in a sleep mode, in which the power consumption is almost zero, is converted to a wake-up signal (Y, 20).