GB2350757A

GB2350757A - Delay compensation buffer

Info

Publication number: GB2350757A
Application number: GB9912792A
Authority: GB
Inventors: Jouni Kristola
Original assignee: Nokia Telecommunications Oy
Current assignee: Nokia Oyj
Priority date: 1999-06-03
Filing date: 1999-06-03
Publication date: 2000-12-06
Also published as: GB9912792D0

Abstract

A delay compensation buffer is used to compensate for differing delays in data received over a plurality of data links (for example in an IMA transmission system) to enable the data to be merged to form an aggregate data stream. Data received over each link is stored in a respective group (L1-L3) of addresses in a memory, the addresses into which data are to be written at any one time being identified by write pointer means (16, 18, 22) . The data is then read from the addresses identified by read pointer means (20), with the read and write pointer means moving through the addresses of the groups in the same sequence, and being so offset relative to one another that the faster the link, the shorter its data is stored in the buffer memory, so as to compensate for the differences in said delays. The buffer is expandable to accept a further link (L3), in which case it is also operable to determine the delay associated with the further link and adjust the relative offset of the read and write pointer means (if necessary) also to compensate for the delay in data. Where a common read pointer is used, and the further link has a longer delay than any of the existing links, the read pointer (for all the links) is moved back until it is behind the write pointer for the further link, and the reading of the memory addresses is prevented until the read pointer has returned to the position it occupied before it was moved back.

Description

2350757 TITLE: DELAY COMPENSATION BUFFER

Field of the Invention

This invention relates to delay compensation buffers, and is particularly applicable to such buffers for use in inverse multiplexer systems for transmitting data. The invention also relates to a method of inverse multiplexed data transmission.

Background to the Invention

An inverse multiplexer (IMA) system may be used in a telecommunications network to enable the network to carry a data stream which has a higher data rate than any of the individual data links used in the network. The inverse multiplexer system comprises a transmitter which acts as a demultiplexer for dividing an input aggregate data stream into several lower speed data streams. Each lower speed data stream is then transmitted over a respective independent transmission link to the receiver of the inverse multiplexer system. The receiver includes a multiplexer which re-assembles the data from the various links into the aggregate data stream. Such systems are often used to transmit Asynchronous Transfer Mode (ATM) signals, which generally have relatively high bandwidth requirements, over digital telecommunications systems.

The desired characteristics of one type of inverse multiplexer system are defined by ATM Forum in the Inverse Multiplexing for ATM (IMA) specification, AF-PHY=0086.000.

Inverse multiplexing systems provide a cost-effective modular bandwidth for users by combining any desired amount of individual transmission links to form a single virtual link to provide, for example, user access to an ATM network or for connecting ATM elements.

2 However, since the individual physical data links take different routes through the network, the transmission delay times (i.e. the time between the application of data to the input of a given link and the receipt of the data at the other end of the link) can vary from link to link. It is therefore necessary to compensate for these delay differences in the receiver before the original aggregate data stream can be reassembled in the correct order. To that end, it is known to employ a delay compensation buffer (DCB) which delays the data received on the faster links more than that received on slower links.

For an IMA system, various required characteristics of the delay compensation buffer are set out in IMA specification appendix A, in which the method of aligning data from di f f erent links in the buffer is also presented. The specification describes the generation of DCB write pointers (which determine the memory addresses of the buffer into which data is to be written) and the principle of a common read pointer value for determining the addresses from which, at any one time, data is to be read.

However, the IMA specification fails to indicate how a DCB can operate in such a way as to enable an IMA system to be expanded by the addition of a further link having a longer delay than the existing links. Thus, known IMA systems cannot be expanded in this way without errors being introduced into the reassembled data stream.

Sunnary of the Invention According to a first aspect of the invention, there is provided a delay compensation buffer for compensating for differing delays in data received over a plurality of data links to enable the data to be merged to form an aggregate data stream, the buffer comprising a memory for storing data received over each link in a respective group of addresses, write pointer 3 means for defining the addresses into which the data is written and the sequence in which data is written into the addresses and read pointer means for defining the addresses from which data is to be read, also in said sequence, the read pointer means and write pointer means being so offset relative to one another as to compensate for differences in said delays, wherein the buffer is expandable to accept a further link and is operable to adjust, if necessary, the relative offset of the read pointer means and the write pointer means also to compensate for the delay in the transmission of data over the additional link.

The feature that the relative offset of the read and write pointer means can be adjusted in response to the addition of a new link enables the buffer to accept a link which has a longer delay than any of the existing links so that the reading of data from the new link is properly synchronised with that of data from the existing links. By contrast, were a longer delay link to be added to a prior art compensation buffer, the timing of the sending of data for the new link would not be consistent with that of the existing links, leading to the loss of the correct sequence of data in the aggregate data stream.

Said adjustment may, for example, be achieved by altering the position(s) in the sequence of the read pointer means, the write pointer means or both the read pointer means and the write pointer means.

Preferably, the read pointer means comprises a common pointer which, at any given time, identifies corresponding addresses, in said sequence in the groups, the write pointer means comprising a respective pointer for each group, each write pointer being offset from any other write pointer by a number of addresses corresponding to the relative delay between data received on the link for that pointer's group and the data received on the link for the other group.

4 Thus if, for example, each group has 128 addresses (each for holding, for example, a single ATM cell), then at any one time the read pointer identifies the nth cell (where n is greater than or equal to 1 and less than or equal to 128) cell in each group. The use of a common read pointer conforms with the IMA specification referred to above.

Preferably, the buffer is operable to determine whether the delay in receipt of data over the further link is greater than each delay associated with the existing links and, if it is, to move the common read pointers sufficiently far back in the sequence for it to follow the write pointer of the further 1 ink.

Preferably, in that event, the buffer is also operable to prevent data which are stored in the groups of addresses for the other links and which have already been read from being fed to the output aggregate data stream a second time.

To that end, the reading of data from the memory may preferably be prevented or inhibited until the common read pointer has progressed, through said sequence, to the position it occupied before having been moved back.

Conveniently, the sequences are consecutive sequences, so that, after having caused data to be written to any given address in its group, each write pointer moves to the neighbouring address in the group, and the process continues until data has been written to all the addresses in the group, whereupon the write pointer recommences from the first address in the group, the common read pointer also moving through the addresses in each group consecutively.

Thus, the invention provides a buffer which adjusts the read pointer, in the case of a newly added link having the longest delay, and pauses the reading of data out f rom the buf f er af ter the read pointer phase is adjusted.

The invention also lies in an inverse multiplexing receiver for receiving data over a plurality of data links, having different delays associated therewith, of a telecommunications system, wherein the receiver includes a delay compensation buffer as aforesaid.

Preferably, the receiver forms part of the node of a telecommunications system. Preferably, the receiver is an IMA receiver.

According to a further aspect of the invention, there is provided a method of adding a data link to an inverse multiplexed data transmission system, in which system data from existing links is supplied to a buffer memory for compensating for differing times taken to transmit data over the links, the data from each link being written into a respective group of memory addresses under control of write pointer means for identifying the addresses in the group into which data is to be written and for moving from each address in each group to the next in a given sequence, the stored data being read from addresses identified by a common read pointer which moves from each address to the next in each group in the same sequence as the write pointer, the read pointer and write pointers being so offset from each other as to compensate for said differences in data transmission times, the method comprising the step of adding an additional link, determining the transmission delay of data over the additional link with those of other links and, if that delay is the greatest of all the links, moving the read pointer back through the sequence of addresses so that it follows the write pointer of the additional link.

Where the read pointer is moved back, the method preferably also comprises a step of not reading any data from the groups associated with the existing links until the read pointer has returned to the position from which it was moved back.

Brief Description of the Drawings

I 6 The invention will now be described, by way of example only, with reference to the accompanying drawings in which:

Figure 1 shows an IMA system which includes a buffer in accordance with the present invention; Figures 2A-2F are simplified representations of the memory of the buffer, showing what happens when a new data link is added to the IMA system; and Figures 3A-3F are corresponding views which illustrate the way in which a known buffer would fail to accommodate a new link (if the new link has the longest delay).

Detailed Description

The telecommunications system shown in Figure 1 is a digital system, such as an SDH system, and has an ATM layer over which ATM signals can be transmitted and received. To that end, the telecommunications system uses an IMA system because the granularity of commonly availa'--le link bandwidths is too coarse and the use of higher speed 'Links for the purposes of ATM transmission is relatively expensive. For example, a user requiring a 10 Mb/s capacity -for ATM transmissions would have to pay for a 34 Mb/s transmission link, which is expensive, if an IMA sysem were not used. By contrast the IMA system allows the user to transmit the ATM signals over five 2 Mbits/s links at a much lower cost. IMA thus provides a relatively cost effective means of using available transmission links.

Accordinaly, the system shown in Figure 1 includes an IMA transmitter 1 which acts as a de-multiplexer of an ATM data stream, generally referenced 2. The transmitter 1 thus splits the input signal 2 into a numher of component signals, each of which is transmitted through the telecommunications network (generally referenced 4) alonc a respective one of four links such as the link 0 (indicated by reference numeral 6). The 7 signals from the links are received by an IMA receiver 8 which includes a multiplexer 10 for re-assembling the signals into the transmitted ATM cell stream 12, which is passed back into the ATM layer of the network. The links take different physical routes through the system, and as a result the data delay (between transmission by the transmitter 1 and reception by the receiver 8) will vary from link to link. In order to compensate for this, the receiver 8 includes a delay compensation buffer 14 which applies a delay to the data received from the links before the data is passed on to the multiplexer 10, the amount of the delay for any given link being inversely related to the speed of the link.

The IMA signal transmitted over each of the links (link # 0link # 3) is divided into frames, each of 128 cells, including an IMA Control Protocol (ICP) cell, the position of which defines the frame offset. The link with the smallest ICP offset and frame sequence numbers is the link which has the longest delay.

Data from the links is written to the buffer in the way shown in Figures 2A-2F. Each of those Figures shows a part of the memory of the buffer, represented as three columns (L1, L2 and L3), each of ten boxes. Each box constitutes an address in the memory and is able to store a respective IMA cell, and the columns represent three groups of memory addresses, each associated with a respective link. In this case, column Ll represents the group for link # 1, column L2 link # 2 and column L3 link # 3. For the sake of simplicity, only 10 addresses are shown in each group, the fourth group (for link # 0) is not shown and the IMA f rame length is assumed to be of only 8 cells.

In Figures 2A-2F, the letters a-c indicate the IMA frame being received, whilst the accompanying numbers (1-8) identify the cell in that frame. The values for T shown on the figures represent time (in terms of numbers of cells received on a link L1) For the group Ll, the identity of the address into which a given cell is to be written is determined by a write pointer 16, whilst the write pointer 18 determines the address into which a cell is to be written in the group L2. In this example, data received over the link # 2 is delayed by 3 cells relative to that received over link 4 1. Each of the write pointers starts at the bottom address of its group, and then is incremented, one address at a time, through the group until the top address in the group has been reached, whereupon the pointer then returns to the bottom of the group, and the cycle repeats itself. However, the pointer 18 lags behind the pointer 16 by a number of addresses corresponding to the difference in the delays between the links link # 1 and link # 2. Consequently, the frames from all the links are, in effect, aligned in the buffer memory (with the differing positions of the write pointers compensating for the differing delays in the links). The memory addresses in L1 and L2 which are to be read at any one time are identified by means of a common read pointer 20 which also starts at the bottom addresses and then increments up each of the groups (one address at a time) until it reaches the top whereupon it returns to the bottom addresses. The read pointer 20 thus reads the addresses in the sequence in which data was written into the addresses by the write pointers. Since the frames in the two groups are aligned, the effect of the differing delays in links link #1 and link # 2 has been eliminated so that the read pointer reads cell al from L1 and L2 simultaneously and then reads the cell a2 from both frames and so on.

Thus far, the operation of the buffer is as described in the ATM (IMA) specification.

However, in Figures 2A and 2B the link # 3 has yet to be added. This link is delayed by 6 cells relative to link # 1, and its write pointer 22 is therefore 6 addresses behind the write 9 pointer 16 and 3 addresses behind write pointer 18.

As can be seen from Figure 2C, this means that the write pointer 22 is initially ',above,, the other two write pointers, and the read pointer 20 is interposed between the pointers 16/18 and 22.

In order for the data to be read from the memory addresses in the correct sequence, the read pointer 20 must be behind the last of the write pointers (in this case 22), and is therefore moved back to the position shown in Figure 2D, in which it is positioned at the addresses immediately below the top address of each group and the write pointer 22. The pointers then progress in relation to the addresses in the same way as before, but nothing is read from the addresses until the read pointer returns to the bottom of the groups, i.e. the position shown in Figure 2C (which the read pointer 20 occupied before being moved back). When the read pointer was moved back, the addresses containing cells bi and b2 in L1 and L2 had already been read, and the interruption in the reading of data from the addresses therefore prevents those cells being read a second time. Once the read pointer 20 has reached the position shown in Figure 2E, reading from the addresses recommences, (with cells b3 being the next to be read), and continues as shown in Figure 2F.

The cells bi and b2 on L3 are "filler cells" which are emitted when the link is set up, so that the pause in read out does not disrupt the proper ATM signal.

Figures 3A-3F show what would happen if the read pointer were not to be moved back. Figure 3A corresponds to Figure 2C showing the situation in the buffer at T=15 (i.e. after the write pointer 16 has moved through 15 cells of Ll.

As can be seen from Figures 3B, 3C and 3D, the pointer 20 continues to cause data to be read from the addresses in the correct sequence until Time T=24 at which stage the pointer reads cells c3 from Ll and L2, -but cell bi from L3. The reason for this difference is that the address containing bl has not yet been overwritten with cell c3 by the time the read pointer 20 reaches it. Subsequently, (Figures 3E and 3F) the read pointer 20 continues to cause the cells read from each of Ll and L2 to be different from that read from L3 so that there is an error in the cells in the aggregate output data stream.

Claims

1 - A delay compensation buffer for compensating for different delays in data received over a plurality of data links to enable the data to be merged to form an aggregate data stream, the buffer comprising a memory for storing data received over each link in a respective group of addresses, write pointer means for defining the addresses into which the data is written and the sequence in which data is written into the addresses, and read pointer means for defining the addresses from which data is to be read, also in said sequence, the read pointer means and write pointer means being so offset relative to one another as to compensate for differences in said delays, wherein the buffer is expandable to accept a further data link, and is operable to adjust the relative offset of the read and write pointer means, if necessary, also to compensate for the delay in data transmitted over said link without causing errors in the positions, in the aggregate data stream, of data transmitted over the other links.

2. A buffer according to claim 1, in which the buffer is operable to adjust the position of the read pointer means relative to the addresses of the groups of addresses if the further link has a longer delay than the existing links.

3. A buffer according to claim I or claim 2, in which the read pointer means comprises a common pointer which, at any given time, identifies corresponding addresses in said sequence in said groups, the write pointer means comprising a respective write pointer for each group of addresses, each write pointer being offset from any other write pointer by a number of addresses corresponding to the relative delay between data received on the link for that pointer's group of addresses and data received on the link for the other pointer's group.

12

4. A buffer according to claim 3, in which the buffer is operable to determine whether the delay in receipt of data over the further link is greater than each delay associated with the existing links and, if it is, moves the common read pointer sufficiently far back in the sequence for it to follow the write pointer of the further link,

5. A buf f er according to claim 4, in which, where the read pointer is moved back, the buffer is also operable to prevent data in those addresses for the other links which have already been read from being fed to the aggregate data stream a second time.

6. A buf f er according to claim 5, in which the reading of data from the memory is prevented or inhibited until the common read pointer has progressed to the position it occupied before having been moved back in response to the addition of the further, longest delay link.

7. A buffer according to any of the claims 3 to 6, in which the sequence is a consecutive sequence, so that, after having caused data to be written into any given address in its group of addresses, each write pointer moves to the next address in the group, and the process continues until data have been written into all the addresses in the group, whereupon the write pointer recommences from the first address in the group.

8. An inverse multiplexing receiver for receiving data over a plurality of data links, the links having different delays associated therewith, wherein the receiver includes a delay compensation buffer in accordance with any of the preceding claims.

9. An inverse multiplexing receiver according to claim 8, in which the receiver forms part of a node of a telecommunications system.

13

10. A method of adding a data link to an inverse multiplexed data transmission system, in which system data from existing links is supplied to a buffer memory for compensating for differing times taken to transmit the data over the links, the data from each link being written into a respective group of memory addresses under the control of write pointer means for identifying the addresses into which data are to be written and for moving from each address in each group to the next in a given sequence, the stored data being read from addresses identified by a common read pointer which moves from each address to the next in each group in the same sequence as is followed by the write pointer means, the read pointer and write pointer means being so offset from each other as to compensate for said differences in data transmission times, the method comprising the step of adding an additional link having a respective group of memory addresses associated therewith, determining the transmission delay of data over the additional link and, if the delay is greater than the transmission time of each of the existing links, moving the read pointer back through the sequence of addresses so that it follows the write pointer means associated with the additional link.

11. A method according to claim 10, in which, when the read pointer is moved back, the method also comprises a step of not reading data from the groups associated with the existing links until the read pointer has returned to the position from which it was moved back.