GB2350244A

GB2350244A - Voltage converter

Info

Publication number: GB2350244A
Application number: GB0011765A
Authority: GB
Inventors: Howard H Bobry
Original assignee: Multipower Inc
Current assignee: Multipower Inc
Priority date: 1999-05-17
Filing date: 2000-05-17
Publication date: 2000-11-22
Also published as: JP2000358363A; GB0011765D0

Abstract

A system and method are provided to convert a DC voltage from a first voltage level to a second voltage level by operating multiple voltage converter circuits in staggered phase relationship. Smoothest operation with minimum ripple voltages and ripple currents will be obtained if each converter is equally phase shifted from the converters that immediately precede and follow it in operation. Given that a full cycle consists of 360 electrical degrees, if the number of converters to be used is "N", then each converter will be phase shifted from its neighbors by 360/N degrees. If, for example, three converters are used (N = 3) then each converter will be phase shifted from its neighbors by 360/N degrees. If, for example three converters are used (N=3), then each converter will be phase shifted from its neighbors by 120 degrees. Four phases will result in a 90 degree phase shift, and so on, resulting not only in greatly reduced ripple, but ripple which is at a frequency of N times the converter operating frequency, further simplifying and reducing any filtering required. A power factor controller (174, Figs 10 and 11) may be included.

Description

2350244 POLYPHASE VOLTAGE CONVERTER AND METHOD

CLAIM OF PRIORITY

This application claims priority to copending U.S. provisional patent application entitled, "Polyphase Switch Mode Power Converter," filed on May 17, 1999 and assigned Serial Number 60/134,452, and to co-pending U.S. provisional patent application entitled, "Polyphase Switch Mode Converter," filed on June 9, 1999 and assigned Serial Number 60/138,339, both of which are entirely incorporated herein by reference.

TECHNICAL FIELD

The present invention is generally related to the field of power conversion, and, more particularly, is related to a polyphase switch mode power conversion system and method.

BACKGROUND OF THE INVENTION

Various switch mode power converter circuits are well known in the art, including, among others, buck and boost converters. Buck converters operate to step a direct current (DC) voltage down from one level to another, lower, level, while boost converters operate to step up a DC voltage from one level to a higher level. These converter circuits are well known and are relatively simple and operate at high efficiency, but they are limited in power handling capacity due to the ratings of the solid state switching devices used, such as field effect transistors (FETs) and insulated gate bipolar transistors (IBGTs). For this reason, operation at high power levels may require that multiple switching devices be operated in parallel. Similarly, the inductors required are easier to produce and more economical in smaller sizes, so it is common practice to use both parallel switching devices and parallel inductors in converter circuits designed to operate at relatively high power levels.

While this parallel operation of components allows operation at the desired high power levels, it does nothing to reduce the high levels of ripple current and voltage produced at the input and output terniinals of these converters.

The benefits of polyphase operation in electric power distribution, transformers, and rotating machines such as motors and generators have long been understood. Three phase electrical power distribution is common as well as the use of three phase motors, generators, rectifiers, battery chargers, and power supplies. It has long been known and understood that polyphase power provides smoother operation of motors and generators because there are six, rather than two, pulses of power per cycle, just as a six cylinder engine is inherently smoother than a two cylinder engine of comparable power. In the case of devices that produce a DC output, such as rectifiers, battery chargers, and power supplies, the use of polyphase power is especially beneficial because the overlap of the phases greatly reduces the need to filter the DC output in order to achieve smooth, low ripple DC output voltages and currents.

It has been common practice in the prior art to use a plurality of switch mode converters, one per phase, in conjunction with polyphase power systems. For example, three converters have been used on a three phase power system where the three phases all contribute to a single output.

Unfortunately, for single phases, the same benefit has not been realized.

SUARY OF THE INVENTION In light of the foregoing, the present invention provides for a system and method to convert a DC voltage from a first voltage level to a second voltage level by operating multiple voltage converter circuits in staggered phase relationship. Smoothest operation with minimum ripple voltages and ripple currents will be obtained if each converter is equally phase shifted from the converters that immediately precede and follow it in operation. Given that a full cycle consists of 360 electrical degrees, if the number of converters to be used is "N", then each converter will be phase shifted from its 2 neighbors by 360/N degrees. If, for example, three converters are used (N = 3) then each converter will be phase shifted from its neighbors by 360/N degrees. If, for example three converters are used (N=3), then each converter will be phase shifted from its neighbors by 120 degrees. Four phases will result in a 90 degree phase shift, and so on, resulting not only in greatly reduced ripple, but ripple which is at a frequency of N times the converter operating frequency, further simplifying and reducing any filtering required.

The present invention may also be viewed as a method for converting a DC voltage. In this regard, broadly stated, the method comprises the steps of: arranging a number of voltage converter circuits in parallel orientation, generating a number of phase signals with a control circuit, and, applying each of the phase signals to a respective one of the voltage converter circuits, thereby causing the voltage converter circuits to generate an output waveform. The present method may further comprise the step of offsetting the phase signals by a predefined phase interval.

Other features and advantages of the present invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional features and advantages be included herein within the scope of the present invention.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE

DRAWINGS The invention can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present invention. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.

3 Fig. 1 is a schematic diagram of a conventional buck converter circuit according to the prior art;

Fig. 2 is a graph of selected waveforms of the circuit of Fig. 1; Fig. 3 is a schematic diagram of a conventional boost converter circuit according to the prior art;

Fig. 4 is a graph of selected waveforms of the circuit of Fig. 3; Fig. 5 is a schematic diagram of a two phase buck converter circuit according to the present invention; Fig. 6 is a graph of selected waveforms of the circuit of Fig. 5; Fig. 7 is a schematic diagram of a two phase boost converter circuit according to the present invention; Fig. 8 is a graph of selected waveforms of the circuit of Fig. 7; Fig. 9 is a graph of selected waveforms of a four phase boost converter circuit according to the present invention; Fig. 10 is a schematic diagram of a four phase boost power factor correction converter circuit according to the present invention; and Fig. 11 corresponds to Fig. 10 with the showing of the controller expanded.

DETAILED DESCRIMON OF THE INVENTION With reference to Fig. 1, shown is a buck converter circuit 10, according to the prior art. The buck converter circuit 10 is shown in schematic form and includes a switching device 16 that is drawn as a field effect transistor (FET). Although the switching device 16 and corresponding switching devices shown with reference to other figures may be shown as field effect transistors, it is understood that any such switching devices may include any suitable alternative switching device, such as bipolar transistors, insulated gate bipolar transistors, or various other devices.

Referring to Fig. 1, an input voltage is applied between an input 12 and a common connection 14 that is common to both the input and the output 4 of the circuit. Transistor 16 is switched on and off by a control circuit (not shown) so that generally the output voltage available at output 24 is at a desired level lower than that of the input voltage. When transistor 16 is r6on", current flows from the input voltage source, through inductor 20, and through a load (not shown) connected between output 24 and common 14. As current flows through the inductor, energy is stored in the inductor's magnetic field. After a period determined by the control circuit, the transistor is turned "off". At this point, the stored energy in the inductor field forces current to continue to flow through the inductor, the load, and through the diode 18, until the stored energy has been used up or until the transistor is again turned "on". If the transistor 16 is again turned on before the energy in the inductor field has been expended, the circuit is said to be operating in continuous mode, because the current through the inductor never declines to zero. The circuit, may also be operated in discontinuous mode, where the inductor current is allowed to decline to zero for some period during each cycle. In addition, the circuit can be operated in critical conduction mode, where the inductor current is allowed to just decline to zero before the transistor is turned on again to start the next cycle and cause an immediate increase in the inductor current.

With reference to Fig. 2, shown is a graph of two of the waveforms present in the circuit of Fig. 1. For purposes of example, the waveforms:

have been selected to be representative of a circuit which operates in a continuous mode, with a four to one step down in voltage, such as, for example, a circuit having a 48 volt DC input and a 12 volt DC output. The waveform 30 represents the voltage present at the junction between the transistor 16, diode 18, and inductor 20 in Fig. 1. This point is raised to the potential of the input voltage source 12 when the transistor is on, and falls to one junction below zero when the transistor is off due to the conduction of diode 18. In continuous mode of operation, the output voltage at 24 will be equal to the average value of the voltage 30, so for a 12 volt output and a 48 volt input, the duty cycle, or ratio of the transistor on time to the sum of the on time and off time, will be 1/4, or 25 When the transistor 16 is on, the inductor current, indicated by waveform 32, ramps up from a minimum to a maximum value as energy is being stored in the inductor's magnetic field. When the transistor 16 is off, the inductor current ramps down to its minimum value as shown. In this particular example the minimum has been selected to be near, but always above, zero, so that the circuit is operating in continuous conduction mode, but nearly at the point of critical conduction. Note that the desired output of the circuit is a smooth DC voltage, yet the current through the inductor is a saw tooth waveform. The capacitor 22, shown in Fig. 1, serves the purpose of providing a path for the AC (ripple) components of the inductor current.

The amount of ripple voltage present at the output of the circuit will be a function of this ripple current, the capacitor size, and the ripple frequency.

The average DC component, of the inductor current is shown by dashed line 34 in Fig. 2. The ripple current, which must pass through the output capacitor 22 shown in Fig. 1, is the difference between the DC current 34 and the actual inductor current 32. The circuit shown in Fig. 1 and the waveforms of Fig. 2 reflect the prior art and are well known and understood.

Referring next to Fig. 3, shown is a boost converter circuit 40 according to the prior art. An input voltage is p roduced between output 54 and the common 44. For purposes of example, assume that the converter has a three to one step up ratio, such as, for example, a 12 volt input and a 36 volt output. As in the case of the buck converter previously described, the boost converter may operate in continuous, discontinuous, or critical conduction modes. In operation, transistor 48 is turned on and off by a control circuit (not shown) generally in response to the voltage level at output 54. When the transistor 48 is on, current flows from the input 42, through inductor 46 and the transistor 48. As was the case with the buck converter circuit IQ.(Fig. 1) previously described, when the transistor 48 is "on" the 6 current in the inductor 46 increases, as does the energy stored in the inductor's magnetic field. When the transistor 48 is turned "off," current continues to flow from the input, through the inductor 46, and then through diode 50 to the output 54. A capacitor 52 is connected across the output 54 and the common 44 of the boost converter circuit 40 that provides a path for the AC (ripple) components.

Turning to Fig. 4, shown is the voltage waveform 60 at the junction of the transistor 48 (Fig. 3), diode 50 (Fig. 3), and inductor 46 (Fig. 3), as wen as the inductor current waveform 62 and the average or DC component of the current through the inductor 46, that is shown by waveform 64. The voltage is reduced to near zero when transistor 48 is turned on. At the same time, the inductor current 62 ramps up to a maximum that is reached at the time the transistor 48 is turned off. At that instant, the inductor current can no longer.

flow through the transistor 48, and must flow through diode 50 to the output 54 and thence to the load (not shown). As was the case with the buck converter circuit 10 (Fig. 1), the operation of the boost converter circuit 40 is well known in the art.

Referring to Fig. 5, shown is a polyphase buck converter 70 according to an embodiment of the present invention. The polyphase buck converter 70 comprises two buck converters 72 and 74 that are operated in a phase shifted relationship. Each of the buck converters 72 and 74 operates as was described with respect to Figs. 1 and 2. The buck converters 72 and 74 use a single input 76 with respect to common 78, and produce a single output 80.

The buck converters 72 and 74 are driven by control circuit 82 such that the buck converters 72 and 74 operate 180 degrees out of phase with each other.

The control circuit 82 may be implemented from discrete components, or may be an integrated circuit as will be described more fully with respect to Fig. 7.

Turning to Fig. 6, shown is a graph of a number of waveforms that illustrate _the phase shifted operation of the polyphase buck converter 70 (Fig.

7 5). The following discussion of the operation of the polyphase buck converter 70 assumes a four to one voltage step down ratio. Waveforms 90 and 94 represent the voltage waveforms in buck converters 72 and 74 respectively, taken at the junctions of the respective transistors, diodes, and inductors. The waveforms 90 and 94 generally correspond to waveform 30 (Fig. 2). Similarly, waveforms 92 and 96 are the inductor current waveforms in the two buck converters 72 and 74, each corresponding to waveform 32 (Fig. 2). According to the prior art, operation of the buck converter circuit (Fig. 1) at a doubled power level, or operation of two such circuits in parallel, would result in a doubled inductor current shown by waveform 98.

According to the present invention, operation of the two buck converters 72 and 74 in a polyphase configuration, i.e., phase shifted as described, results in a composite current shown by waveform 100 that is the sum of the individual inductor currents 92 and 96. Waveform 102 shows the average, or DC component, of the output of the polyphase buck converter 70.

It is apparent that waveform 100 is smoother and has a significantly lower AC current component or ripple than waveform 98 that is representative of the prior art. Further, it can be seen that by using the present invention not only has the magnitude of the ripple been reduced, but the frequency has been doubled, and this in turn makes it easier to filter this ripple to obtain smooth DC input and output currents. The increase in ripple frequency is a direct function of the number of phases used, such that if there are N phases, the ripple frequency will be multiplied by N. The reduction in ripple magnitude is a function of not only the number of phases, but also the voltage conversion ratio of the converter.

Turning to Fig. 7, shown is a polyphase boost converter 110 according to another embodiment of the present invention. The polyphase boost converter 110 includes two phases, although a greater number of phases may be employed according to the principles of the present invention. A DC voltage is applied between input 112 and common 114. A first boost circuit 8 comprised of inductor 118, transistor 122, and diode 136 operates as a first phase, and a second boost circuit comprised of inductor 120, transistor 124, and diode 138 operates as a second phase. The second phase is shifted 180 degrees, or one half cycle, from the first phase. The output voltage is generated at the output 142 with respect to common 114. Input capacitor 116 provides a path for input ripple current flow, while output capacitor 140 provides a path for output ripple current flow and filters the output.

The boost converter circuits are driven by control circuit 134 that in a similar manner as the control circuit 82 (Fig. 5). The control circuit 134 drives the transistors 122 and 124 through resistors 126 and 128 as shown, and regulates the output voltage of the polyphase boost converter 110 in response to a feed back voltage divider that comprises resistors 130 and 132.

The control circuit 134 may be a double ended pulse width modulation converter intended for push-pull inverter applications as are well known in the art, such as, for example, the "Current Mode PWM Controller" manufactured by Unitrode Corporation, Model Number UC1846/7 that is the subject of a Unitrode publication "Current Mode PWM Controller," Model Number UC186417, dated 1197. Further details of the operation and connection of the Unitrode controller are provided in the above referenced publication that is incorporated herein by reference.

Referring next to Fig. 8, shown are the pertinent waveforms of the polyphase boost converter 110 (Fig. 7). For purposes of illustration, the polyphase boost converter 110 is assumed to be operating at a conversion ratio of 12, such that the output voltage is double the input voltage. This is achieved, with continuous mode operation, with a 50 % duty cycle, i. e. the transistor is turned on, or made conductive, for one half the duration of each cycle. The voltage waveforms 150 and 152 generally correspond to the voltage waveform 60 (Fig. 4). The inductor current waveforms 154 and 156 correspond to the current waveform 62 (Fig. 4). The waveform 158 is the sum of the current waveforms 154 and 156. Because the two boost 9 converters of the polyphase boost converter 110 operate at a 50 % duty cycle with a phase separation of 180 degrees, the current waveform 154 rises at the same rate, and at the same time that the current waveform 156 falls, and vice versa. The result of this is that the waveform 158 that is the sum of these 5 currents has no AC or ripple component.

With reference to Fig. 9, shown is a graph of a ripple current generated in an polyphase boost converter using four boost converter circuits 40 (Fig. 3), for example, that are operating in critical conduction mode to provide further illustration of the principles of the present invention. The graph includes four boost converter inductor currents 160, 162, 164, and 166 over a period of two complete cycles or 720 degrees. Generally, the current flowing through each inductor in the polyphase boost converter of this example ramps from a minimum of zero (0) to a maximum of eight (8) amperes, and back down to zero. Adding these four currents yields the composite, or effective current, waveform 168. According to the prior art practice, either a single converter or four parallel converters would have to process a current ramping from zero to thirty-two (32) amps to yield an average DC component of 16 amps and would produce an AC or ripple current component of thirty-two (32) amps peak-to-peak.

According to the present invention, the composite current 168 has an average (DC) component of 16 amps as desired, but the AC (ripple) current component has been reduced to two (2) amps peak to peak. The operation of four boost converter circuits 40 in a polyphase configuration, evenly phase shifted with respect to one another, has reduced the undesirable ripple current component by a factor of sixteen. In addition, the frequency of the ripple current has increased four fold. Since the impedance of an output filter capacitor located at the output of the polyphase boost converter similar to the output filter capacitor 140 (Fig. 7) is inversely proportional to frequency, the four fold increase in ripple frequency increases the effectiveness of the capacitor as a filter by a factor of four. This, combined with the reduction in ripple magnitude by a factor of sixteen, results in a reduction of ripple, with a given filter capacitor, by a factor of sixty-four (64) when compared with a converter of the prior art. Conversely, the size of the filter capacitor may be reduced by a factor of sixty-four while keeping the ripple the same as that of 5 the prior art.

While the control circuit 134 (Fig. 7) described with respect to the polyphase boost converter 110 (Fig. 7) is useful for implementing two phase operation, more than two phases require additional circuitry to generate the drive signals for the additional transistors and inductors. In general, where N phases are used, N phase drive signals, one for each phase, are required. These phase drive signals may be derived from a single, master control signal. It should be apparent that there are many circuit configurations that can achieve this desired result, including the use of a microprocessor controller. Once such circuit includes a circuit described with reference to Fig. 10 that relies upon digital shift registers to derive slave drive signals from a master drive signal, although this circuit is not the only circuit that may be employed for the purpose of generating the appropriate phase drive signals.

Turning to Fig. 10, shown is a schematic diagram of a four phase boost converter circuit 170 according to the present invention. In particular, Fig. 10 illustrates the use of the present invention as a power factor correction circuit. Power factor correction circuits, well known in the art, typically use a boost converter to modulate an input current of a converter in such a manner that the input current remains, at all times, proportional to the input voltage. Where the input voltage is, for example, a rectified sine waveform, the input current of a converter will also be a rectified sine waveform.. In this manner the power factor of the converter input is corrected, or made to look as if the converter were a resistive load. Such power factor correction circuits are typically controlled by an integrated circuit control device made specifically for the purpose, such as, for example, 11 the power factor controller manufactured by Motorola, Inc., of Schaumburg, Illinois USA, Model Number MC34262 described in the data sheet published by Motorola, Inc., entitled "Power Factor Controllers", Model Nos.

MC34262/MC33262, (1996), which is incorporated herein by reference in its entirety.

Referring once again to Fig. 10, the four phase boost converter circuit includes a power factor controller circuit 174 that features the previously referenced power factor controller 175, Motorola Model No. MC34262 and associated components as shown in simplified schematic form. For components or devices of Fig. 10 for which a reference is or has been made to a manufacture's publication, the manufacturer's pin numbers for a referenced component have been shown on the drawing, including the power factor controller 175 that shows the manufactures pins 1, 3, 4, 5, and 7. The omitted pins are merely connected to supply voltages or to a common and, consequently, are not shown in the figures.

In addition to the power factor controller circuit 174, the four phase boost converter circuit 170 further comprises a clock oscillator 172, a first shift register 178, a second shift register 176, a counter 180, and four phase boost converter 188 as shown. The four phase boost converter 188 comprises respective boost converters with respective inductors 202, 204, 206, and 208 as well as transistors 210, 212, 214, and 216 as shown. Although the four phase boost converter 188 is shown with respective boost converters, it is understood that the four phase boost converter 188 may be replaced with a four phase buck converter according to the principles of the present invention.

With respect to the power factor controller 175, pin 3 connected to the converter input 190, pin 1 (VFBK) is connected to the converter output 194, pin 5 (zero) is connected to the output circuit of the counter, and an output pin 7 is connected to the shift register 178 and to a driver for the transistor 210 for the first inductor 202 of the master phase, all circuits of the 12 component being referenced to circuit common 192. Operation of the power factor controller 175 is as described by the Motorola publication with the exception that it operates in a discontinuous conduction mode, where the controller runs at a fixed master cycle frequency as determined by a clock circuit, not voltage or current. This contrasts with the operation of the power factor controller 175 as described in the Motorola publication in a critical conduction mode, i.e. the drive output from the controller occurs immediately upon an inductor current of a cycle reaching zero voltage.

A clock signal is derived from the clock oscillator 172 that is comprised of a hex inverter circuit connected to achieve a buffered RC oscillator as is well known in the art. The clock signal from the clock oscillator 172 drives the counter 180, a conventional digital counter such as, for example, a 12 bit binary counter Model No. MC1404013, manufactured by Motorola, Inc., of Schaumburg, Illinois, the 12 bit binary counter being the subject of publication Motorola CMOS Logic Data (1995). The 12 bit binary counter Model No. MC14040B is provided as an example as other suitable counters are well known to the art and are commercially available.

As shown in Fig. 10, selected outputs of the counter 180 are coupled to a logic circuit 186, so that a start pulse is obtained from the counter 180 to activate the output of pin 7 of the power factor controller 175 after a fixed, predetermined number of clock cycles from the clock oscillator 172. Thus, while a master cycle involves four phases which are shifted from each other as explained herein, the counter 180 only initiates each successive master phase via its output to the power factor controller 175.

In typical single phase operation, the output of the power factor controller circuit 174 would be buffered by an amplifier and then used to drive the transistor 48 (Fig. 3) of a boost converter circuit 40 (Fig. 3) to charge the inductor 46 (Fig. 3). In the four phase boost converter circuit 170, the output of pin 7 of the power factor controller 175 is buffered by one of two amplifiers contained in a dual buffer package 184. The dual buffer 13 package 184 may comprise, for example, a dual buffer package Model No. MC34152, manufactured by Motorola, Inc., of Schaumburg, Illinois, the amplifier package being the subject of the Motorola publication: "High Speed Dual MOSFET Drivers" MC34152-MC34152, (1996). The dual buffer package Model No. MC34152 is provided as an example as other suitable buffers are well known to the art and are commercially available. The output of the amplifier is used to drive transistor 210 as shown.

The output from the power factor controller 175 is referred to as the master phase of a master cycle, or the first phase. The output of the controller 174 also drives the data input D of the first shift register 178. The first and second shift registers 178 and 176 may be contained within, for example, a single Dual 64-Bit Static Shift Register, Model No. MC14517B manufactured by Motorola, Inc., of Schaumburg, Illinois and are described in a data sheet entitled "Dual 64-Bit Static Shift Register" published by Motorola, Inc., (1995), the entire content of which is incorporated herein by reference. Thus, although the first and second shift registers 178 and 176 are shown as separate items, in fact they are contained within the same integrated circuit for the sake of convenience. The first and second shift registers 178 and 176 generally act to delay the respective phase signals that are applied to the remaining transistors212, 214, and 216 as shown. It is understood that there are many other components that may be used in place of the first and second shift registers 178 and 176 to generate delayed phase signals from a master phase signals as is known by those skilled in the art.

To summarize, the shift register 178, shown in Fig. 10, receives a signal at its data input D and digitally shifts this signal with each cycle of the clock signal from the clock oscillator 172, thereby delaying the signal received. The delayed or shifted signal may be obtained at pins 1, 6, 2, 5, 15, 10, 14, and 11 of the first and second bit shift registers 178 and 176 as shown, depending upon the number of delay stages through which the signal is to be processed. In order to obtain increased delays, a number of the shift 14 registers 176 and 178 may be connected in cascade, such that inputs of a subsequent shift registers are connected to one of the outputs of shift registers prior to them as is the case with the first and second bit shift registers 178 and 176. The first shift register 178 provides output delays of 16, 32, 48, and 64 clock cycles and the second shift register 176 adds delays to the first to yield delays of 80, 96, 112 and 128 clock cycles as shown.

In order to obtain the desired four phases, evenly spaced with respect to each other, a master phase output signal is generated by the power factor controller 175 and is directly applied to the transistor 210 without delay to initiate the first phase and is also applied to the data input D of first shift register 178 to establish delayed outputs at 32, 64 and 96 clock cycles of the cascaded first and second shift registers 178 and 176. Each phase is thus displaced from each adjacent phase by 32 clock cycles. The selected outputs of the first and second shift registers 178 and 176 are buffered by amplifier stages of buffer circuits 182 and 184 as previously described with respect to the master phase. Each of these slave phases, like the master phase, drives one of the transistors 212, 214, or 216 of the four phase boost converter 188.

As before, the four phase boost converter 188 includes four boost converters that comprise inductors 202, 204, 206 and 208, an inductor for each of the phases with each having respective transistor switches 210, 212, 214 and 216 and each being connected to the output by a diode 219. The transistor switches are turned on and off in sequence to provide a four phase output and a four phase power factor correction boost circuit is realized according to the present invention.

With reference to Fig. 11, shown is the four phase boost converter circuit 170 with the same components as depicted in Fig. 10 with a more detailed depiction of the power factor controller 175 and with the addition of a full wave rectifier 224 as shown. The power factor controller 175 comprises several components, including a latch drive component 217, a comparator 226, a multiplier 222, and a cycle averaging circuit and error amplifier circuit 225. The drive output on pin 7 of the controller 175 for the transistor switch 210 is latched on by setting a latch in the latch drive component 217 and is high for the duty on-time of the transistor switch 210 and off when the latch drive component is reset. The output of pin 7 remains off until the initiation of the next master cycle by the counter 180.

The output of the controller on pin 7 is also connected to the D input of first shift register 178. This enables a number of logical " Ps" to be clocked into the first shift register 178 while the transistor 210 is in an "on" state. When the transistor 210 is in an "off" state, zeros are clocked into the 10first shift register 178. Thus the transistors 212, 214, and 216 are turned on by the "1's" as that are shifted through the respective output stages to which the drivers for the transistors 212, 214, and 216 are connected, and the transistors 212, 214, and 216 are turned off at each stage when the zeros appear once again.

The output from the power factor controller 175 to the first shift register 178 and the first phase transistor switch 210 is turned off when the inductor current through the transistor 210 exceeds a threshold determined by a voltage derived by the multiplier 222 from an input at pin 3 of the power factor controller 175. At pin 3, the multiplier 222 monitors the full wave haversines of the full wave rectifier 224 providing the input to the respective boost converters. The multiplier 222 also has an input from a cycle averaging circuit and error amplifier circuit 225 that averages a feedback from the converter output over several cycles of operation to provide an error signal representing the output voltage error, the input to the cycle averagi g and error circuit 225 being connected to pin I of the controller on which the feedback voltage is established. The output of the multiplier is the product the signals derived from the input and from the averaging and error signal circuit.

For comparing the current of the first phase inductor 202 with the threshold. voltage determined by the multiplier, current through. a ground 16 referenced resistor R7 in the source circuit of the first phase transistor switch 210 establishes an input on terminal CS, pin 4, of the controller 175. Pin 4 is connected to the source circuit of the transistor 210 at a point between the transistor 210 and the resistor R7 as shown. The terminal CS is connected to a comparator circuit 226 where the voltage derived from the current through the resistor R7 is compared with a threshold voltage established by the multiplier 222. When the threshold is exceeded by the current sense voltage, the latched drive output is reset to turn off the transistor 210.

In the Motorola type of power factor controller 175 referenced above, zero current monitoring at pin 5 (zero) normally operates in conjunction with the current sense input at pin 4 to provide a critical mode of operation in which the input at pin 5 initiates a drive output from the controller at pin 7. This occurs when inductor current drops to zero and then terminates the drive output to turn off the switch when the current peak at pin 4 exceeds the threshold level established by the multiplier 222.

The present invention does not use current circuitry that provides an input to controller pin 5. Instead, the output of the clock counter 180 is applied to pin 5 to initiate the turning on of the drive output to the master phase transistor 210, any other transistors 212, 214, and 216 being turned on and off by delayed clock signals as slaves of the first phase transistor 210. As explained above, the counter count delays initiation of the next master cycle for several clock counts to assure the discontinuous mode of operation of the transistor switch for the master phase.

In the preferred embodiment, the counter 180 at a predetermined count, provides an output from the logic circuit 186 in the form of a positive going pulse, which preferably extends over a number of count cycles. When the trailing edge of the pulse drops to zero it will be detected by the zero start amplifier 230 which is basically a comparator having a positive bias on its negative input of around one and one-half volts as described in the referenced Motorola. publication for the power factor controller 175. This detection 17 causes the drive output from the controller to turn on transistor 210 and initiate the next master cycle. The width of the pulse from the logic circuitry for the counter output will, as noted above, preferably extend over several clock signals to introduce a delay between master cycles to assure discontinuous operation for the master cycles to assure discontinuous operation for the master and slave phases. Thus, the period between the trailing edges of successive counter pulses is to be greater than the clock pulses that would be needed for critical operation. It will be noted that the phase converters should have essentially the same charge and discharge characteristics to provide good power factor correction, along with being evenly spaced in the master cycle.

It should be understood, that a continuous mode of operation may be obtained if the cycle is such that the master inductor is turned on again before it has time to discharge. As will be appreciated by one in the art, whether the operation is in a continuous or discontinuous mode is a function of various factors including the inductor value, the operating frequency, and the input and output voltages of the converter and that one of ordinary skill in the art would be able to provide a polyphase boost or buck converter operating in accordance with the invention in either one of the other modes.

Also, it is to be noted that the first and second shift registers 178 and 176 have sufficient outputs available to drive eight phases, if desired, and additional shift registers can be cascaded to drive even higher numbers of phases. Such an increased number of phases may be desirable at increased power levels, for example, or in applications where particularly smooth input and output currents are required. From the foregoing it can be seen that the present invention of polyphase operation of switch mode converters is an improvement which operation minimizes ripple currents as well as, as in Figs. 10 and 11, providing an improved power factor correction circuit. In addition, the polyphase switch mode converters disclosed herein may also be advantageously used for power factor correction.

18 Many variations and modifications may be made to the abovedescribed ernbodhnent(s) of the invention without departing substantially from the spirit and principles of the invention. AR such modifications and variations are intended to be included herein within the scope of the present invention.

19

Claims

CLAIMS What is claimed is:

1. A system for converting a voltage, comprising:

a number of boost circuits arranged in a parallel orientation; and a control circuit comprising a power factor correction circuit and at least one delay circuit, wherein the power factor correction circuit and the at least one delay circuit are configured to collectively generate a number of phase signals that are phase shifted with respect to each other, wherein each of the phase signals is applied to a respective one of the boost circuits to drive a corresponding boost circuit output.

2. The system of claim 1, wherein the phase signals generated by the power factor correction circuit and the at least one delay circuit are offset in phase by a predefined phase interval.

3. The system of claim 1, wherein the phase signals generated by the power factor correction circuit and the at least one delay circuit drive the respective boost circuits in a discontinuous mode.

4. The system of claim 1, wherein the phase signals generated by the power factor correction circuit and the at least one delay circuit drive the respective boost circuits in a critical conduction mode.

5. The system of claim 1, wherein one of the phase signals is a master phase signal generated by the power factor correction circuit and at least one of the phase signals is a slave signal generated by the at least one delay circuit.

6. The system of claim 1, wherein each of the boost circuits further comprise:

a switching device having a control input, a power source input, and a switch output, the switch output being electrically coupled to a common; an inductor electrically coupled between an input of the boost circuit and the power source input; and a diode electrically coupled between the power source input and an output of the boost circuit.

7. The system of claim 5, wherein the power factor correction circuit further comprises a master phase output that is electrically coupled to a switching input of one of the boost circuits.

8. The system of claim 5, wherein the at least one delay circuit includes a phase input and at least one slave output, wherein the at least one slave output is electrically coupled to a switching input of a corresponding one of the boost circuits.

9. The system of claim 6, wherein the switching device further comprises an insulated gate bipolar transistor.

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10. A method for converting a voltage, comprising:

a number of boost circuits arranged in a parallel orientation; a power factor correction means for generating a first one of a number of phase signals; and at least one delay means for generating at least one second one of a number of phase signals, the phase signals being phase shifted with respect to each other, wherein each of the phase signals is applied to a respective one of the boost circuits to drive a corresponding boost circuit output.

11. The method of claim 10, further comprising means for offsetting the phase signals by a predefined phase interval.

12. A method for converting a voltage, comprising the steps of electrically coupling a number of boost circuits in a parallel orientation; collectively generating a number of phase signals with a control circuit comprising a power factor correction circuit and at least one delay circuit, the phase signals being phase shifted with respect to each other, wherein each of the phase signals is applied to a respective one of the boost circuits to drive a corresponding boost circuit output.

13. The method of claim 12, further comprising the step of offsetting the phase signals by a predefined phase interval.

14. The method of claim 12, further comprising the step of driving the respective boost circuits with the phase signals in a discontinuous mode.

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15. The method of claim 12, further comprising the step of driving the respective boost circuits with the phase signals in a critical conduction 5 mode.

16. The method of claim 12, wherein the step of collectively generating a number of phase signals with a control circuit comprising a power factor correction circuit and at least one delay circuit further comprises the steps ofgenerating a master phase signal with the power factor correction circuit; and generating a slave phase signal with the at least one delay circuit.

17. The method of claim 12, further comprising the step of providing the boost circuits, comprising the steps of: providing a switching device having a control input, a power source input, and a switch output, the switch output being electrically coupled to a common; electrically coupling an inductor to an input of the boost circuit and the power source input; and electrically coupling a diode between the power source input and an output of the boost circuit.

18. The method of claim 16, further comprising the step of providing a master phase output from the power factor correction circuit that is electrically coupled to a switching input of one of the boost circuits.

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19. The method of claim 16, further comprising the step of providing a phase input and at least one slave output of the at least one delay circuit, wherein the at least one slave output is electrically coupled to a switching input of a corresponding one of the boost circuits.

20. The method of claim 17, wherein the step of providing a switching device having a control input further comprises the step of 10 providing an insulated gate bipolar transistor.

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