GB2347309A

GB2347309A - Decoding packets of digital data

Info

Publication number: GB2347309A
Application number: GB9929828A
Authority: GB
Inventors: Mark Taunton
Original assignee: Element 14 Inc Great Britain
Current assignee: Broadcom UK Ltd Great Britain
Priority date: 1998-12-16
Filing date: 1999-12-16
Publication date: 2000-08-30
Anticipated expiration: 2019-12-16
Also published as: GB9929828D0; GB2347309B

Abstract

A data decoding system for a stream of packets of digital data is provided using a combination of hardware (2) and software decoding. Hardware (2) is used to compare a packet identifying data, such as a channel identifier, within each received packet with one or more items stored packet identifying data to indicate whether that packet is one that should be decoded or discarded. Packets having matching packet identifying data (i.e meeting a predetermined relationship) are stored into a packet memory together with decode assisting information associated with those packets. The decode assisting information and the packets are then used together by a processor performing software decoding.

Description

DECODING PACKETS OF DIGITAL DATA This invention relates to the field of decoding packets of digital data. More particularly, this invention relates to the decoding of a stream of packets of digital data representing multiplexed data channels, each packet including packet identifying data.

It is known to provide systems in which a stream of packets of digital data includes multiplexed data channels. An example of such systems is an MPEG data transmission systems. In these systems the different channels may represent different video images, associated different audio signals and associated different supplementary data. Whilst many such channels can be multiplexed together in a single data stream, the selected channels that are to be decoded from this stream will usually be a sub-set of the total. For example, a user of a set-top television decoder box may select a single video channel with its accompanying audio signal and additional data. The packets required for the decoding need to be picked out from amongst all of the packets in the data stream and directed to an appropriate decoder.

Conventional devices for such decoding use a hardware demultiplexer that examines the channel identifier within each packet and if it matches one of the selected channels directs it to the appropriate one of a video decoder, an audio decoder or an additional data decoder. Packets with channel identifiers not matching any of the selected channels are discarded.

It is strongly desirable that the decoder devices should be inexpensive and readily capable of modification for different uses and/or updating as the surrounding technology advances. The demultiplexer of the type discussed above that physically switches each packet to the appropriate hardware decoder are relatively complex to produce and difficult to modify.

Viewed from one aspect the present invention provides apparatus for decoding a stream of packets of digital data representing multiplexed data channels, each packet including packet identifying data, said apparatus comprising: a packet identifying data memory for storing packet identifying data of those packets required for decoding; a storage control circuit for comparing packet identifying data of received packets with said packet identifying data stored in said packet identifying data memory; a packet memory for storing those received packets having packet identifying data having a predetermined relationship with packet identifying data stored in said packet identifying data memory, those received packets not having said predetermined relationship with packet identifying data stored in said packet identifying data memory not being stored in said packet memory; said storage control circuit storing additional decode assisting information in association with each packet stored in said packet memory; and a processor for performing software decoding of said packets stored within said packet memory using said decode assisting information.

The present invention adopts a different approach to the selection and processing of desired packets. Hardware is provided that examines packet identifying data (e. g. the channel identifier and other identifying data) of each packet received against a list of selected packet identifying data which it is looking for and if there is a match (i. e. a predetermined relationship is met) stores the packet into a packet memory. If there is no match then the packet is rejected. All packets that match are placed into the packet memory and no attempt is made to demultiplex them or pass them to separate decoding devices for their respective channels. In addition to storing the packets within the packet memory, decode assisting information is associated with each packet. This decode assisting information is produced by the hardware matching portion of the apparatus and is then used by the processor performing software decoding, during the decoding process. The decode assisting information that is added by the hardware portion can significantly increase the efficiency of the software decoding enabling less expensive and more capable devices to be produced.

The hardware portion that merely either accepts or rejects each packet but does not attempt to demultiplex the accepted packets provides a highly flexible arrangement (e. g. variable number and mix of channels) allowing for future modification whilst reducing memory requirements by avoiding any need to store unwanted packets.

The decode assisting information can take many different forms. In preferred embodiments said decode assisting information includes a match value indicative of which location within said packet identifying data memory matched the received packet and therefore caused storage of the received packet into said packet memory.

Including a match value indicative of the location within the packet identifying data memory that gave rise to the match enables a more rapid and efficient later selection of the appropriate decoding software for that packet to be made. A match value can be very much shorter than the full packet identifying data and so the software processing of such match values is quicker and less complicated.

A further example of decode assisting information is that in which said decode assisting information includes an added time stamp value indicative of a time at which that packet was received.

Placing a time stamp with each packet enables the appropriate ordering of the receipt of the packets to be maintained and examined and also allows the time stamp to be used for various diagnostic and control purposes.

In some systems the packets received include embedded time stamps. These embedded time stamps give an indication of the master time associated with each packet. By comparing these embedded time stamps with the associated added time stamps within the decode assisting information, the local clock of the decoding device may be adjusted to remain in synchronism with the master time.

In this context, preferred embodiments are ones in which said added time stamp is of a fixed bit-width and a variable precision such that depending upon the precision being used the wrap spacing and the resolution of the added time stamp value vary.

An embedded time stamp will typically have a relatively large number of bits.

Such a large number of bits are not in practice required in most circumstances and a saving in storage capacity may be made by making the added time stamp have a smaller bit width. The requirements of a particular environment may also be better matched with the use of variable precision whereby the available bit space within the added time stamp is allocated to record time in a manner with a variable precision and corresponding variable wrap spacing. In a highly stable environment where tight control of timing is provided greater precision may be usefully stored without encountering problems due to the reduced wrap spacing. Alternatively, in an environment with lower stability (less tight control of timing), then extra precision is not useful and a gain may be made by increasing the wrap spacing.

A further use of the decode assisting information is that in which said decode assisting information includes a validity value indicative of whether that packet contains valid data.

Using the hardware portion of the device to provide an assessment of validity allows more rapid processing using software to occur. This is particularly useful as the vast majority of received packets will be error free and so reducing the error checking overhead for the software decoding will be strongly advantageous. One way of further reducing the software overhead is to concatenate the various validity conditions into a single bit with only this single bit needing to be checked to determine if the packet is valid. If a packet is invalid, then a more elaborate fault handling routines may be entered.

Using a single bit to indicate validity or invalidity also has the advantage that in circumstances in which the packet is valid, the bits that would otherwise be used to indicate particular types of invalidity may instead be used for other purposes.

The packet identifying data could be within any portion of each packet.

However, the packet identifying data is preferably within a header portion of a packet.

In order to increase the flexibility of possible uses of the decoding device for different protocols and systems it is desirable that the decoder should read the header in a flexible manner that at least includes the packet identifying data. Flexibility may be further increased by the use of mask values when comparing the packet identifying data of received packets with those of the desired packet identifying data.

For example, if the number of channels to be received is more than the number of entries in the packet identifying data memory, it may still be possible to achieve this by combining similar packet identifying data values into a single entry and masking out those bit in which the channel identifiers differ. In this case, software would have to perform a little extra work to distinguish the received packets by using the bits from the header of the packet as stored.

Alternatively there are situations where packets may need to be distinguished using more than just the channel identifier. For example, in MPEG transport streams a sequence of packets containing say video data for a channel (A) may also include in a few of the packets timing information applicable to some other video channel (B). If it is desired to receive only channel (B) plus the timing information from channel (A), this can be achieved by unmasking not only the channel identifier from the header for packets of channel (A) but also the bits in the header which indicate the presence of timing information. The combination of mask and packet identifying data would then be set so as to receive only those packets of channel (A) that contained the timing information.

Having selected the packets to be stored in the packet memory, a desirable way of efficiently storing them is to use a linked-list structure within the packet memory.

This enables good use to be made of the storage capacity of the packet memory whilst coping with the variable rates at which packets may be stored into the memory and cleared from the memory.

The packets may be efficiently stored into the packet memory in vacant locations as a linked-list in the order of receipt. Once stored in the packet memory the packets may be processed by the processor acting under software control to separate them into separate linked-lists for each different channel identifier. This process is assisted using the decode assisting information.

It will be appreciated that the different channels could represent many different data types. The invention is particularly useful when the channels represent one of a video channel, an audio channel and a data channel. The data stream could be a stream of MPEG transport packets or may alternatively be a stream of ATM cells.

Viewed from another aspect the present invention provides a method of decoding a stream of packets of digital data representing multiplexed data channels, each packet including a packet identifying data, said method comprising: storing packet identifying data of those packets required for decoding; comparing packet identifying data of received packets with said stored packet identifyingdata; storing those received packets having packet identifying data having a predetermined relationship with said stored packet identifying data, those received packets not having said predetermined relationship with said stored packet identifying data not being stored; storing additional decode assisting information in association with each stored packet; and performing software controlled decoding of said stored packets using said decode assisting information.

An embodiment of the invention will now be described, by way of example only, with reference to the accompanying drawings in which: Figure 1 schematically illustrates a portion of a decoding apparatus that uses hardware to select or reject a packet; Figure 2 illustrates a storage control circuit of the device of Figure 1 in more detail; and Figure 3 illustrates linked-list data storage structures within a packet memory.

Figure 1 shows a hardware portion 2 of an apparatus for decoding a stream of packets of digital data. The digital data is received on a data channel 4.

Accompanying the packet data are various synchronization, error and validity signals as well as a receiving clock signal. The received data packet is buffered within a FIFO memory 6 and passed in parallel to a packet filter 8 which performs part of the job of the storage control circuit by comparing the channel identifier and any other identifiers (e. g. a flag indicating the packet contains desired timing information even though the channel itself is not selected for full decoding) within the received packet with a pre-stored set of channel identifiers The channel identifiers and other flags form the packet identifying data. What follows discusses channel identifiers as the packet identifying data, but the general concept is not limited to this. If a match in the channel identifiers is detected by the packet filter 8, then an accept signal is issued to a gate circuit 10 which allows the packet data buffered within the FIFO memory 6 to proceed to the FIFO memory 12. If an accept signal is not generated, then the packet data buffered within the FIFO memory 6 is discarded.

When the packet filter 8 detects a match, it passes a 5-bit signal indicating which of its 32 potential channel identifier storage locations resulted in the match to a decode assisting information assembly block 14. The decode assisting information assembly block 14 uses this match value information (Match ID) together with a time stamp value from a counter 16 and validity data from an initial network receiver 18 to assemble the decode assisting information that is added to the packet held in the FIFO memory 12. The adding of this decode assisting information takes place within a formatting unit 20. The output from the formatting unit 20 passes to a further FIFO memory 22 before being written to a packet memory (not illustrated).

The time stamp data added to the decode assisting information comprises a 20bit time value. Embedded time values (which may be in channels other than those primarily selected for decoding, but can nevertheless have the appropriate packets captured for use) within the data stream (such as an MPEG or ATM data stream) will typically have a greater bit-width. This does not cause a problem providing the software that decodes the added time stamps is able to cope with the relevant wrap spacing. In order to adjust the resolution of the time stamp values added to match the circumstances, a pre-scalar unit 24 modifies the reference clock signals applied to the counter 16 such that the time stamp is scaled so that its least significant bit represents an appropriate time resolution for the circumstances involved.

The validity bits from the initial network receiver 18 may be processed by the decode assisting information assembly block 14 to be represented by a single bit in the leading position of the decode assisting information that indicates whether or not any invalidity condition is present. This single leading bit can be detected by a relatively quick software test (e. g. a sign determination). If an error is present, then further flags may be set within the decode assisting information to indicate what type of error is present. If an error is not present, then these bit positions can be used for other purposes, e. g. to increase the number of possible Match ID values.

Figure 2 illustrates a portion of the storage control circuit that performs the determination of whether the desired predetermined relationship exists between the received packet identifying data and that stored to indicate that it is required. The data stream is received within a discard/hold circuit 26 and a counter 28 is used to identify when the header portion of a packet has been reached and latched. When this header portion is present within the discard/hold circuit 26, then it is passed to a matching circuit 30. The matching circuit 30 in turn compares the latched value with the channel identifier values stored within various channel identifier storage locations 32.

An entry counter 34 indicates how many channel identifiers are stored within the storage locations 32 such that unnecessary comparisons with empty channel identifier locations are not made. If a match occurs, then the match circuit 30 issues an accept signal to the gate circuit 10. At the same time, the match circuit 30 outputs the Match ID indicating which of the channel identifier storage locations 32 gave rise to the match. As the software control decoding that occurs later can be passed information indicating what type of decoder is required for each channel identifier storage location, then this short Match ID value can be used to select the required software decoder rather than relying upon a full re-examination of the channel identifier.

Figure 3 illustrates the manner in which the data output from the FIFO memory 22 is stored as a linked-list structure within the packet memory prior to software control decoding. When the data is received and written into the packet memory it is stored as a linked-list at vacant locations in the order in which it was received. This order could for example include interleaved video and audio packets.

As a later process, the as received linked-list data is parsed by the processor operating under software control and the Match IDs used to identify whether each packet is a video or an audio packet. These can then be re-linked into separate linkedlists. As a further stage, the separated video and audio linked lists can then be processed by appropriate decoding software operating on a general purpose processor.

Claims

CLAIMS 1. Apparatus for decoding a stream of packets of digital data representing multiplexed data channels, each packet including packet identifying data, said apparatus comprising : a packet identifying data memory for storing packet identifying data of those packets required for decoding; a storage control circuit for comparing packet identifying data of received packets with said packet identifying data stored in said packet identifying data memory; a packet memory for storing those received packets having packet identifying data having a predetermined relationship with packet identifying data stored in said packet identifying data memory, those received packets not having said predetermined relationship with packet identifying data stored in said packet identifying data memory not being stored in said packet memory; said storage control circuit storing additional decode assisting information in association with each packet stored in said packet memory; and a processor for performing software decoding of said packets stored within said packet memory using said decode assisting information.
2. Apparatus as claimed in claim 1, wherein said decode assisting information includes a match value indicative of which location within said packet identifying data memory matched the received packet and therefore caused storage of the received packet into said packet memory.
3. Apparatus as claimed in any one of claims 1 and 2, wherein said decode assisting information includes an added time stamp value indicative of a time at which that packet was received.
4. Apparatus as claimed in claim 3, wherein at least some packets received by said apparatus include an embedded time stamp value.
5. Apparatus as claimed in claim 4, wherein said embedded time stamp value has a greater bit-width than said added time stamp value.
6. Apparatus as claimed in any one of claims 3,4 and 5, wherein said added time stamp is of a fixed bit-width and a variable precision such that depending upon the precision being used the wrap spacing and the resolution of the added time stamp value vary.
7. Apparatus as claimed in any one of the preceding claims, wherein said decode assisting information includes a validity value indicative of whether that packet contains valid data.
8. Apparatus as claimed in claim 7, wherein said validity value is a single bit indicative of the presence of one or more invalidity conditions for that packet.
9. Apparatus as claimed in claim 8, wherein when said validity value indicates that a packet is invalid, then said decode assisting information includes further validity flags indicating the nature of said invalidity and when said validity value indicates that a packet is valid, then said decode assisting information does not includes said further validity flags with the bit-space corresponding to said further validity flags being used to represent different information.
10. Apparatus as claimed in any one of the preceding claims, wherein each packet includes a header portion containing said packet identifying data.
11. Apparatus as claimed in claim 10, wherein said storage control circuit compares at least a portion of each header with said packet identifying data stored in said packet identifying data memory.
12. Apparatus as claimed in any one of claims 10 and 11, wherein said header includes a channel identifier and other flags.
13. Apparatus as claimed in any one of claims 11 and 12, wherein said comparison is subject to a bit-masking operation using mask values stored in said packet identifying data memory.
14. Apparatus as claimed in any one of the preceding claims, wherein said packets are stored in said packet memory in a linked-list structure.
15. Apparatus as claimed in claim 14, wherein said storage control circuit stores said packets into said packet memory as a linked-list in order of receipt.
16 Apparatus as claimed in claim 15, wherein said processor re-sorts said linkedlist stored by said storage control circuit into separate linked-lists for each stored packet identifying data using said decode assisting information.
17. Apparatus as claimed in any one of the preceding claims, wherein said packet identifying data includes at least a channel identifier.
18. Apparatus as claimed in claim 17, wherein said channel identifiers correspond to at least one of : a video channel, an audio channel and a data channel.
19. Apparatus as claimed in any one of the preceding claims, wherein said stream of packets of digital data is an MPEG data stream.
20. Apparatus as claimed in any one of claims I to 17, wherein said stream of packets of digital data is an ATM data stream.
21. A method of decoding a stream of packets of digital data representing multiplexed data channels, each packet including a packet identifying data, said method comprising: storing packet identifying data of those packets required for decoding; comparing packet identifying data of received packets with said stored packet identifyingdata; storing those received packets having packet identifying data having a predetermined relationship with said stored packet identifying data, those received packets not having said predetermined relationship with said stored packet identifying data not being stored; storing additional decode assisting information in association with each stored packet; and performing software controlled decoding of said stored packets using said decode assisting information.
22. Apparatus for decoding substantially as hereinbefore described with reference to the accompanying drawings.
23. A method of decoding substantially as hereinbefore described with reference to the accompany drawings.