GB2346725B - Programmable logic device with hierarchical interconnection resources - Google Patents

Programmable logic device with hierarchical interconnection resources

Info

Publication number
GB2346725B
GB2346725B GB0011200A GB0011200A GB2346725B GB 2346725 B GB2346725 B GB 2346725B GB 0011200 A GB0011200 A GB 0011200A GB 0011200 A GB0011200 A GB 0011200A GB 2346725 B GB2346725 B GB 2346725B
Authority
GB
United Kingdom
Prior art keywords
programmable logic
logic device
interconnection resources
hierarchical interconnection
hierarchical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0011200A
Other versions
GB0011200D0 (en
GB2346725A (en
Inventor
Srinivas T Reddy
Richard G Cliff
Christopher F Lane
Ketan H Zaveri
Manual M Mejia
Bruce B Pederson
David E Jefferson
Any L Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Altera Corp
Original Assignee
Altera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/855,192 external-priority patent/US5977793A/en
Application filed by Altera Corp filed Critical Altera Corp
Publication of GB0011200D0 publication Critical patent/GB0011200D0/en
Publication of GB2346725A publication Critical patent/GB2346725A/en
Application granted granted Critical
Publication of GB2346725B publication Critical patent/GB2346725B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
GB0011200A 1996-10-10 1997-09-26 Programmable logic device with hierarchical interconnection resources Expired - Fee Related GB2346725B (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US2820696P 1996-10-10 1996-10-10
US3781597P 1997-02-05 1997-02-05
US08/855,192 US5977793A (en) 1996-10-10 1997-05-13 Programmable logic device with hierarchical interconnection resources
GB9720543A GB2318199B (en) 1996-10-10 1997-09-26 Programmable logic device with hierarchical interconnection resources

Publications (3)

Publication Number Publication Date
GB0011200D0 GB0011200D0 (en) 2000-06-28
GB2346725A GB2346725A (en) 2000-08-16
GB2346725B true GB2346725B (en) 2000-12-13

Family

ID=27451706

Family Applications (2)

Application Number Title Priority Date Filing Date
GB0011195A Expired - Fee Related GB2346724B (en) 1996-10-10 1997-09-26 Programmable logic devices
GB0011200A Expired - Fee Related GB2346725B (en) 1996-10-10 1997-09-26 Programmable logic device with hierarchical interconnection resources

Family Applications Before (1)

Application Number Title Priority Date Filing Date
GB0011195A Expired - Fee Related GB2346724B (en) 1996-10-10 1997-09-26 Programmable logic devices

Country Status (1)

Country Link
GB (2) GB2346724B (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5455525A (en) * 1993-12-06 1995-10-03 Intelligent Logic Systems, Inc. Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array
US5541530A (en) * 1995-05-17 1996-07-30 Altera Corporation Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4695740A (en) * 1984-09-26 1987-09-22 Xilinx, Inc. Bidirectional buffer amplifier
US5583452A (en) * 1995-10-26 1996-12-10 Xilinx, Inc. Tri-directional buffer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5455525A (en) * 1993-12-06 1995-10-03 Intelligent Logic Systems, Inc. Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array
US5541530A (en) * 1995-05-17 1996-07-30 Altera Corporation Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks

Also Published As

Publication number Publication date
GB0011200D0 (en) 2000-06-28
GB0011195D0 (en) 2000-06-28
GB2346724B (en) 2000-12-06
GB2346725A (en) 2000-08-16
GB2346724A (en) 2000-08-16

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20080926