GB2342016A - Interfacing digital signals - Google Patents

Abstract

A digital data output stage having a data scrambler for scrambling an input digital signal to generate an output digital signal, comprises: a pseudorandom processor for generating a pseudorandom digital signal from the output digital signal; and logic for combining the input digital signal with the pseudorandom digital signal to generate the output digital signal. A complementary descrambler is also disclosed.

Description

2342016 INTERFACING DIGITAL SIGNALS This invention relates to interfacing

digital signals such as, for example, digital audio signals.

Several signal interface formats exist for defining the way in which digital signals are carried (e.g. by cables) from one place to another. Examples include the AESIEBU standard for audio signals, and the so-called "SDI" standard for audio/video sianals.

These interface formats take into account the physical properties of the signal to be transmitted, such as its bit rate or bandwidth, the identification of components of the transmitted signal, such as the identification of different audio channels within a signal formed of multiple channels, and synchronisation of the received signals so that they can be correctly decoded.

In the case of one-bit digital audio signals, a particular problem must be addressed, which is the fact that a one-bit digital audio signal has frequency components which are correlated with those of the corresponding analogue audio signal. This is a particular problem in a studio environment for example, where a onebit digital audio signal carried between pieces of by apparatus can picked up as electromagnetic interference by other apparatus or nearby signal cables. This can result in the subjectively disturbing situation whereby the background noise on one audio signal is discernible as a different audio signal. In extreme cases, a signal source (such as a microphone) could pick-up interference from the one-bit digital audio signal representing that source's own output, leading to potential feedback problems.

To address these problems, a system of scrambling or decorrelating a onebit tn audio signal for transmission has been proposed, with a corresponding descrambling process taking place on reception of the scrambled signal. An example of this process c C> is described in GB-A-2 3 19 922 which uses a convolutional randomising encoder to decorrelate the one-bit signal from the corresponding analogue audio signal, with a t 0 In corresponding decoder also being provided to reverse the process.

1:1 This invention provides a digital data output stage having a data scrambler for scrambling an input digital signal to generate an output scrambled digital signal, the => 4-- 0 It> 1 2 data scrambler comprising: a pseudorandom processor for generating a pseudorandom digital signal from the output digital signal; and logic for combining the input digital signal with the pseudorandom digital signal to generate the output digital signal.

The invention recognises that signal scrambling arrangements of the type shown in GB-A-2 319 922 (and a similar type for use with video signals, as described in "The Art of Digital Video", Watkinson, Focal Press, 1990) introduce delays into the C signal path. In general, delays in an audio processing chain are undesirable. Particular examples of the undesirable effects of signal path delays are in a recording studio where a foldback signal is supplied to the performing artist, and in continuity announcement studios for television broadcast, where equipment providing continuity announcements has to be patched in and out of a continuous emission signal feed for transmission.

The invention addresses this problem of unwanted delays by generating the pseudorandom signal from the output of the scrambler. There can then be just the combining logic, which can be as sim le as a single exclusive-OR gate, between the 4n C. p t input to the scrambler (the "input digital signal" referred to above) and the output of the scrambler (the "output digital signal"). In comparison with systems such as that C) shown in GB-A-2 3319 922, where a series of delays used to form the pseudorandom signal form part of the actual signal path, because in the invention the pseuodarandom C generator forms a side processing chain separate from the main signal path, the delay imposed by the scrambler can be reduced dramatically.

This invention also provides a digital data input stage having a data descrambler for descrambling an input scrambled digital signal to generate an output digital signal, the data descrambler comprising: a pseudorandom processor for generating a pseudorandom digital signal from the input digital signal; and logic for combining the input digital signal with the seudorandom digital signal to generate the 1 P output digital signal.

I I This invention also provides a digital transmission system for transmission of a I digital signal. the system comprising: an output stage as defined above; an input stage 3 as defined above; and a transmission medium linking the output of the output stage to the input of the input stage.

Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which:

Figure I schematically illustrates a digital signal transmission path formed of an output interface stage coupled to an input interface stage; Figure 2 schematically illustrates a scrambler circuit; Figure 3 schematically illustrates a transition generator circuit; Figure 4 schematically illustrates a differentiator circuit; Figure 5 schematically illustrates a descrambler circuit; Figure 6 schematically illustrates a data multiplexer; Figure 7 schematically illustrates a clock generator; and Fiaure 8 schematically illustrates a clock extractor.

Figure I schematically illustrates a digital signal transmission panel forTned of an output interface stage coupled to an input interface stage.

The output interface stage comprises a control and synchronisation generator (10) a multiplexer (20), a data scrambler (30) and a transition generator (40). The output of the transition generator (40) is passed to a transmission line (50) such as a coaxial cable.

At a corresponding input stage at the far end of the transmission line (50) incoming signals are received by a differentiator (60), and are descrambled by a descrambler (70). The output of the descrambler is applied to a clock extractor (80) and a demultiplexer (90) which demultiplexes the various different signals in accordance with clock information supplied by the clock extractor. At the output of the demultiplexer n audio channels are output together with control information giving details of the audio channels and timing and synchronisation information to do with them.

Of the parts described above, the scrambler, transition generator, descrambler and differentiator will be described below with reference to Figures 2 to 5. The multiplexing and corresponding de-multiplexing operations will be described with reference to Figure I I 4 6. Finally, the clock generation and clock extraction systems will be described with reference to Figures 7 and 8.

Figure 2 schematically illustrates the data scrambler 30. The scrambler is intended to decorrelate data to be transmitted along the cable 50 from the data as input to the apparatus, and in particular serves to decorrelate any one-bit audio signals present in the bit stream from analogue representations of the same audio signals, thereby avoiding pick-up problems.

The input to the scrambler, signal V, is supplied to an exclusive-OR gate where it is combined with a pseudorandom digital signal to generate an output signal W.

The pseudorandom digital signal is in turn generated by combining two delayed r versions of W, delayed by 5 and 9 bit periods respectively, in an exclusive-OR gate I 10.

So, the following expression can be used:

1 W=VW1V9 where indicates an exclusive-OR operation and P"' signifies signal P delayed by n bit periods.

Figure 3 illustrates the transition generator 40 which acts using known techniques to remove a polarity dependence from the transmitted data stream. The transition detector comprises a single delay unit 120 and an exclusive-OR gate 130 so as to implement the function:

X = W)C1 In corresponding fashion, the differentiator 60 receives the signal X and, using a C single delay unit 140 and an exclusive-OR gate 150, implements the function:

Y = X X_ I The data descrambler 70 operates in a substantially complementary manner to that of the scrambler 330, to recombine the received signal Y with a pseudorandom bit W sequence derived from Y, so as to implement the function:

Z=YY-5Y-9 So, the signal Z should then be identical to the signal V originally supplied to the scrambler ') 0.

The operation of the data multiplexer 20 will now be described, but first, reference will be made to some of the characteristics of data to be transmitted using the present system.

Data channels are defined as 1ndividual Bitstreams" or IBs. Each IB has a bit rate of 64 x 44.1 kHz, i.e. 2822400 bits per second. This means that an IB can represent a one-bit digital audio signal operating at a sampling rate of 64 x 44.1 kHz (referred to as "64fs'), an AES/EBU channel where 64 bits are used to encode audio data at a sampling rate of 44.1 kHz, or any other signal at this bit rate.

IBs are identified by a number within a sequence of IBs (from 0 to NIB, the total number of IBs), and by an IB type (a. code from 0 to 127). At least two IBs are transmitted, with IB 0 being a control channel, while IBs 1 to n are available for carrying data.

The different IB types will now be listed.

Type 0.

IB 0 is always of Type 0 and no other IB is ever of Type 0. The presence of a Type 0 IB thus allows for the synchronisation of the receiver demultiplexing circuitry. The detection of a Type 0 bitstream may thus be used as an indication of correct reception of a Signal according to the present format. The lack of reception of a Type 0 bitstrearn C may be used as a reliable indicator of the lack of a Signal according to the present format (or the lack of synchronisation to an input Signal according to the present format) and the consequent requirement to mute any output signal derived from reception of a Signal according to the present format.

A Type 0 bitstrearn (and hence IB 0) has a repeating structure of 64 bits numbered from 0 to 63. Bits 2-633 inclusive are at present undefined, and bits 0 and 1 will now be described.

Ty e 0 Bit 0 (PISYNC).

p Type 0 Bit 0 (referred to as P 1 SYNC) recurs at the IB data rate divided by 64 or 2822400/64 which is 44100 bits/second. Thus the PCT clock rate of 44.1 kHz may be transmitted through the present interface by synchronising the generation of P 1 SYNC to Z) C1 6 an incoming 44.1 kHz clock and by generating at the receiver a 44.1 kHz clock synchronised to the arrival of P 1 SYNC.

It is the structure of P1SYNC which allows for the synchronisation of the receiver and the demultiplexing and decoding of the component IBs.

The overhead of one IB imposed-by the format implies a 33% overhead for a two channel interface, an overhead of 14% for a six channel interface and an overhead of 1.75% for a 56 channel interface. These figures compare with the 62.5% overhead of the AES/EBU two channel interface or the 40% overhead of the MADI 56 channel interface.

Type 0 Bit 1 (P I CTRL).

Type 0 Bit 1 (referred to as P 1 CTRL) carries control information, specifically the types of all the IBs in the present use of the present interface.

The Type of each IB is encoded in an 8-bit sequence, a single bit'l' followed by a seven-bit binary number sent MSB first which contains the Type. Since IB 0 is always of Type 0 and only one IB may be of Type 0 the binary sequence of seven zeros "0000000" can only occur at one point in PICTRL and serves as a synchronisation mark for the decoding of P 1 CTRL. The Type of each IB is sent in sequence. It is legal for more Type information to be transmitted in PICTRL than is required by the presently used NIB, such excess Type information should follow the Type information for the used IBs and be of Type 127.

Type 1 An IB of Type 1 is the first (and possibly only) IB of an individual high- sample rate audio signal. A single channel of 64FS (FS=44. I kHz) single bit audio data is carried 0 C) by a single IB of Type 1. The numerical significance of the bits sent in a Type 1 IB is 1.

Type 2 An IB of Type 2 is the second or subsequent of two or more 1Bs used to carry multiple bits of the same signal (i.e. a signal having a data rate of more than 2822400 bits 0 C 3 0 per second can be multiplexed onto two or more IBs). The significance of a Type 2 IB is 7 the same as that of the previous IB. Thus two single bit outputs from a dual 64FS ADC (both having the same polarity), or of a temary representation, might be carried by a sequence of two IBs of Types 1 and 2.

Type 3 An IB of Type 3 is the second or subsequent of two or more IBs used to carry multiple bits of the same signal. The significance of a Type 3 IB is twice that of the previous IB. Thus the output of a three bit ADC operating at 64FS, would be carried by an LSB first sequence of three IBs of Types 1, 3 and 3. 10 Type 4 An IB of Type 4 is the first IB of a second (or subsequent) set of bits used to carry the same sig 0 gnal. A Type 4 IB always has a significance of one. Thus the output of two three bit ADCs operating in parallel on the same analogue signal and considered to be part of a single 64Fs digital signal, would be carried by a sequence of six IBs of Types 1, 3, 3, 4, 3 and 3.

Type 5 An IB of Type 5 is the first IB of a second (or subsequent) set of bits used to 20 carry the same signal. A Type 5 IB always has a significance of minus one. Thus the 0 output of two one bit ADCs operating differentially on the same analogue signal and considered to be part of a single 64Fs digital signal, would be carried by a sequence of 0 two 1Bs of Types 1 and 5. The output of two three bit ADCs operating differentially on the same analogue signal and considered to be part of a single 64Fs digital signal, would 0 C> be carried by a sequence of six IBs of Types 1, 33, 3, 5, 3 and -3 3.

Type 6 An IB of Type 6 begins a second (or subsequent) sample occupying a 64FS timeslot. A Type 6 IB always has a significance of one. Thus a 128FS signal would be 0 0 carried by a sequence of two 1Bs of Types 1 and 6. A 256Fs signal would be a sequence C> of Types 1, 6, 6 and 6. A pair of one bit ADCs acting differentially at 128FS used to represent a single signal would be 1, 5, 6, and 5. It is normally that the sequence of Types following a Type 6 IB will be the same as that following the previous Type 1 or Type 6 IB. This assures that each sample of the signal is represented in the same way.

A summary of Types 1 to 6

The properties of these Types may be summarised as follows.

Type Significance Action 1 1 Starts new signal 2 As previous 3 Twice previous 4 1 -1 6 Increases sample rate by 64FS The intention of Types 1 to 6 is to allow the carriage of signals at 64FS or integer multiples thereof using unary, binary and/or differential representations.

Types 7 to 31 20 IBs of these types are at present undefined.

Type32 An IB of Type 32 carries AES/EBU two channel (64 bit) PCM data. Only the 44.1 kHz sampling rate of AES/EBU is supported. A Type 32 bitstream has a repeating structure of 64 bits numbered from 0 to 613). As noted above, Bit 0 of a Type 3)2 IB will be in synchronism with Bit 0 of IB 0 (IPSYNC).

The mapping from the AES/EBU format (including preambles, sync etc) is as 0 follows. Note that this mapping takes advantage of the fact that the position of the start of the 64-bit frame is known.

9 Bits 4-31 and bits 36-63 of a Type 32 IB are identical to the same bits in the AES/EBU interface. Only bits 0-3 and 32-35 differ in that they carry an encoding of the AES/EBU preamble types. The rules used to encode the AESIEBU preambles are as follows. 5 Preamble Type Channel B iphase Mark Encoded Preamble X A 111000 10 or 000 11101 0010 Y B 11100100 or 00011011 0100 z A/Block Start 11101000 or 00010111 1000 Types 33 to 62 IBs of these types are at present undefined.

Type63 Type 63 simply marks an unused IB. 15 Type64 Type 64 is undefined.

Types 65 to 126 An IB of Type 65 to 126 marks a muted IB of the type whose value is 64 less than the type under consideration. The bit of significance 64 in the Type number simply indicates "Muted". The implied Type information (held in the lower 6 bits of Type) may however be used by the receiving circuitry to prepare the appropriate output (and any 5 equipment fed from it) to receive information of that type.

The effect of a Type greater than 64 is to allow the type of an IB to be changed without producing unwanted noises at the output of the receiver, for instance from Type 1 to type 32 via the sequence 1 -> 65 -> 96 -> 32. This sequence induces the following. action in the receiver:- Type Action 1 Audio signal at 64FS transmitted.

Receiver mutes 64FS output.

96 Receiver changes output mode to AES/EBU, muted.

32 Receiver un-mutes AES/EBU output.

Type 127 Type 127 simply marks an unused IB.

So, each bitstream. supplied to the multiplexer 30 has an associated IB type and an associated IB number from 1 to NIB. The type 0 IB (i.e. IB 0) is generated by the control generator 10.

Referring now to Figure 6, a bitclock 200 is provided or generated, having a clock rate equal to NIB x 64 x 44100. In the example of Figure 6, NIB is 4 so the bitclock is at 11.2896 MHz. The bitclock is supplied to a divider 210 where it is divided by NIB. The divider 210 generates two outputs: one is an IB bitclock 220 at 2.8224 t> MVIz, and the other is a multiplex control signal 2-30 which counts cyclically from 0 to NIB at the rate of the bitclock 200.

The IB bitclock is supplied to a ftirther divider 240 where it is divided by 64 to generate a 44.1 kHz clock 250 and, as before, a six-bit multiplex control signal 260 which counts cyclically ftom 0 to 63 at the rate of the IB clock 220.

The 44.1 kHz clock is then supplied to another divider 270 where it is divided by 8 to generate a 5512.5 kHz clock 280 and a three-bit multiplex control signal 290 which counts cyclically from 0 to 7 at the rate of the 44.1 kHz clock.

Finally, the 5512,5 kHz clock 280 is divided by NIB to form a two-bit multiplex control signal 300 which counts cyclically from 0 to NIB at the rate of the 5512.5 kHz clock.

Seven bit data specifying the IB types is received by an NIB-way multiplexer 3 10 which cycles through the set of four NIB types. In this example, there are four IBs: a type 0 (control) IB, two type 1 IBs carrying one-bit digital audio data (so-called 'DSD 0 0 data) and a type 32 IB carrying a multiplexed AES/EBU PCM signal.

The output of the multiplexer 33 10 is passed to another multiplexer 3320 where the seven bit words specifying the IB types are serialised, with a 1 being inserted at every eighth bit. These are passed to a fizlher multiplexer 330 as bit one of IB 0, i.e. PICTRI, referred to above. PISYNC is supplied to the multiplexer 330 to form bit 0 of IB 0. The remaining bits of IB 0 are at present undefined, but would be added in at the multiplexer 330. The multiplexer 330 has the effect of serialising the 64 bits of IB 0.

The serial IB 0 data, together with two type 1 IBs 9Bs 1 and 2) and a serialised 0 version of the AES/EBU audio signal (serialised by a receiver and multiplexer 340) are 0 scrambled and subjected to a transition generator before being supplied to a multiplexer 350 where a serial bitstrearn is formed from all four IBs. Finally, the serial bitstream is scrambled 330 and supplied to the transition generator 40.

In the entire apparatus of Figure 6, a very small delay of perhaps one period of the IB clock is imposed on the data streams.

So, in the output bitstream, every fourth bit comes from the same IB, so the bitstream looks like:

(bit from IB 0) (bit from IB 1) (bit from IB 2) (bit from IB J) (bit from IB 0) 12 Within the bits from an individual IB, these either progress through the received bits as in the case of a continuous DSD signal, or cycle through bits 0 to 63) of successive words in the case of 64-bit signals such as IB 0 and the AES/EBU signal.

Groups of eight successive bit Is from IB 0 specify the types of the various IBs being transmitted. The type code for IB 0 itself comes first, followed by the type code for IB 1 and so on, cycling through the set of IBs from 0 to NIB. Since the code for IB 0 is unique in that it is the only code to contain seven adjacent zeroes, this can be used at the receiver to synchronise the decoding of the IB types for the remaining IBs.

Figure 7 schematically illustrates a circuit for generating the clock signal 0 P 1 SYNC. It is basically similar to the scrambler circuit described earlier, but is fed from a bit inserter 400. The bit inserter 400 inserts zeroes into the chain of delay units, apart from in a start-up state where a number of ones (e.g. 9 ones) are fed in to avoid an initial lock-up condition.

After the initial start-up condition, the output S of the circuit of Figure 7 may be represented as:

S = S-5 S-9 As described above, the clock signal is multiplexed into the bitstrearn in one bit (bit 0 of IB 0) occurring every (64 x NIB) bits in the bitstream. So, in order to synchronise with the transmitter clock and so decode the received data correctly, at the receiver, a correlation is carried out to detect the presence of the clock signal in each of the NIB 64 possible bit positions using the circuit of Figure 8.

In Figure 8, the incoming bitstream is divided by NIB and by 64, at a bit position C> relative to the rest of the bitstrearn set by a synchronisation controller 500. The output of the division stage, S, is then subjected to processing to generate: S S-5 S-9 If this expression is consistently zero, then the correct bit position for bit 0 of IB 0 has been found, and the remaining IBs can be decoded with respect to that bit position.

The synchronisation controller transmits locking information to the remainder of a receiver circuit which demultiplexes the bitstream in a complementary manner to the apparatus of Figure 6.

If the output S S-5 S-9 is not zero, then the synchronisation controller causes the dividers 5 10 to displace by one bit so that another possible bit position is examined, 5 and so on.

It transpires form the mathematics behind the process that correlation needs to be tested for only about 11 bits before a relatively confident answer can be obtained as to whether the incoming bitstream at that position correlates with the transmitter clock. So, synchronisation can be achieved in a very short time.

14

Claims (1)

1. A digital data output stage having a data scrambler for scrambling an input digital signal to generate an output scrambled digital signal, the data scrambler comprising:

a pseudorandom processor for generating a pseudorandom digital signal from the output digital signal; and logic for combining the input digital signal with the pseudorandom digital signal to generate the output digital signal.

An output stage according to claim 1, in which the pseudorandom processor comprises means for combining at least two versions of the output digital signal, one version being delayed with respect to another version, to generate the pseudorandom CD digital signal.

3. An output stage according to claim 2, in which the pseudorandom processor is operable to combine two versions of the output digital signal, one such version being V delayed by five bit periods with respect to the output digital signal, and the other such version being delayed by nine bit periods with respect to the output digital signal.

4. An output stage according to claim 2 or claim 3, in which the pseudorandom I processor comprises logic operating as an exclusive-OR gate for combining the C, C.

versions of the output digital signal to generate the pseudorandom digital signal.

5. An output stage according to any one of the preceding claims, in which the C> Z:' combining logic operates as an exclusive-OR gate.

CD 1 6. An output stage according to any one of the preceding claims, comprising a 1 0 tl.

transition generator for processing the output digital signal, the transition generator I I C comprising second combining logic for combining the output digital signal with a L_ z:1 C, delayed version of the output of the second combining logic.

I I 7. An output stage according to claim 6, in which the second combining logic operates as an exclusive-OR gate.

8. A digital data input stage having a data descrambler for descrambling an input scrambled digital signal to generate an output digital signal, the data descrambler C comprising: a pseudorandom processor for generating a pseudorandom digital signal from the input digital signal; and logic for combining the input digital signal with the pseudorandom digital signal to generate the output digital signal.

9. An input stage according to claim 8, in which the pseudorandom processor tD t comprises means for combining at least two versions of the input digital signal, one 1 version being delayed with respect to another version, to generate the pseudorandom C) ZP digital signal.

C 10. An input stage according to claim 9, in which the pseudorandom processor is 0 operable to combine two versions of the input digital signal, one such version being delayed by five bit periods with respect to the input digital signal, and the other such version being delayed by nine bit periods with respect to the input digital signal.

11. An input stage according to claim 9 or claim 10, in which the pseudorandom C processor comprises logic operating as an exclusive-OR gate for combining the versions of the input digital signal to generate the pseudorandom digital signal.

12. An input stage according to any one of the preceding claims, in which the C combining logic operates as an exclusive-OR gate.

C) 0 16 13. An input stage according to any one of the preceding claims, comprising a differentiator for pre-processing a received digital signal to form the input digital signal, the transition generator comprising second combining logic for combining the received digital signal with a delayed version of the received digital signal.

14. An input stage according to claim 13, in which the second combining logic operates as an exclusive-OR gate.

15. A digital transmission system for transmission of a digital signal, the system comprising: an output stage according to any one of claims 1 to 7; Z an input stage according to any one of claims 8 to 14; and a transmission medium linking the output of the output stage to the input of the t> input stage. 15 16. A system according to claim 15, in which the digital signal is a one-bit di ital 9 audio signal.

1 17. A digital data output stage substantially as hereinbefore described with CP reference to the accomp,iying drawings.

18. A digital data input stage substantially as hereinbefore described with reference to the accompanying drawings.

t 19. A dicital transmission system substantially as hereinbefore described with 0 reference to the accompanying drawings.

0