GB2341991A

GB2341991A - Apparatus for generating signals of ultra-wide arbitrary frequencies

Info

Publication number: GB2341991A
Application number: GB9820545A
Authority: GB
Inventors: Philip Charles Jarrett Pring
Original assignee: ELETTRONICA
Current assignee: ELETTRONICA
Priority date: 1998-09-21
Filing date: 1998-09-21
Publication date: 2000-03-29
Anticipated expiration: 2018-09-21
Also published as: GB2341991B; GB9820545D0

Abstract

Apparatus 2 for generating electrical signals of ultra-wide arbitrary frequencies comprising impulse generator means 4, for generating signals 50, splitter means 26 for splitting the signals into a plurality of parallel signal paths 28, and combiner means 30 for combining the parallel signal paths. Time delay means 34 and an amplitude weighting 38 means, which may be a scaling means, may be included. There may be a plurality of direct digital synthesizers.

Description

2341991 APPARATUS FOR GMMRATING ELECTRICAL SIGNALS OF ULTRA-WIDE AMI%2ARY

FREOMMCIES This invention relates to apparatus for generating electrical signals of ultra-wide arbitrary frequencies.

Apparatus utilizing direct digital synthesis is known and commonly used to generate electrical signals from low frequencies to hundreds of MHz. In the known apparatus, a clock signal updates sequentially a read address of a digital memory. The read data is passed to a digital-to- analogue converter. The output of the digital - to- analogue converter is filtered to produce an analogue waveform with characteristics defined by source data stored within a digital memory. Waveforms of different shapes and frequencies may be produced by appropriately programming the source data. The maximum output frequency is limited theoretically to half of the system clock frequency. The clock, parts of the memory, and the digital to- analogue converter operate at the clock frequency. Thus the maximum output signal frequency is limited by the slowest of these components.

It is an aim of the present invention to reduce the above problem and improve the maximum output signal frequency.

2 Accordingly, in one non-limiting embodiment of the present invention there is provided apparatus for generating electrical signals of ultrawide arbitrary frequencies, which apparatus comprises -impulse generator means for generating signals, splitter means for splitting the signals into a plurality of signals in parallel signal paths, and combiner means for combining the signals in the parallel signal paths.

In the apparatus of the present invention, the electrical signals are generated by the summation 'of parallel signal channels utilizing the combiner means.

Usually, the impulse generator means will be a single impulse generator.

The apparatus may include time delay means for delaying the signals in the parallel signal paths in time relative to each other.

The apparatus may include amplitude weighting means for weighting the signals in the parallel signal paths in amplitude relative to each other.

Preferably, the amplitude weighting means is a scaling means which enables a predetermined reduction of signal amplitude on the signal amplitude on the signals in each of the parallel signal paths. The scaling means will usually comprise a plurality of scaling devices, one for each signal path.

3 The apparatus may include a plurality of direct digital synthesizers, there being one of the direct digital synthesizers for each one of the scaling devices.

The apparatus may include a master clock f or feeding the direct digital synthesizers and the impulse generator means.

An embodiment of the invention will now be described solely by way of example and with reference to the accompanying drawings in which:

Figure I shows known apparatus for generating electrical signals from low frequencies to hundreds of MHz; and Figure 2 shows apparatus of the invention for generating electrical signals of ultra-wide arbitrary frequencies.

Referring to Figure 1, there is shown apparatus 2 which utilizes the known technique of direct digital synthesis to generate electrical signals from low frequencies to hundreds of NHz. The apparatus 2 comprises a clock 4 which provides clock signals to sequentially update a read address of a digital memory 6. The sequential updating is effected on line 8. Programme memory data is shown schematically being input by arrow 10.

4 The read data is passed to a digital - to- analogue converter 12. A connector 14 bypasses the digital memory 6 as shown. The output from the digital-toanalogue converter 12 passes on line 16 to a low pass filter 18 to produce an analogue waveform with characteristics defined by source data 10 stored within the digital memory 6. Waveforms of different shapes and frequencies may be produced by appropriately programming the source data 10. ' Figure 1 shows the output of the low pass f ilter 18 as an analogue signal 20 of an arbitrary frequency. The maximum output frequency is limited theoretically to half of the frequency of the clock 4. The clock 4, parts of the memory 6, and the digital-to-analogue converter 12 operate at the clock frequency. Thus the maximum signal output frequency is limited by the slowest of the clock 4, the parts of the memory 6, and the digital-to-analogue converter 12.

Referring now to Figure 2, there is shown apparatus 22 for generating electrical signals of ultra-wide arbitrary frequencies. The apparatus 22 comprises impulse generator means 24 for generating signals, splitter means 26 for splitting the signals into a plurality of signals in parallel signal paths 28, and combiner means 30 for combining the signals in the parallel signal paths 28. As can be seen f rom Figure 2, the impulse generator means 24 is a single impulse generator. The splitter means- 26 is an n-way splitter, and the combiner means 30 is an n-way combiner.

The apparatus 22 includes time delay means 32 in the form of a plurality of time delay elements 34 arranged one in each parallel signal path 28. The time delay means 32 is for delaying the signals in the parallel signal paths 28 in time, relative to each other.

The apparatus 22 further includes amplitude weighting means 36 for weighting the signals in the parallel signal paths 28 in amplitude relative to each other. The amplitude weighting means 36 is a scaling means which enables a predetermined reduction of signal amplitude on the signals in each of the parallel signal paths 28. The scaling means comprises a plurality of scaling devices 38, there being one of the scaling devices 38 arranged in each one of the parallel signal paths 28 as shown.

The apparatus 22 includes a plurality of direct digital synthesizers DDSO, DDS1,DDS2.... DDSn as shown. There is one of these direct digital synthesizers for each one of the scaling devices 38.

The apparatus includes a' master clock 40 which feeds the direct digital synthesizers 6 DDSO,DDSI,DDS2.... DDSn via line 42 and which feeds the impulse generator 24 via line 44. The apparatus 22 further comprises a low pass filter 46 providing an output analogue signal shown schematically as output analogue signal 48.

The apparatus 22 operates such that a number 'Inn of direct digital synthesizers DDSO,DDS1,DDS2.... DDSn are operated from the common master clock 40. The master clock 40 also triggers the impulse generator 22 once per clock cycle.

The output of the impulse generator 24 is a single temporarily short burst of signal energy 50 with a temporal duration of at least "n" times less than the period of the master clock 40. The impulse generator output is passed to the splitter means 26 which splits the output from the impulse generator 24 into a plurality of parallel outputs along the parallel signal paths 28. The number 'In" of the parallel signal paths 28 may vary from two parallel signal paths to in excess of 30 parallel signal paths. The number of the parallel signal paths may be an odd number or an even number.

The impulse output on the parallel signal paths 28 each pass to one of the scaling devices 38. The scaling devices 38 may each be a mixer, a variable attenuator, or any other suitable and appropriate 7 scaling device. Each scaling device 38 scales its impulse in amplitude according to the direct digital synthesized signal feeding a port of the scaling device 38 via line 52. The port may be regarded as a second or controlled port.

The scaled impulses travel through the individual time delay elements 34 before they are recombined in the combiner means 30.

The shortest time delay T1 is not critical.

However, the incremental delay between the shortest time delay T1 and the next shortest time delay T2 should be equal to the master clock period divided by the number 'In". Similarly, the increment between T2 and T3 and all other consecutively numbered parallel signal paths 28 should also be equal to the master clock period divided by the number "n". Thus the delay "Tn" is equal to Ti plus the (master clock period multiplied by (n-l)/n). In this way, at the output 54 of the combiner means 30, there are continuous impulse arrivals at a frequency 'In" times greater than the master clock frequency. Since each of the 'In" impulses reaching the combiner means 30 within a master clock cycle is controlled independently in amplitude by its own scaling device 38 and an independently programmed direct digital synthesized channel 52, the output signal update rate 8 is also 'In" times the master clock frequency. Thus the theoretical maximum output signal frequency of the present invention is in enhanced by a factor "n" relative to that of conventional known systems as shown In Figure 1.

It will thus be appreciated that the apparatus 22 operates to facilitate the generation of ultra-wide bandwidth waveforms of arbitrary shape through the use of the direct digital synthesizers DDSO, DDS1, DDS2 DDSn in conjunction with available high frequency devices, to effectively multiply the output sample rate, and therefore the maximum output signal frequency.

It is to be appreciated that the embodiment of the invention described above with reference to Figure 2 has been given by way of example only and that modifications may be effected. Thus, for example, for each impulse, the parallel signal paths 28 between the splitter means 26 and output are linear propagation paths for each particular set of scaling parameters. Thus the order of many components is not critical, and some may be distributed. For example, the output low pass filter 46 may be placed before the splitter means 26, although in practice some filtering would be performed at output 54. Similarly, the time delay elements 34 may represent more properly propagation 9 times along each of the n "scaled" paths inclusively from the splitting means 26 to the combiner means 30 to give maximum flexibility of design for the apparatus.22.

The impulse generator means 24 determines the maximum frequency limit of operation of the apparatus 22. Impulse generator devices such for example as step-recovery diodes may be used to create impulses of around SOPs in duration, building a maximum output effective clock rate of around 20GHz. It may be advisable to choose appropriate devices, or to apply conditioning, in order to limit high frequency components beyond the maximum desired output frequency, in order to reduce the frequency specification of subsequent components.

The scaling devices 38 are required to alter the amplitude of the propagating impulses in response to the direct digital synthesized control input on lines 52. Unbalanced components such for example as fieldeffect transistors or PIN diodes, may be used as programmable attenuators. Alternatively, balanced mixers may be used with the added facility of fourquadrant multiplication permitting the inversion of impulses before re-combination. The above mentioned scaling devices and impulse generator devices may alternatively be implemented using photonic technologies.

Claims

1. Apparatus for generating electrical signals of ultra-wide arbitrary frequencies, which apparatus comprises impulse generator means for generating signals, splitter means for splitting the signals into a plurality of signals in parallel signal paths, and combiner means for combining the signals in the parallel signal paths.

2. Apparatus according to claim 1 in which the impulse generator means is a single impulse generator.

3. Apparatus according to claim 1 or claim 2 and including time delay means for delaying the signals in the parallel signal paths in time relative to each other.

4. Apparatus according to any one of the preceding claims and including amplitude weighting means for weighting the signals in the parallel signal paths in amplitude relative to each other.

5. Apparatus according to claim 4 in which the amplitude weighting means is a scaling means which enables a predetermined reduction of signal amplitude on the signals in each of the parallel signal paths.

6. Apparatus according to claim 5 in which the scaling means comprises a plurality of scaling devices, one for each signal path.

7. Apparatus according to claim 6 and including a plurality of direct digital synthesizers, there being one of the direct digital synthesizers for each one of the scaling devices.

8. Apparatus according to claim 7 and including a master clock for feeding the direct digital synthesizers and the impulse generator means.

9. Apparatus for generating electrical signals of ultra-wide arbitrary frequencies, substantially as herein described with reference to the accompanying drawings.