GB2341058A

GB2341058A - Method for avoiding data loss in a packet switch

Info

Publication number: GB2341058A
Application number: GB9818796A
Authority: GB
Inventors: Robert Geoffrey Wood
Original assignee: Mitel Corp
Current assignee: Microsemi Semiconductor ULC
Priority date: 1998-08-28
Filing date: 1998-08-28
Publication date: 2000-03-01
Also published as: GB9818796D0

Abstract

Packets transmitted over a data bus 14 from an incoming I/O (input/output) port 10a to an outgoing I/O port 10b are also stored in a shadow buffer 46. When the buffer 42 of an output port is full, a detector 44 asserts a buffer overflow error signal informing the shadow buffer controller 48 that the packet should be retained in the shadow buffer for later retransmission to the output port. The buffer overflow detector asserts a buffer available signal when room becomes available in the output port buffer and the packet is then forwarded from the shadow buffer to the port. The shadow buffer acts as a centralized memory resource for temporary storage of data packets which would otherwise be lost during transmission due to a full buffer in the outgoing port. The shadow buffer may be either a first-in-first-out (FIFO) memory or a random access memory (RAM) which may be indexed by an I/O port number.

Description

2341058 METHOD AND APPARATUS FOR AVOIDING DATA LOSS IN A PACKET SWITCH

FIELD OF THE INVENTION

This invention relates in general to data transfer systems and more specifically to an apparatus and metho4 for avoiding data loss in a data transfer system.

BACKGROUND OF THE INVENTION

Data switches are well known in the art for transferring data. Such systems are based upon a plurality of input/output (1/0) ports which transfer data between each other in the form of data packets over a single, shared high speed parallel bus. Data is transferred from an incoming 1/0 port to an outgoing 1/0 port via the high speed bus in the form of packets of fixed length. Access to the data bus by incoming data may be controlled by an arbitration system such as described in LJK Patent Application No. 9724256.4, filed November 17, 1997 entitled Method of Selecting Between Multiple Clock Drive Sources for a Backplane Clock Signal.

In prior art systems, incoming data (in the form of data packets) may be, but are not necessarily, stored in temporary incoming data buffer memory on the incoming input/output (1/0) ports. The data packets are transferred, via the bus, to the appropriate outgoing 1/0 port, where they are temporarfly stored in a memory buffer located on the outgoing 1/0 port until the port is free to transmit the data packets. A problem known as buffer overflow arises when data packets are destined for an outgoing 1/0 port whose data buffer memory is full. In this situation, the data packets cannot be stored in the buffer of the outgoing 1/0 port, and hence are not transmitted to the 1/0 port, therefore resulting in loss and corruption of data.

Numerous efforts have been made to overcome this problem. In Banyan or non-blocking switches, packets which can not be output due to a full output buffer are 2 re-routed through a switch such that output packets which cannot be sent are circulated through the switch between the output and input ports thereof.

In so-called bus architectures, centralized memory is connected to a data bus and is used to temporarily store packets which can not be output due to an output buffer full condition.

US Patent No. 5,233,606 (Pashan et al) discloses a system which replaces a lowest priority cell or data packet with an incoming data packet when there is no room in the buffer memory for the incoming packet. Unfortunately, the replaced lowest priority data packet is often still needed and thus important data might be discarded.

US Patent No. 5,237,564 (Lespagnol et at) describes a frame switching relay which switches fi-ames between input and output paths by multiplexing the paths at the frame cell level.

US Patent No. 5,455,820 (Yamada) discloses an output-buffer switch for implementing asynchronous data transfer. A shortcoming of the system set forth in this patent is that there is no centralized memory in which to store the overflowed data.

Other prior art which addresses the problem of buffer overflow in various switch architectures, is as follows:

US Patent No. 5,079,762 Tanabe US Patent No. 5,446,734 Goldstein US Patent No. 4,692,894 Bemis US Patent No. 5,543,853 Haskell et al.

US Patent No. 4,964,119 Endo et al.

US Patent No. 5,530,698 Kozaki et al.

SUN54ARY OF THE INVENTION 3 According to the present invention, a method is provided for avoiding data loss in a data packet switch during transfer between 1/0 ports. By temporarily storing all data packets in a shadow memory buffer as the data packets are being transmitted to an outgoing 1/0 port, data loss is prevented when the buffer of the outgoing YO port is full and unable to accept the data packets. When the outgoing 1/0 port is able to accept data, the shadow memory buffer retransmits the saved data packet(s) to the outgoing 1/0 port, thereby emptying the shadow memory and completing the data transfer. The system of the present invention decreases the amount of buffer memory required on the outgoing 1/0 ports relative to prior art systems without requiring costly large centralized buffer memories and without loss of switch bandwidth.

BRIEF DESCRIPTION OF THE DRAWINGS

Various embodiments of the present invention are described below with reference to the drawings in which:

Figure I is a block diagram showing a basic system architecture according to the prior art;

Figure 2 is a timing diagram showing the behavior of signals created during data packet transmission by the system architecture of Figure 1; Figure 3 is a representation of the format of a data packet transferred by the system of Figure 1; Figure 4 is a block diagram showing the main functional blocks of the present invention distributed through a system architecture; Figure 5 is a detailed block diagram of a shadow buffer for the system of Figure 4, according to a first embodiment implemented in a FIFO arrangement as a ring buffer; 4 Figures 6a and 6b are state diagrams showing operation of the shadow buffer; Figures 6c and 6d are state diagrams showing operation of the shadow buffer according to an alternative embodiment of the present invention; Figure 7 is a detailed block diagram of a shadow buffer for the system of Figure 4, according to a flifther alternative embodiment; and Figure 8 is a detailed block diagram of a shadow buffer for the system of Figure 4, according to yet another alternative embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

In the illustrative examples appearing herein below to describe the various embodiments of the invention, each data packet is 64 bytes and a 64 bit wide high speed bus is used for data transfer. A maximum of 16 1/0 ports and 16,383 priority levels (channels going through a data switch) are provided. However, it will be appreciated to a person of ordinary skill in the art that the size of the data packets and data bus is immaterial to the substance of the invention.

Turning to Figure 1, the basic architecture of a simple bus system is shown where N represents the number of 1/0 ports 10 (i.e. N= 16 in the present example).

The 1/0 ports 10 are connected to each other and a central controller 12 via a data bus 14, a timing bus 16 and a status signal bus 18. The central controller 12 is utilized to control, monitor and maintain the 1/0 ports 10. The 1/0 ports 10 tramfer data packets over the data bus 14 during a discrete time period which is defined by a transfer time signal sent over the timing bus 16. Error and status signals are sent over the status signal bus 18 to inform the 1/0 ports 10 and central controller 12 of the status of each data transfer.

Figure 2 shows the behavior of signals on busses 14, 16 and 18. The Transfer Time signal is a reference timing signal for defining each data packet transfer time, from which the Clock signal that drives the timing bus 16 is derived. The data packet transfer cycles are indicated by the Data Transfer Cycle signal. Figure 2 shows the transfer of three consecutive packets M, N and 0. Three status signals (Status-1, Status-2 and Status-3) are transmitted on status signal bus 18 at predetermined times during a packet transfer cycle. The status signal bus 18 is connected in a wired-OR configuration to the 1/0 ports 10 so that only one port 10 may drive the status signals at any instant. Either the source or destination 1/0 ports, or a third device, which monitors the bus IS can drive the status signals.

The Status-1 signal can only be driven after the completion of a data packet across the bus 14. Status_1 may represent, for example, a BIT_ERROR signal.

The Status-2 signal may be driven at any time during the data packet transfer.

Both the Status-1 and Status-2 signals can be driven by any one of the 16 1/0 ports, and there is no indication as to which 1/0 port 10 is driving these status signals.

With respect to the third status signal, Status-3, each port 10 is allotted a specific time period for driving this signal. This allows the port 10 driving the status signal to be explicitly identified. As can be seen by Figure 2, two transfer cycles are required to allot a specific time period for each of the 16 1/0 ports 10.

Figure 3 represents the format of a data packet transfer showing the relationship of actual data transfer bus cycles represented in Figure 2. The priority number for each data packet transfer cycle is transmitted over the data bus 14 along with the data packet itself The priority number effectively becomes a channel identification number and is used as an 1/0 port destination address.

As can be seen from Figure 3, data is transferred least significant word first, with each word being transferred least significant byte and bit first. However, it will be appreciated by a person of ordinary skill in the art that data can be trarisferred most significant bit first,for in any arbitrary order. Likewise, the transfer cycle priority number can be transferred in any position within the data packet transfer cycle.

6 Turning to Figure 4, a schematic diagram is provided showing the main elements of the present invention with respect to the entire bus system. Data packets arrive at the buffer 40 of an incoming 1/0 port 10a. The buffer 40 is generally small and sized to cater for latency of the received date transmitted over the data bus 14.

When data is transmitted over the data bus 14 to an outgoing 1/0 port 10b, the data packet is stored in an buffer 42 in the outgoing 1/0 port 10b. The buffer 42 contains buffer overflow detect circuitry 44 to detect when the buffer 42 is full. If the buffer 42 becomes full, a BUFFER_OVERFLOW_ERROR_SIGNAL (as labeled in Figure 4) is asserted.

Each data packet, as it is being transmitted, is also stored in a shadow buffer 46 located on a control card 12. The shadow memory buffer 46 is controlled by a control circuit 50 which, after sensing the BUFFER_OVERFLOW_ERROR_SIGNAL from the circuitry 44 of the outgoing port 10b, organizes the data packet(s) within the shadow memory buffer 46 and controls retransmission of the packet(s) to the correct outgoing 1/0 ports 10b.

In the preferred embodiment, the output buffer 42 asserts a BUFFER_FULL signal, within the circuitry 44, when the buffer 42 is full. If the data packet being transmitted over the data bus 14 is addressed to an outgoing 1/0 port 10b with its BUFFER_FULL signal asserted, the packet will not be stored in the buffer 42. Upon sensing the BUFFERJULL signal, the circuitry 44 asserts the BLTFFER_OVERFLOW_ERROR_SIGNAL informing the shadow buffer controller 48 that the packet should be kept in the shadow buffer 46 for later retransmission.

The BUFFER_OVERFLOW_ERROR_SIGNAL is transmitted at the end of a data packet transmission similar to Status-2 shown in Figure 2. When the circuitry 44 determines that room is available in the buffer 42, it informs the shadow buffer controller 48 by a BUFFER_AVAI]LABLE signal. The BUFFER_AVAI]LABLE signal may be transmitted at the beginning of a data packet transfer (similar to Status-1 in Figure 2), or may be transmitted in turn (similar to Status-3 in Figure 2).

7 According to an essential aspect of the present invention, shadow buffer 46 acts as a centralized memory resource for temporary storage of data packets which would otherwise be lost during transmission due to a full buffer 42 in the outgoing port I Ob. This results in an efficient distribution of buffer memory. The memory of the shadow buffer 46 may be either First-In First-Out (FIFO) or random access (RAM) memory, which may be indirectly indexed by an 1/0 port number.

In the preferred embodiment, FIFO memory is used for the shadow buffer 46, as shown in Figure 5. Each data packet transmitted on the bus 14 is automatically stored in the next available location in FIFO 52. In the embodiment of Figure 5, the FIFO 52 is shown implemented as A ring buffer in memory. An address multiplexer 54 is used to address the contents of FIFO 52 with a pointed selected from one of either a Buffer_Pointer register 56 or a Packet-Pointer register 58, as discussed in greater detail below.

Operation of the shadow buffer 46 of Figure 5 during a data packet transmission, is illustrated in Figures 6a and 6b. When a data packet (shown as a PACKET_RX signal) is transmitted, the packet is stored in the shadow buffer 46 at the next available space in the shadow buffer 46. The shadow controller 50 contains a NEXT_BUFFER_POINTER which points to the next available storage location in the shadow buffer 46. If the BUFFER_OVERFLOW-ERROR SIGNAL is not asserted, no action is taken and the shadow buffer 46 awaits transmission of next data packet. If the BUFFER_OVERFLOW_ERROR_SIGNAL is asserted, then the NEXT_BUFFER_POINTER increments to a next available packet storage location in the shadow buffer 46. The shadow buffer 46 then awaits the next packet.

During retransmission of a data packet, the PACKET_POINTER, stored in register 58 of shadow buffer controller 50, points to the earliest packet saved in the shadow buffer 46. When no buffer overflow has occurred, the PACKET - POINTER and the NEXT_BUFFER_POMTTER point to the same location in the shadow buffer 46. If a buffer overflow has occurred, the shadow buffer 46 enters a READY-TO-TRANSNUT state. When the BUFFER_AVAILABLE signal is 8 detected, the shadow memory 46 gains control of the data bus 14 and retransmits the packet to the non-full buffer 42 of the outgoing 1/0 port 10b. Simultaneously, the PACKETJOINTER is incremented to point to the next earliest stored packet in the shadow buffer 46.

In the preferred embodiment, a BUFFER_OVERFLOW_ERROR_SIGNAL assertion is followed by a BUFFER_AVAILABLE originating from the same outgoing 1/0 port 10b. In the case that these signals originate from different 1/0 ports 10, the shadow buffer 46 retransmits the data packet to an outgoing 1/0 port I Ob which is not capable of accepting the data packet. Arrival of the data packet at the wrong port 10b cause the port to signal a BTJFFER_OVERFLOW_ERROR_SIGNAL and the packet is re-stored in the shadow buffer 46. This results in an out-of-order transmission of packets if one or more packets for a single port 10 is held in the shadow buffer 46.

In order to overcome this problem, an alternative mode of operating the shadow buffer 46 is illustrated in Figures 6c and 6d. In the alternative embodiment, each 1/0 port 10 is associated with a separate BUFFER_AVAELABLE signal and therefore each packet is temporarily stored in the shadow buffer 46. This mode of operation also requires the inclusion of a further register 60 and look- up RAM 62, as shown in Figure 7, for storing the availability status of each 1/0 port buffer 42 and 44, as discussed in grater detail below.

The difference in operation between the altenative embodiment of Figures 6c and 6d and the embodiment of Figures 6a and 6b, relates to the READY_TO_TRANSNffT state. According to the alternative embodiment, when in the READY-TO-TRANSMIT state, the shadow buffer controller 50 determines which 1/0 port 10 is the destination port for the packet. This can be achieved by one of the following methods:

1. A discrete 1/0 port identification number in the packet header; 9 2. A table look-up with packet priority ID No. when the packet is stored in the shadow buffer 46; or 3. A table look-up with packet priority ED No. when the packet is next in the FIFO shadow buffer 46 for retransmission.

The identification of the availability of the buffer 42 of the outgoing 1/0 port I Ob or the buffer 40 of and incoming 1/0 port 1 Oa is determined by seeing which outgoing 1/0 port 10b is driving the BUFFER - AVAILABLE signal. The BUFFER_AVAILABLE signal is transmitted in a similar manner to the Status-3 signal shown in Figure 2. Register 60 is used to record the availability status of each 1/0 port buffer 42 or 44.

According to a fin-ther alternative embodiment of the invention as illustrated in Figure 8, packets are temporarily stored in the shadow buffer 46 in a predetermined sequence. When Port 0 becomes available, the packets Port O(N) and Port O(N+I) are transmitted on the bus 14. However, if Port 5 is not available, then packet (W for Port 5 is not transmitted until Port 5 is available. The subsequent packets in the shadow buffer 46, such as packets Port O(N+ 2) and Port 3(P), are also not transmitted. Subsequent packets may only be transmitted once Port 5 becomes available and its packet has been transmitted.

It will be appreciated that, although a particular embodiment of the invention has been described and illustrated in detail, various changes and modifications may be made. All such changes and modifications may be made without departing from the sphere and scope of the invention as defined by the claims appended hereto.

Claims

What is claimed is:

1. A packet switch comprising:

a) a data packet bus; b) a first 1/0 port connected to said data bus for receiving an incoming data packet; C) a second 1/0 port connected to said data bus for receiving said data packet and storing said data packet in an outgoing packet buffer prior to further transmission, said second 1/0 port including a buffer overflow detector for generating a buffer overflow signal in the event said outgoing packet buffer becomes fall and a buffer ready signal in the event said outgoing packet buffer is not full; and d) a controller for controlling packet transmission between said first and second 1/0 ports, said controller including a shadow buffer connected to said data bus for storing said data packet as it is transmitted from said first 1/0 port to said second 1/0 port and in response to receiving said buffer overflow signal retaining said data packet for re-transmission to said second 1/0 port, and in response to receiving said buffer available signal retranslating said data packet to said second port and discarding said data packet from said shadow buffer.

2. The packet switch of claim 1 wherein said shadow buffer is a First-InFirst Out (FIFO) memory.

3. The packet switch of claim I wherein said shadow buffer is random access memory (RAM).

4. The packet switch of claim I wherein said controller further comprises a buffer pointer register for identifying a location of said shadow buffer for storage of said data packet.

5. The packet switch of claim I wherein said controller fin-ther comprises a packet pointer register for identifying a location of said shadow buffer for retrieval of said data packet or retransmission of said data packet.

11

6. The packet switch of claim I wherein said shadow buffer further comprises a port availability register and a port number look up table.

7. The packet switch of claim 6 wherein said controller ffirther determines said second 1/0 port by one of either a discrete 1/0 port identification number in a header of said data packet or a table look-up of packet priority identification numbers when said data packet is next for transmission or retransmission in said shadow buffer.

8. The packet switch of claim 6 wherein said data packets are stored in a predetermined sequence in said shadow buffer for transmission.