GB2337169A

GB2337169A - An adaptive predistorter for an amplifier

Info

Publication number: GB2337169A
Application number: GB9809790A
Authority: GB
Inventors: Petri Manninen; Harri Lilja
Original assignee: Nokia Mobile Phones Ltd
Current assignee: Nokia Oyj
Priority date: 1998-05-07
Filing date: 1998-05-07
Publication date: 1999-11-10
Also published as: GB9809790D0

Abstract

An amplifying circuit which may be incorporated into a transmitter for use in a wireless telecommunications network receives an input signal and applies some predistortion thereto to provide a predistorted signal. An amplifier amplifies the predistorted signal and provides an output signal. The input signal is compared with the output signal and in dependence on the difference between the input and output signals, the predistortion to be applied to a subsequent input signal is modified. The frequency with which the comparison is made may be altered in dependence on the difference, the resulting reduction in processing reducing battery consumption.

Description

1 AMPLIFYIMG CIRCUIT AND METHOD 2337169 The present invention relates to

an amplifying circuit and method including predistortion. In particular, but not exclusively, the present invention relates to a transmitter incorporating such an amplifying circuit. This transmitter may be used in a wireless telecommunications network, such as for example, a spread spectrum cellular telecommunications network.

The use of code division multiple access (CDMA) is currently being proposed for the next generation of cellular telecommunications networks. CDMA uses a digital spread spectrum multiple access technique which it is believed will allow the volume of traffic supported by a cellular telecommunications network to be increased. In CDMA if the transmitter of, for example, a mobile station is not linear, spectrum spreading to adjacent channels can occur. By linear, it is meant that the input signal is linear with respect to the transmitted signal. This leads to a reduction in the quality of the transmissions and can also reduce the system capacity. If the transmitter is linear or substantially linear, the problem of spread spectrum spreading to adjacent channels can be reduced.

The linearity of the transmitter is largely dependent on the operating characteristics of the power amplifier which is used to amprlify the signal to be transmitted. Highly linear power amplifiers could be used to reduce the amount of spectrum spreading to adjacent channels. However, the power efficiency of linear amplifiers is poor. This is disadvantageous for mobile stations where battery life is an important consideration. Less linear amplifiers are more power efficient and in particular consume less power for the required amplification. It is therefore been proposed to use non-linear amplifiers in spread spectrum transmitters, particularly in mobile stations but with compensation for the non-linearity of the amplifier. one method of compensation is adaptive digital predistortion. With this method, before a signal is input to a power amplifier, it is 2 predistorted in a non-linear manner. This predistortion is the inverse of the distortion which is caused by the amplifier. Accordingly, the predistorted signal is input to the amplifier which then provides a linear output. Digital predistortion requires signal processing means which operate with an oversampling speed proportional to transmission bandwidth. In a wideband system, digital predistortion related circuitry, which includes digital circuits, analogue to digital converters and digital to analogue converters, can consume a significant amount of power, because the power consumption is proportional to clock frequency.

In adaptive predistortion, a feedback or adaption path is provided which allows a part of the signal which is transmitted to be compared with the input signal. This allows the linearity of the transmitted signal with respect to the input signal to be determined. The predistortion applied to the subsequent input signals is altered in dependence on the result of the comparison between the input signal and the transmitted signal. Generally, when the transmitter is first used, the predistortion provided does not accurately compensate for the non-linearity of the amplifier. However, after a certain number of comparisons, the predistortion will become relatively accurate. The operating characteristics of the amplifier will change slowly with time, resulting from changes in temperature. The feedback path allows the predistortion applied to input signals to be altered to compensate for these changes in the operating characteristics of the amplifier with time.

However, there are some disadvantages with known adaptive predistortion arrangements.

provision of the feedback As discussed hereinbefore, the path in order to allow the predistortion to be modified consumes power each time a comparison takes place. In a device such as a mobile station, this places an additional demand on the battery and accordingly will reduce its life between chargings. In the known systems, the frequency of the comparisons represents a compromise between 1 j obtaining accurate predistortion quickly when the transmitter is first used which is obtained by a high comparison frequency and prolonging battery life which is obtained with a low frequency of comparison. When the transmitter is first used, the predistortion applied will be relatively inaccurate and it may take some time for the adaptive path to compensate correctly for the non-linear linearity of the power amplifier. This is disadvantageous. However, when the device has been operating for some time and because the changes in the operating characteristics of the amplifier occur relatively slowly with time, changes in the operating characteristics can be easily compensated for. The constant comparison frequency used in the prior art does not take into account these differences.

It is therefore an aim of embodiments of the present invention to provide a circuit which avoids or reduces the problems of the prior art.

According to one aspect of the present invention there is provided an amplifying circuit comprising: predistortion means for receiving an input signal and applying a predistortion thereto to provide a predistorted signal; amplifier means for amplifying the predistorted signal and providing an output signal; and means for comparing the input signal with the output signal and modifying in dependence on the difference between said input and output signals the predistortion to be applied by the predistortion means to a subsequent input signal, wherein an adaption characteristic of the comparing and amplifying means is alterable to reflect changes in the difference between the input and output signals.

Since an adaption characteristic of the comparing and modifying means is alterable to reflect changes in the difference between the input and output signals, better power efficiency can be achieved. It should be appreciated that the changes in the adaption characteristic can occur in response to actual changes in the difference between the input and output signals or be 4 based on predicted changes in the difference. Accordingly, said adaption characteristic may be alterable in dependence on the difference between the input and output signals. Alternatively, the adaption characteristic may be altered after a predetermined length of time.

Preferably, the predistortion means is arranged to apply at least one predistortion value to the input signal to provide the predistortion signal. The at least one predistortion value which is applied to the input signal may be dependent on one or more characteristics of the input signal. The one or more characteristics of the input signal may be amplitude or a characteristic dependent on amplitude. The predistortion value may be a coefficient, possibly complex, which is multiplied with the input signal, for example in complex gain predistortion. Alternatively the at least one predistortion value may be a factor. In polar predistortion one factor is added to the phase of the signal and another factor is multiplied by the magnitude of the signal.

The comparing and modifying means preferably updates the at least one predistortion value used by the predistortion means to predistort the input signal, in dependence on the result of the comparison to provide at least one new predistortion value, the at least one new predistortion value being used by the predistortion means to predistort a subsequent input signal.

Preferably, the adaption characteristic of said comparing and modifying means which is altered is the frequency with which the comparing and modifying means compares the input and output signals (the comparing frequency is how often the input and output signals are compared). Preferably, the frequency is higher when there is a relatively large difference between the input and output signals and the frequency is lower when there is a relatively small difference between the input and output signals. Thus, the comparing frequency can be high when there is poor compensation being provided by the predistortion means enabling a fast improvement in the compensation. The comparing frequency can be low, when there is good compensation being provided by the predistortion means, thus reducing the power consumption The comparison frequency can be altered in dependence on the difference between the input and output signals or can be altered after a predetermined time.

Preferably, the predistortion means receives a first clock signal and the comparing and modifying means receives a second clock signal for controlling the frequency of said comparisons, said second clock signal being derived from the first clock signal.

Preferably, clock frequency dividing means are provided for dividing the first clock signal, said dividing means receiving an input setting the amount by which the first signal is to be divided to provide the second clock signal. The input to said clock frequency dividing means is preferably derived from the result of the comparison performed by the comparing means. Alternatively the input to the clock frequency dividing means can be arranged to change after a predetermined time after start-up.

Alternatively or additionally, the adaption characteristic of said comparing and modifying means which is altered is the step size of the modification provided by said comparing and modifying means.

Preferably, the step size is relatively large when there is a relatively large difference between the input and output signals and the step size is smaller when there is a relatively small difference between the input and output signals. Alternatively, the step size may be relatively large to begin with and then be altered to a smaller size after a predetermined time. Thus, the dif f erence between the new and old predistort ion coef f icients may be relatively large if the step size is relatively large and the difference between the new and old predistortion coefficients may be relatively small if the step size is smaller.

6 memory means may be provided for storing a plurality of predistortion coefficients which may be implemented in the form of a look up table.

Preferably, an address calculation block is provided to calculate an address from which the at least one predistortion coefficient is obtained, the address being calculated based on a parameter of said input signal. The parameter may be amplitude or based on amplitude, for example power.

Preferably, delay means are provided to ensure that the output signal is compared with the corresponding input signal.

Preferably, the predistortion means is arranged to compensate for non linearities in said amplifier means so that the output signal is linearly amplified with respect to the input signal.

Preferably, said comparing and modifying means uses a least mean square algorithm to determine the modified predistortion or at least one new predistortion value to be applied by the predistortion means to a subsequent input signal.

The predistortion means may use predistortion based on predistortion in Cartesian form (complex gain predistortion) or predistortion based on predistortion in polar form (polar distortion) In the latter case, means may be provided for converting said input signal into polar form prior to predistortion and converting the predistorted signal rectangular form after predistortion and prior to amplifying the amplifier means.

to by A transmitter may incorporate the circuit as described hereinbefore. The transmitter may be in a mobile station or base station transceiver.

According to a second aspect of the present invention, there is provided a method comprising the steps of:

7 receiving an input signal and applying a predistortion thereto to provide a predistorted signal; amplifying the predistorted signal and providing an output signal; comparing the input signal with the output signal and modifying in dependence on the difference between the input and output signals the predistortion applied by the predistortion means to a subsequent input signal; and altering an adaption characteristic of said comparing and modifying means to reflect changes in the difference between the input and output signals.

For a better understanding of the present invention, and as to how the same may be carried into effect reference will now be made by way of example to the accompanying drawings in which:

Figure 1 shows a block diagram of a transmitter embodying the present invention; Figure 2 shows a schematic diagram of part of a cellular telecommunications network incorporating base transceiver stations and mobile stations; and Figure 3 shows the spectra of an output of the power amplifier of Figure 1.

Reference will now be made to Figure 1 which shows a transmitter 2 embodying the present invention. The transmitter 2 includes a predistortion section 4 and an adaption section 6.

The predistortion section 4 is arranged to predistort an input signal so as to compensate for the non-linear behaviour of a power amplifier 8. As discussed hereinbefore, better power consumption is achieved if nonlinear amplifiers or amplifiers in their non-linear mode of operation are used instead of linear amplifiers or amplifiers in their linear mode of operation. The predistortion section 4 is arranged to provide compensation for 8 t. non-linearity of the power amplifier 8. The predistortion seccion 4 aims to ensure that the output of the power amplifier 8 is linear or substantially linear with respect to the input to the predistortion section 4. The predistortion section 4 receives a modulated signal via input 10. The signal is at the baseband frequency, which means that the signal is separated into its quadrature components, namely the I and Q components. Mathematically the signal is considered as a complex signal, of which the real and imaginary parts correspond to the I and Q components respectively. These I and Q components will be referred to as I and Q signals hereinafter. The input I and Q signals are input to a predistortion block 12 of the predistortion section 4 which predistorts the signals to compensate for the non-linearity of the amplifier 8.

The I and Q signals are also input to an address calculation block 14. As the predistortion section 4 is arranged to compensate for amplitude based distortion of the amplifier 8, the predistortion which is applied by the predistortion block 4 takes into account the amplitude of the band pass signal or a parameter which is a function of the amplitude, for example power. The address calculating block 14 therefore calculates the magnitude of the complex input signal if the compensation is to be based of the amplitude of the complex input signal or the squared magnitude of the complex input signal if the compensation is to be based on the power of the complex input signal.

The address calculating block 14 may calculate the magnitude A(i) of the complex signal using the following equation:

A (i) = (12 (i) + Q2 (i)) 11 where I (i) and Q (i) are the components of the input complex signal. The address may, but not necessarily, be a function of A(i). In practice, quantization of the calculated magnitude is required before the address can be derived.

9 The address calculating block 14 is connected to a look-up table 16. The value calculated by the address calculating block 14 defines an address in the look-up table 16. The look-up table may be provided by a RAM (random access memory). The look-up table 16 contains predistortion coefficients. Thus, each address contains two coefficients which can be considered as one complex predistortion coefficient. The look-up table 16 has an output connected to the predistortion block 12. The complex predistortion coefficient present at the address calculated by the address calculating block 14 is output to the predistortion block 12. The predistortion block 12 predistorts the input I and Q signals in accordance with the complex predistortion coefficient provided by the look-up table 16. The predistortion carried out by the predistortion block 12 will be discussed in more detail hereinafter.

The output of the predistortion block 12 is connected to an I/Q modulator error balance block 18. This balance block 18 is arranged to compensate for phase and amplitude imbalances and DC offsets between the I and Q signals. These imbalances and DC offsets are generally cau sed by the I/Q modulator 30 which is downstream of the balance block 18 and will be discussed in more detail hereinafter. Thus, the I/Q modulator error balance block 18 effectively compensates for errors which would be introduced by the analogue I/Q modulator 30. The balance block 18 may be arranged to adjust itself automatically to compensate for the particular characteristics of the modulator 30 to which it is connected. Alternatively, the balance block 18 may be adjusted during production. This latter approach will provide adequate results as the imbalances introduced by the modulator 30 will not tend to vary significantly with time or temperature. The output of the predistortion block 12 as well as the I/Q modulation error balance block 18 can still be regarded as being two signals, an I signal and a Q signal. The output of the I/Q modulator error balance block 18 is input to a digital to analogue converter block 22 which converts the signals from their digital form to analogue form. In practice the digital to analogue block 22 will comprise two digital to analogue convertors, one for the I signal and one for the Q signal. The output of the digital to analogue converter block 22 represents the output of the predistortion section 4 and includes separate outputs for the I and Q signals.

The predistortion section 4 also includes first and ---ind delay blocks 24 and 26. These delay blocks 24 and 26 may, f:,.xample, be shift registers or the like. The first delay blo- ---Ahas an input from the address calculating block 14 an- an output connected to the look-up table 16. The address calculated by the address calculating block 14 is, at the same time that it is output to the look-up table 16, output to the first delay block 24. At a predetermined time later, that address is output to the lookup table 16. The delay provided by the first delay block is equal to T1,1,. The significance of this delay will be discussed hereinafter.

The second delay block 26 receives the input I and Q signals from input 10 and outputs those signals, a predetermined time later to the third delay block 27 which is included in the adaption section 6. The delay provided by the second delay block 26 is the same as that provided by the first delay block 24.

The third delay block 27 receives its input from the second delay block 26 and outputs the I and Q signals a predetermined time later to the adaption algorithm block 60 which will be described in more detail hereinafter. The delay provided by the third delay block 26 compensates for the delay caused by the I/Q demodulator error balance block 58 which will be described in more detail hereinafter as will the significance of the delay provided by the third delay block 27.

Thus, the predistortion section 4 comprises the predistortion block 12, the I/Q modulator error balance block 18, the digital to analogue converter block 22, the address calculation block 14, the first delay block 24 and the second delay block 26. it should be appreciated that the predistortion section 4 also receives a 11 predistortion clock signal CLK,,, which controls the timing thereof.

The output of the digital to analogue converter block 22 is connected to the input of a first filter block 28. In practice, the first filter block 28 will comprise two filters, one for the I signal and one for the Q signal. The filters of the first filter block 28 are reconstruction filters and take the form of lowpass filters. The digital to analogue converter block 22 creates undesired mirror images of the signals. The first filter block 28 will remove any such mirror images.

The I and Q outputs of the first filter block 28 are input to the I/Q modulator 30 which creates a real bandpass signal out of the two separate I and Q baseband frequency signals. This real bandpass signal will be at an intermediate frequency. A signal from a first local oscillator 32 is input to the modulator 30. The l/Q modulator mixes the I signal with cos(27rft) and the Q signal with -sin(27rft). t is time and f is the mixing frequency provided by the first local oscillator 32.

The resulting signals are then combined to give a resultant signal as follows:- Sl/Q (t) =I (t) cos (27rf t) Q (t) sin (27rft) ( 1) Thus, the I/Q modulator 30 can be regarded as being a quadrature mixer. The output of the I/Q modulator 30 is connected to a first filter 34 which is tuned to the intermediate frequency f. The first filter 34 is a bandpass filter. The first filter 34 eliminates any harmonics which result from the mixing operation carried out by the I/Q modulator 30.

The output of the first filter 34 is connected to the input of a first mixer 36. The first mixer 36 also receives an input from a second local oscillator 38. The signal from the second local oscillator is mixed by the first mixer 36 with the output of the 12 first filter 34 to provide a signal at the radio frequency. The output of the first mixer 36 is connected to a second filter 40 which is a bandpass filter and which is arranged to eliminate any harmonics resulting from the mixing operation carried out by the first mixer 36. The second filter 40 is tuned to the radio frequency. The output of the radio frequency filter 40 is input to the power amplifier 8, which is operating in a non- linear manner. The output of the power amplifier 8 is passed to an antenna 42 for transmission across a radio channel.

Between the output of the power amplifier 8 and the antenna 42, a coupler 44 is provided. This coupler 44 takes a small proportion of the signal to be transmitted and inputs it to a second mixer 46. The signal provided by the coupler 44 is a feedback signal. The second mixer 46 also has an input from the second local oscillator 38. The second mixer 46 mixes the signal from the coupler 44 with the signal from the second local oscillator 38 to provide a signal at the intermediate frequency. The output of the second mixer 46 is input to an gain control block 48. The gain control block may be an automatic gain control block. The gain control block 48 adjusts the amplitude of the feedback signal so that it is within the optimal input range of an analogue to digital converter block 50, downstream of the gain control block 48. The analogue to digital converter block 50 forms part of the adaption section 6 and will be described in more detail hereinafter.

The output of the gain control block 48 is input to an I/Q demodulator 52. The I/Q demodulator 52 receives an input from the first local oscillator 32. The feedback signal, output from the gain control block 48, is mixed by the I/Q demodulator 52 with the signal from the first local oscillator 32 to provide a complex signal comprising an I and a Q signal, each at the baseband frequency. The outputs of the I/Q demodulator 52 are connected to the input of a second filter block 54 which comprises two anti-alias filters, one for the I signal and one for the Q signal. These anti-alias filters are lowpass filters 1 and are provided to remove any harmonics caused by the mixing operations carried out by the second mixer 46 and the I/Q demodulator 52.

The outputs of the second filter block 54 are input to a sample and hold circuit 56. The sample and hold circuit takes a sample of the I and Q feedback signals which are received from the second filter block 54 and which are in analogue form. The sample and hold circuit 56 holds the samples taken so that the analogue to digital converter block 50 can digitize the sampled signals. The analogue to digital converter block 50 will in practice include two analogue to digital converters, one for the I signal and one for the Q signal. The digitized I and Q samples are output from the analogue to digital converter block 50. The analogue to digital converter block 50 receives an adaption clock signal CLKAD. The relationship between the predistortion clock signal =PD and the adaption clock signal CLK. will be described in more detail hereinafter.

The outputs of the analogue to digital converter block 50 are input to an I/Q demodulator error balance block 58. This block 58 provides a similar function to the I/Q modulator error balance block 18. In particular, the I/Q demodulator error block 18 compensates phase and amplitude imbalances and DC offsets introduced by the I/Q demodulator 52. The I and Q outputs of the I/Q demodulator error balance block 58 are input to the adaption algorithm block 60.

The adaption algorithm block 60 is arranged to compare the I and Q signals provided at input 10 with the I and Q signals output from the I/Q demodulator error balance block 58. This comparison provides a measure as to how successful the predistortion provided by the predistortion block 12 is at compensating for the non-linearity of the power amplifier 8. The adaption algorithm block 60 also receives the complex predistortion coefficient from the look-up table 16 corresponding to the address calculated by the address calculation block 14. The adaption algorithm block 14 also receives an input 61 which provides an adaption factor g. The purpose of the adaption factor will be discussed hereinafter.

The adaption algorithm block 60 may use, for example, a least mean square type algorithm having the following form:

gi.l=gi+ (SFB (i) - S, (i) gi where gi is the previous complex coefficient in the lookup table 16, i.e. the complex predistortion coefficient addressed by the address calculating block 14 and used to predistort the ith input sample and i is its conjugate. SFB (') is the ith sample of the feedback signal obtained by coupler 44 and output by the I/Q demodulator error balance block 58 and gFI1 (') its conjugate. s,,(i) represents the ith input sample at input 10. g is the adaption factor. Thus, the adaption algorithm block 60 effectively compares the signal which is input at input 10 with the signal which is transmitted. The result of that comparison is multiplied by the complex conjugate of the input signal and the adaption factor. This provides a value which is added to the previous complex predistortion coefficient to provide a new complex predistortion coefficient. Adaptation algorithms other than the least mean square algorithm described hereinbefore can be used. For example suitable adaption methods disclosed in the thesis by Lars Sundstr6m entitled lIRF Amplifier Linearisation Using Digital Adaptive Predistortionll (Lund University, Department of Applied Electronics) can be used.

The new complex predistortion coefficient calculated by the adaption algorithm block 60 is output to the look-up table 16. The first delay block 24 ensures that the adaption algorithm block 60 provides an output at the same time that the address calculated by the address calculating block 14 is output by the first delay circuit 24. Thus, the new complex predistortion coefficient replaces the old complex predistortion coefficient in the look-up table 16.

The timing of the transmitter is controlled so that the feedback signal and the original signal are presented at the adaption algorithm block 60 at the same time. The time taken for the I and Q signals provided at input 10 to be output by the second delay block 26 is equal to the rime 71,,N_. The time taken for the output of the second delay block 26 which is input to the third delay block 27 to be output by the third delay block 27 is equal to the time -r2. The time taken for the input signals to pass from input 10 to the input of the sample and hold circuit 56, via the power amplifier 8 is equal to T1,INT+71,FUC. T1,nZAC is a fraction of a single clock cycle which is introduced because the signal is in analogue form for some of the time that it passes through various components of the transmitter. In particular, the time taken to pass from the input 10 tothe sample and hold circuit 56, via the power amplifier 8, does not take a whole number of clock cycles. T1, INT represents an integer number of the predistortion clock CLKp, cycles with 7-1,mc representing a fraction of a clock cycle.. The time taken for the signal to pass from the sample and hold circuit 56 to the adaption algorithm block 60 is equal to r2TI.:. Thus, both the input signal and the feedback signal SIN, SFB take a time equal to T1,1NT + 7.2 to reach the adaption algorithm block 60.

A fourth time delay block 62 which can be analogue or digital receives the adaption clock signal CLK,D and delays that signal by a time equal to -rl,FRAc. The output of the fourth delay block 62 is connected to the input of the sample and hold circuit 56. This fourth delay block 62 compensates for the fractional delay T1,FRAC introduced by the fact that the signal is in analogue form when it passes through part of the transmitter. This means that the samples taken by the sample and hold circuit 56 coincide with the part of the signals which are to be sampled. The timing signal provided by the output of the fourth delay circuit 62 thus controls when the sample and hold circuit 56 takes the samples.

The adaption clock signal CLKAD is derived from the predistortion clock signal CLKID In particular, the adaption clock signal 16 speed is less than the predistortion clock frequency CLKp, by a factor N. The predistortion clock signal CLK,,, is input to a dividing circuit 64 which reduces the clock rate by the factor N. The divider 64 has an input for receiving the value of N. N will generally be an integer.

Referring to the adaption factor g, the value of this may depend on the length of time since start-up of the transmitter. When the transmitter 2 is first used, a relatively large adaption factor can be used. The larger the adaption factor, the faster the adaption, but in practice this means also coarser error correction due to random and systematic errors. The adaption factor can be regarded as being representative of the step size between the old complex predistortion value and the new complex predistortion value. When the difference between the feedback signal and the input signal is smaller, the adaption factor can be reduced. The smaller the adaption factor, the smaller the step size between the old and the current complex predistortion values. Thus, use of large adaption factors initially and smaller adaption factors after a certain time means that the time taken to achieve accurate predistortion compensation can be reduced. The adaption factor g can be set by processing means (not shown) in accordance with an error signal output by the adaption algorithm block 60. The error signal represents the difference between the input signal and the feedback signal. A small difference means a small adaption factor g is selected and a large difference means a large adaption factor g is selected. The adaption factor a can vary stepwise, continuously or have a limited number of values.

The adaption clock frequency can be altered as required. For example, where the difference between the input signal and the feedback signal is relatively large, it can be assumed that the compensation provided by the predistortion section 4 is not particularly good. Accordingly, the adaptation section 6 should be controlled to carry out comparisons of the input and output signals and. the calculations of revised predistortion 17 coefficients as often as possible to achieve accurate predistortion compensation as soon as possible. N will then have a low value and may f or example be 1 or 2. However, when the input signal and the feedback signal have similar values, it can be assumed that any further changes required to the predistortion will occur slowly. These changes may result from changes in temperature, changes in voltages or currents etc. Accordingly, the adaptation clock frequency can be reduced. In those circumstances, the value of N can be increased. Alternatively, the adaption clock frequency can be reduced after a predetermined time. That predetermined time will usually be sufficient for accurate or reasonably accurate predistortion compensation to be achieved-The predetermined time can be based on the average or the worst case adaption time.

In a preferred embodiment of the present invention, the value of N is set by a processing means (not shown) in accordance with the error signal output by the adaption algorithm. The processor could derive a mean square error of the error signal and set one or more threshold levels. The frequency would then be increased or decreased accordingly. With small differences between the input signal and the feedback signal, N will be relatively high and with large differences between the input signal and the feedback signal, N will be relatively low. Alternatively, the frequency could be reduced after a predetermined time, as with the adaption factor N. Time based decisions are possible, because on average the adaption time is predictable di.e to the random nature of adaption. The criteria used to alter the adaption factor p will generally also apply to the alteration of the adaption clock CLKAD frequency. In one embodiment, the threshold(s) for changing the adaption factor differs from that or those which are used to alter the adaption clock frequency.

The adaption clock can also be controlled to increase the rate of comparison if, for example, the channel changes. If the channel of communication is changed, this may mean that the previously used predistortion may not be appropriate. It is 18 therefore advantageous to be able to arrive the correct predistortion as quickly as possible. Depending on the type of system, a change in channel may involve a change in frequency.

The predistortion block 12 can carry out any suitable type of predistortion, for example complex gain predistortion or polar predistortion. In complex gain predistortion, the I and Q signals are multiplied by coefficients obtained from the address of the look-up table 16 calculated by the address calculation block 14. The coefficients obtained from the look-up table 16 are gn and gim - The signal output by the predistortion block 12 is defined as:

SOUT W = (9RE ( 1 SIN W 1) +i - 9IM ( 1 SIN (') 1)) - SIN W where SIN (i) represents the complex input signal having the f orm:

SIN(') =,IN(') +i -QIN (') - Thus, SOjT (i) represents the complex output signal of form:

SOUT ( i) =IOUT (i) +i - QOUT (i) In the polar predistortion method, the amplitude of the signal and the phase of the signal are predistorted separately. The I and Q signals are thus converted to polar form in the following way:- Mag (s (i)) = 1 s (i) 1 = (I (i) 2+Q (i) 2) 11 and Phase(s(i))=arctan If 77 j Mag (s (I)) represents the magnitude of the complex input signal while Phase (s (i)) represents the phase of the complex input signal. This conversion to polar form takes place right after the input 10. Additionally the same conversion is needed for the 19 output of the analogue to converter block 50 in the feedback branch. Means for both of these conversions are not shown in Figure 1.

A separate address calculation block is not required if the polar predistortion method is used. This is because the magnitude has already been calculated and can be used to define an address in the look up table 16. Thus, the predistortion factors in the look up table 16 are fetched according to the calculated magnitude Mag (S (i)). The predistortion factors comprise a phase factor and an magnitude factor. The predistortion factor corresponding to the phase is added to the value of the Phase(s(i)). The factor corresponding to the magnitude is multiplied with the Mag (s (i)).

After predistortion and prior to passing through the digital to analogue converter block 22, the polar signal needs to be converted back to rectangular format using the following equations:- I (i) =Re (s (i) =Mag (s (i) cos (Phase (s (i)) and Q (i) = Im (s (i) =Mag (s (i) - sin (Phase (s (i)) where s(i) is the predistorted signal. Means for this conversion are again not shown in Figure 1. In some embodiments of the present invention using polar predistortion, the conversion of the polar form signals back to rectangular form may not be required.

It should be noted that the transmitter circuit 2 shown in Figure 1 is designed for a continuous flow of signals so that at every clock cycle there is a new input and new output value for each block.

Figure 3 is an illustrative example of a possible spectra of an output of the power amplifier 8. Line 70 represents the output without predistortion. Line 72 represents the output after a few rounds of adaption and line 74 represents the output of the power amplifier after good compensation has been achieved by the predistortion section 4.

Embodiments of the present invention may alternatively use mapping or polynomial predistortion. In these cases the predistortion section 4 and adaptation section 6 will differ from that described hereinbefore to take into account the different predistortion method used. The adaption factor and the adaption clock frequency can still be controlled as described in relation to the embodiment shown in Figure 1.

The transmitter described in relation to figure 1 is preferably included in a mobile station for use in a cellular telecommunications network. However, it should be noted that the transmitter shown in figure 1 can also be incorporated into a base transceiver station.

Reference will now be made to Figure 2 in which three cells 102 of a cellular mobile telecommunications network are shown. Each cell 102 is served by a respective base transceiver station (BTS) 104. Each BTS 104 communicates with mobile stations (MS) 106 such as mobile telephones or the like which are located in respective cells. Thus, each base transceiver station 104 is arranged to transmit signals to and receive signals from the mobile stations located in the cell associated with each given BTS 104. Likewise each MS 106 is able to transmit signals to and receive signals from the respective BTS 104. Generally, radio waves are used in the communication between the base transceiver station 104 and the mobile stations 106.

Embodiments of the present invention can be used in relation to spread spectrum systems such as CDMA systems, time division multiple access systems, frequency multiple access systems or hybrids thereof.

Embodiments of the present invention are particularly useful in wideband systems.

21 The embodiment of the present invention has been described in the context of a cellular telecommunications network. However, embodiments of the present invention may be implemented in any suitable wireless communication system.

Embodiments of the present invention are not just limited to applications in wireless communication networks. Embodiments of the present invention can be used in any situation where a nonlinear amplifier is used in combination with predistortion means.

22

Claims

1. An amplifying circuit comprising:

predistortion means for receiving an input signal and applying a predistortion thereto to provide a predistorted signal; amplifier means for amplifying the predistorted signal and providing an output signal; and means for comparing the input signal with the output signal and modifying in dependence on the difference between said input and output signals the predistortion to be applied by the predistortion means to a subsequent input signal, wherein an adaption characteristic of the comparing and amplifying means is alterable to reflect changes in the difference between the input and output signals.

2. A circuit as claimed in claim 1 wherein said adaption characteristic is alterable in dependence on the difference between the input and output signals.

3. A circuit as claimed in claim 1, wherein said adaption characteristic is altered after a predetermined length of time.

4. A circuit as claimed in claim 2 or 3, wherein the predistortion means is arranged to apply at least one predistortion value to the input signal to provide the predistorted signal.

5. A circuit as claimed in claim 1, 2, 3 or 4, wherein the at least one predistortion value applied to the input signal is dependent on one or more characteristics of the input signal.

6. A circuit as claimed in claim 5, wherein one or more characteristics of the input signal is amplitude or a characteristic dependent on amplitude.

7. A circuit as claimed in claim 4, 5 or 6, wherein the comparing 23 and modifying means updates the at least one predistortion value used by the predistortion means to predistort the input signal, in dependence on the result of the comparison to provide at least one new predistortion value, the said at least one new predistortion value being used by the predistortion means to predistort a subsequent input signal.

8. A circuit as claimed in any preceding claim, wherein the adaption characteristic of said comparing and modifying means which is altered is the frequency with which the comparing and modifying means compares the input and output signals.

9. A circuit as claimed in claim 8, wherein the frequency is higher when there is a relatively large difference between the input and output signals and the frequency is lower when there is a relatively small difference between the input and output signals.

10. A circuit as claimed in claim 8 or 9, wherein the predistortion means receives a first clock signal and the comparing and modifying means receives a second clock signal for controlling the frequency of said comparisons, said second clock signal being derived from the first clock signal.

11. A circuit as claimed in claim 10, wherein clock frequency dividing means are provided for dividing the first clock signal, said dividing means receiving an input setting the amount by which the first clock signal frequency is to be divided to provide the second clock signal.

12. A circuit as claimed in claim 11, wherein in said input to said clock frequency dividing means is derived from the result of the comparison performed by the comparing means.

13. A circuit as claimed in claim 8, 9, 10 or 11 wherein the frequency of said comparisons alters after a predetermined time.

24

14. A circuit as claimed in any preceding claim, wherein the adaption characteristic of said comparing and modifying means which is altered is the step size of the modification provided by said comparing and modifying means to the predistortion to be applied to a subsequent input signal.

15. A circuit as claimed in claim 14, wherein the step size is relatively large when there is a relatively large difference between the input and output signals and the step size is smaller when there is a relatively small difference between the input and output signals.

16. A circuit as claimed in claim 14 or 15 when appended to claim 7, the difference between the new and old predistortion values will be relatively large if the stepsize is relatively large and the difference between the new and old predistortion values will be relatively small if the stepsize is smaller.

17. A circuit as claimed in any of claims 5 to 16 when appended to claim 7, wherein memory means are provided for storing a plurality of predistortion values.

18. A circuit as claimed in claim 17, wherein an address calculation block is provided to calculate an address from which the at least one predistortion value is obtained, the address being calculated based on a parameter of said input signal.

19. A circuit as claimed in claim 18, wherein said parameter is amplitude or a parameter based on amplitude.

20. A circuit as claimed in any preceding claim, wherein delay means are provided to ensure that the output signal is compared with the corresponding input signal.

21. A circuit as claimed in any preceding claim, wherein the predistortion means is arranged to compensate for non linearities in said amplifier means so that the output signal is linearly amplified with respect to the input signal.

22. A circuit as claimed in any preceding claim, wherein said comparing and modifying means uses a least mean square algorithm to determine the modified predistortion to be applied by the predistortion means to a subsequent input signal.

23. A circuit as claimed in any preceding claim, wherein said predistortion means uses predistortion based on predistortion in Cartesian form.

24. A circuit as claimed in any one of claims 1 to 22, wherein said predistortion means uses predistortion based on predistortion in polar form.

25. A circuit as claimed in claim 24, wherein means are provided for converting said input signal into polar form prior to predistortion and converting the predistorted signal to rectangular form after predistortion and prior to amplifying.

26. A transmitter incorporating a circuit as claimed in any preceding claim.

27. A mobile station or base transceiver station incorporating a transmitter as claimed in claim 26.

28. A method comprising the steps of: receiving an input signal and applying a predistortion thereto to provide a predistorted signal; amplifying the predistorted signal and providing an output signal; comparing the input signal with the output signal and modifying in dependence on the difference between the input and output signals the predistortion applied by the predistortion means to a subsequent input signal; and altering an adaption characteristic of said comparing and modifying means to reflect changes in the difference between the 26 input and output signals.