GB2333915A - Base current compensation in a PLL charge pump circuit - Google Patents
Base current compensation in a PLL charge pump circuit Download PDFInfo
- Publication number
- GB2333915A GB2333915A GB9802302A GB9802302A GB2333915A GB 2333915 A GB2333915 A GB 2333915A GB 9802302 A GB9802302 A GB 9802302A GB 9802302 A GB9802302 A GB 9802302A GB 2333915 A GB2333915 A GB 2333915A
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- United Kingdom
- Prior art keywords
- current
- transistor
- base
- compensating
- charge pump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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- 238000000034 method Methods 0.000 claims description 10
- 238000012544 monitoring process Methods 0.000 claims description 2
- 238000010276 construction Methods 0.000 abstract description 2
- 239000003990 capacitor Substances 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 229920000729 poly(L-lysine) polymer Polymers 0.000 description 2
- 238000012358 sourcing Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
- H03L7/0895—Details of the current generators
- H03L7/0896—Details of the current generators the current generators being controlled by differential up-down pulses
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
- H03K17/66—Switching arrangements for passing the current in either direction at will; Switching arrangements for reversing the current at will
- H03K17/665—Switching arrangements for passing the current in either direction at will; Switching arrangements for reversing the current at will connected to one load terminal only
- H03K17/666—Switching arrangements for passing the current in either direction at will; Switching arrangements for reversing the current at will connected to one load terminal only the output circuit comprising more than one controlled bipolar transistor
- H03K17/667—Switching arrangements for passing the current in either direction at will; Switching arrangements for reversing the current at will connected to one load terminal only the output circuit comprising more than one controlled bipolar transistor using complementary bipolar transistors
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Lateral PNP current switching transistor Q11 has a low current gain so that a significant proportion of the current 15 applied to its emitter is lost in its base circuit. To compensate for this current loss, a current Icomp is added to 15. This compensating current is derived from transistor Q6 via mirror circuits 7 and 8. Q6 conducts the base current from PNP transistors Q4 and Q5, which are similar in construction to Q11 and carry a similar current. The matching of Isource and Isink is improved.
Description
CURRENT COMPENSATION IN BIPOLAR CHARGE PUXP CIRCUITS
The present invention relates to a transistor base current compensation circuit, particularly for use in charge pump circuits.
Charge pumps are electronic devices for sourcing or sinking current to or from an output. Charge pumps are often used in phase locked loop (PLL) phase detector circuits as a means of comparing the phase difference between an input signal and a reference signal. The charge pump is used to charge or discharge a capacitor in an RC network which provides a voltage output which is related to the phase difference between the input and reference signals. This voltage can then be used to control a voltage controlled oscillator of the phase locked loop.
When a charge pump is being used in the phase detector of a phase locked loop, the source current and the sink current are preferably closely matched. This can be achieved by using a common reference current and using current mirrors to "copy" that current to the current source and current sink circuits. This technique provides substantially equal sink and source currents which are largely independent of variation in the circuit parameters due to variations in temperature and supply voltage.
Whilst fairly simple current mirrors can be constructed out of relatively few components, because they utilise bi-polar transistors, biasing base current is needed. This can affect the balance of the current mirror, because some of the mirrored current is "lost" as bias current. In particular, if the transistors used have relatively low current gain (ss or hfe), this base current represents a significant portion of the mirrored current.
Furthermore, if different transistors within the circuit (e.g. PNP and NPN) have different values of current gain, the effect is uneven. This can have a significant effect on the operation of the current mirror such that the supposedly balanced currents are significantly different.
This can be a problem with integrated circuits. In particular the P of lateral PNP transistors manufactured in many anolog IC processes can be signficantly lower than that of a standard vertical NPN.
Therefore, the present invention provides a method of compensating for base current in a first transistor carrying a first current, comprising:
monitoring the base current of a second transistor arranged to carry a similar current to the first transistor and having similar characteristics such that the base currents in the first and second transistors are substantially the same;
producing a compensating current having the same magnitude as the base current of the second transistor; and
adding the compensating current to the first transistor.
By utilising a second transistor having similar characteristics to the first, the current gain of the second transistor is preferably the same or at least close to that of the first transistor. Therefore, for a given current through the transistors, each will have the same base current. The compensation current is theoretically equal to the base current flowing out of the base such that the effect is to give the appearance that there is no base current.
The present invention is applicable to both PNP and
NPN transistors. Depending on the type of transistor, the base current will flow into or out of the transistor.
Consequently, the compensating current may be positive or negative accordingly. Therefore, where this specification refers to the addition of compensating current to allow for base current leaving the transistor, this is intended to cover also the removal of compensating current to allow for base current into the transistor.
The present invention further provides a base current compensating apparatus comprising:
a first transistor for carrying a current;
a second transistor, having similar characteristics to the first transistor, arranged to carry a current substantially the same as the first current, such that the base currents of both the first and second transistor are substantially the same; and
a current source for providing to the first transistor a compensating current, which is the same magnitude as the base current of the second transistor.
The present invention compensates for the base current needed to drive the transistors so that the sink and source currents of the charge pump output more closely match the reference current and hence each other.
Whilst it is indicated above that charge pump circuits are commonly used in PLLs, it is not intended that the bias current compensation of the present invention be limited to use in PLLs or charge pump circuits. Furthermore, the compensation circuit of the present invention is equally applicable to circuits comprised of discrete components as well as integrated circuits.
The present invention will be more clearly understood from the following description, given by way of example only, with reference to the accompanying drawings in which:
Figure 1 is a schematic diagram showing the use of a charge pump circuit in a phase comparator;
Figure 2 shows how the phase comparator operates under different input signals;
Figure 3 shows a current reference based charge pump circuit without compensation; and
Figure 4 shows a current reference charge pump circuit with compensation.
Most modern phase detectors are inherently digital in nature and the charge pump forms an integral part of the output stage as a means of controlling the voltage feedback to the voltage controlled oscillator. The charge pump operates by sourcing or sinking a predetermined current to or from a capacitor in an RC network according to the relative phases of an input and a reference signal.
Referring to Figure 1, the input signal (IN~A) and the reference signal (IN~REF) are fed to a phase detector which compares the phases of the two signals and provides a pair of output control signals for controlling the source and sink currents of the charge pump circuit. It can be seen from Figure 2 that when the phase of the reference signal (IN~REF) preceeds that of the input signal (IN~A), the switch (S1) feeding the source current to the RC network is turned on, increasing the charge on the capacitor C. This continues for a time At corresponding to the phase lag between the reference and input signals.
In contrast, when the input signal leads the reference signal, the switch (S2) controlling the sink current is turned on and the charge on the capacitor in the RC network is reduced. Similarly, this continues for a time At' which corresponds to the time lag between the input signal and the reference signal. Where the phases of the input and reference signals are matched, then the phase detector does not turn either of the source or sink currents on and the charge on the capacitor remains substantially constant.
Thus, if the input signal lags behind the reference signal, current is fed into the capacitor and this causes an increase in the frequency of the output from the VCO which tends to reduce the phase gap by advancing the input signal. Similarly, if the input signal leads the reference signal, causing current to be removed from the capacitor, the voltage across the capacitor drops causing the frequency of the voltage controlled oscillator to reduce.
This tends to delay the input signal (IN~A). Clearly if the input and reference signals are matched, then the frequency of the voltage control oscillator is correct and so the voltage fed to it from the capacitor is correct.
The above relates to one possible arrangement of the system. In particular, whether the charge pump output acts as a source or sink during a phase lag will depend on whether the VCO frequency increases or decreases with the control voltage.
If the sink and source currents of the charge pump are asymmetrical then a phase lag and a phase lead will affect the VCO differently. This can lead to instability in the settling time of the VCO. Furthermore, unbalanced source and sink currents can lead to the presence of sidebands around the VCO carrier frequency at +n.fref, where n = 1, 2, 3, 4 etc and represent the fundamental and harmonics of the phase detector reference frequency (IN~REF).
As indicated above, it is therefore desirable to balance the source and sink currents as closely as possible. Figure 3 shows an example of a circuit which sets out to provide a charge pump with a source current and sink current substantially equal to a reference current ( IREF ) The circuit of Figure 3 is described below in detail.
The first part of the charge pump drive circuit section 1, includes a reference current source (I,,) which is used to set the appropriate magnitude of the output source and sink currents. The relative magnitude of the sink and source current controls the response time of the
PLL. Transistors Q1, Q3 and Q7 are chosen to have the same geometry such that they have similar characteristics.
Whilst it is desirable to have identical characteristics, in practice there may be slight variations due to variations in materials and production. Consequently the collector current of Q1 will be matched by the collector currents of Q3 and Q7. Consequently, currents I3 and I7 will be substantially the same as IEF. Section 2 of the circuit is a differential amplifier which is fed with an input and its inverse from the phase detector.
Logic input A is fully differential. Signals A and A represent a differential logic signal. Logic high (=1) corresponds to a pair of signals on A & A, in which the voltage on A is higher than that on A by 200mV or more. In contrast logic low (=0) corresponds to a pair of signals on
A and A in which the voltage on A is lower than that on A by 200mV or more. These are negative voltage levels.
Logic input B is similarly fully differentiated. If the voltage of A is greater than that of A by about 200mV or more, then Q8 will be turned off and Q9 will carry all the current I7. The reverse will apply when A is greater than A by a similar amount. If A, the control signal from the phase comparator, is low, then Q8 is turned on and a current I7 is fed from the supply rail via Q8.
However, when A is high, Q9 is turned on and Q8 is turned off. Thus, all of the current I7 is provided from transistor Q9, as current I9 which acts as the reference in another current mirror shown in section 3. R7 and R9 are matched and again, Q12 and Q13 are arranged to have the same geometry. Consequently, the current I9 is mirrored across to the collector current of Q13 which corresponds to the source current of the charge pump. Consequently, when
A is high, the source current is substantially equal to IEF (assuming the P of transistors is high).
Section 4 of the circuit is also a current mirror which operates in a similar manner to section 3 mirroring the current I3 to the output of transistor Q5 such that I5 is substantially the same as I3 and hence IEF (provided 1bias is small compared to I3). Again R5 and R6 are matched and Q4 and Q5 are arranged to have the same geometry. The current I5 is fed into section 5 of the circuit, which is another differential amplifier controlled by input B and its inverse B fed from the phase detector. Similarly to section 2, if B is low, current I5 is passed through transistor Q11. If B is high and hence B is low, then the current I5 is fed through transistor Q10 to ground. Where
B changes to high (and hence B is low), I5 is fed through
Q11 and consequently I11 is substantially the same as
Section 6 is again a current mirror which mirrors the current I11 to the collector current of Q16 which corresponds to the sink current of the charge pump.
In the description of the circuit of Figure 3 above, it has been assumed that the base current of the transistors is negligible in comparison to the collector and emitter currents. On the basis of this assumption, the currents on both sides of the current mirror circuits are practically identical and all the current passing through the transistors Q8 to Q11 pass directly from the collector to the emitter or vice versa. This assumption is reasonable where the current gain of the transistors is high.
However, particularly, in mass produced integrated circuits, this is often not the case and furthermore, the current gain of PNP compared to NPN type transistors is often significantly different (and usually less) within the same integrated circuit.
It is possible to show that the value of the source current 1SOURCE is given by:
(1 (1) Isource= - 1 Bp(f+Ep) j Isource= Where Bn and Bp are respectively the NPN and PNP transistor DC beta values. 1bias shown in sections 3 and 4 of the circuit are the bias currents necessary to ensure that transistors Q6 and Q14 are operating in the region having adequate current gain and is typically in the region of 2 to 3 microamps. In a typical IC implementation of the circuit of Figure 3, Bp could be as low as 4 whilst Bn would probably be greater than 50. Iref is typically greater than 20 microamps and so it is significantly bigger than Ibjas Therefore equation (1) can be approximated as follows:
Source Iref (2) 2 Bp Bp(?+Bp) ( From this equation, it can be seen that 1source will be approximately 90% of I ref.
The circuit for providing the sink current includes an extra stage over that for the circuit for providing the source current. Consequently the expression for the sink current is somewhat more complicated. Furthermore, only stage 3 of the circuit for the source current contains PNP transistors, whereas both stages 4 and 5 of the circuit for the sink current contain PNP transistors. The equation for the sink current 1sink is thus:
Isink=- 1+Bp 3 + Bun I Bn} {1+ Bp(f+Bp) }.{1+ 2 (3) Again, if we assume that Bn is high and that 1bias is much smaller than Iref then we can rewrite equation (3) I,i, as follows:
Isink= Iref = Isource (4) 2 Bpl Bp(?+Bp) } { 1 From this equation, assuming that Bp equals 4, then it can be seen that 1sink is approximately 80% of the value 1source and that this value decreases as Bp becomes smaller.
This imbalance is dominated by the potentially large value of base current which is taken from Q11 when B is on and Q11 is biased on. Where the current gain (Bn) is 4, 20% of the current from the current source Q5 is lost in the base bias current of Qll.
This loss of current from the base can clearly be reduced by improving the current gain of the transistor.
However, this leads to significant increases in the cost of processing and number of processing stages.
The present invention therefore aims to overcome this problem of the difference in the source and sink currents without the need to improve the current gain. Rather than trying to reduce the base bias current, it is proposed to compensate for the "lost" base current by adding in extra current. However, as the current gain Bp would not be known exactly until the circuit was constructed, it is difficult to predict in advance what the base current would be.
However, the construction of the circuit of Figure 3 is such that the current I5 which flows into the transistor
Q11 is similar to that flowing through Q4. As Q4 and Qil are devices having the same geometry, then the bias currents flowing from their bases are similar. Bias current from Q4 and the bias current from Q5, which because of the similar geometries of Q4 and Q5 are the same, flow into the emitter of Q6. Thus the current flowing into Q6 is equal to two times the base current flowing from Q4 plus the current Bias. This current is thus approximately double the current flowing from the base Qll by analogy.
Therefore, by modifying Figure 3 as shown in Figure 4 to introduce sections 7 and 8, the current flowing from Q6 can be used to provide a compensation current which is added to the current flowing from Q5. With this in mind, the current I6 flowing from Q6 is fed into a simple 2:1 current mirror with the resistors R102 and R103 having a ratio of 1:2 respectively. This mirror reproduces the current flowing into Q100 halved as the current flowing into Q101.
Thus the current flowing into Ql01, I101 is approximately equal to the base current flowing out of Qll. Iioi is fed into another current mirror in section 8 which provides a current source from Q103 which provides the compensating current Icy~. Thus the current from Q103 is added to the current from Q5 at point A on Figure 4. The value of the collector current of Q103 (IComp) can be expressed as follows:
(5) Is Icomp-- 2 2 Bn ) ( 3p. (1+bop) ) Where
(6) Is= IbiasBp+ 2 f Iref ~ Ibias 1+Bp (l+BP)l+3p(f+3p) (1+BP):1, 2 il+ 2 \ (1+bop) t Bp(l+Bp) \ Bp. (l+Bp) / J This equation can be simplified to:
Ibias + Iref (7 Icomp- 2 (1+Bp) As indicated above, 1bias is typically significantly smaller than Iref and therefore ICow is approximately equal to the current lost from the base of Qil.
The circuit of Figure 4 does contain a number of additional components over the basic circuit of Figure 3.
However, the addition of a few extra components to an integrated circuit adds little to the cost of production relative to improving the fabrication process such that the current gain is higher. Therefore, the present invention provides a means to compensate for poor current gain in integrated circuits without needing to resort to more expensive fabrication methods.
Claims (13)
1. A method of compensating for base current in a first transistor carrying a first current, comprising:
monitoring the base current of a second transistor arranged to carry a similar current to the first transistor and having similar characteristics such that the base currents in the first and second transistors are substantially the same;
producing a compensating current having the same magnitude as the base current of the second transistor; and
adding the compensating current to the first transistor.
2. A method according to claim 1, wherein the step of producing the compensating current comprises controlling a current source or sink.
3. A method according to claim 1 or 2, wherein the step of producing the compensating current includes using a current mirror into which a reference current, substantially equal to the base current of the second transistor, is fed to mirror the reference current of the second transistor to produce the compensating current.
4. A base current compensating apparatus comprising:
a first transistor for carrying a current;
a second transistor, having similar characteristics to the first transistor, arranged to carry a current substantially the same as the first current, such that the base currents of both the first and second transistor are substantially the same; and
a current source for providing to the first transistor a compensating current, which is the same magnitude as the base current of the second transistor.
5. An apparatus according to claim 4, wherein the current source includes a current mirror for mirroring the base current of the second transistor to produce the compensating current.
6. An apparatus according to claim 4 or 5, wherein the first and second transistors are PNP, bi-polar transistors.
7. An apparatus according to any one of claims 4 to 6, wherein the first and second transistors are part of an integrated circuit.
8. An apparatus according to any one of claims 4 to 7, wherein the first transistor is operating as a switch.
9. An apparatus according to any one of claims 4 to 8, wherein the first transitor forms part of a differential amplifier.
10. A charge pump circuit comprising an apparatus according to any one of claims 4 to 9.
11. A charge pump comprising a transistor operating according to a method of any one of claims 1 to 3.
12. A method of compensating for base current in a transistor substantially as described herein with reference to the accompanying drawings.
13. An apparatus substantially as described herein with reference to the accompanying drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9802302A GB2333915A (en) | 1998-02-03 | 1998-02-03 | Base current compensation in a PLL charge pump circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9802302A GB2333915A (en) | 1998-02-03 | 1998-02-03 | Base current compensation in a PLL charge pump circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9802302D0 GB9802302D0 (en) | 1998-04-01 |
| GB2333915A true GB2333915A (en) | 1999-08-04 |
Family
ID=10826392
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9802302A Withdrawn GB2333915A (en) | 1998-02-03 | 1998-02-03 | Base current compensation in a PLL charge pump circuit |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2333915A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9843255B1 (en) | 2014-12-08 | 2017-12-12 | Nxp Usa, Inc. | Charge pump apparatus, phase-locked loop, and method of operating a charge pump apparatus |
| EP3255796A1 (en) * | 2016-06-08 | 2017-12-13 | NXP USA, Inc. | Method and apparatus for generating a charge pump control signal |
| US10270397B2 (en) | 2016-10-24 | 2019-04-23 | Nxp Usa, Inc. | Amplifier devices with input line termination circuits |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4714900A (en) * | 1985-11-21 | 1987-12-22 | Nec Corporation | Current output circuit having well-balanced output currents of opposite polarities |
| US4843342A (en) * | 1987-12-09 | 1989-06-27 | Vtc Incorporated | Differential amplifier with input bias current cancellation |
| US5184028A (en) * | 1992-06-15 | 1993-02-02 | Motorola, Inc. | Current compensating charge pump circuit |
| US5302915A (en) * | 1993-01-29 | 1994-04-12 | National Semiconductor Corporation | Unity-gain, wide bandwidth, bipolar voltage follower with a very low input current |
| US5483150A (en) * | 1993-02-05 | 1996-01-09 | Hughes Aircraft Company | Transistor current switch array for digital-to-analog converter (DAC) including bias current compensation for individual transistor current gain and thermally induced base-emitter voltage drop variation |
-
1998
- 1998-02-03 GB GB9802302A patent/GB2333915A/en not_active Withdrawn
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4714900A (en) * | 1985-11-21 | 1987-12-22 | Nec Corporation | Current output circuit having well-balanced output currents of opposite polarities |
| US4843342A (en) * | 1987-12-09 | 1989-06-27 | Vtc Incorporated | Differential amplifier with input bias current cancellation |
| US5184028A (en) * | 1992-06-15 | 1993-02-02 | Motorola, Inc. | Current compensating charge pump circuit |
| US5302915A (en) * | 1993-01-29 | 1994-04-12 | National Semiconductor Corporation | Unity-gain, wide bandwidth, bipolar voltage follower with a very low input current |
| US5483150A (en) * | 1993-02-05 | 1996-01-09 | Hughes Aircraft Company | Transistor current switch array for digital-to-analog converter (DAC) including bias current compensation for individual transistor current gain and thermally induced base-emitter voltage drop variation |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9843255B1 (en) | 2014-12-08 | 2017-12-12 | Nxp Usa, Inc. | Charge pump apparatus, phase-locked loop, and method of operating a charge pump apparatus |
| EP3255796A1 (en) * | 2016-06-08 | 2017-12-13 | NXP USA, Inc. | Method and apparatus for generating a charge pump control signal |
| CN107482902A (en) * | 2016-06-08 | 2017-12-15 | 恩智浦美国有限公司 | Method and apparatus for producing charge pump control signal |
| US10381051B2 (en) | 2016-06-08 | 2019-08-13 | Nxp Usa, Inc. | Method and apparatus for generating a charge pump control signal |
| CN107482902B (en) * | 2016-06-08 | 2021-01-22 | 恩智浦美国有限公司 | Method and apparatus for generating a charge pump control signal |
| US10270397B2 (en) | 2016-10-24 | 2019-04-23 | Nxp Usa, Inc. | Amplifier devices with input line termination circuits |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9802302D0 (en) | 1998-04-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |