GB2331678A - Controlling data flow in a synchronous data compression system - Google Patents
Controlling data flow in a synchronous data compression system Download PDFInfo
- Publication number
- GB2331678A GB2331678A GB9724913A GB9724913A GB2331678A GB 2331678 A GB2331678 A GB 2331678A GB 9724913 A GB9724913 A GB 9724913A GB 9724913 A GB9724913 A GB 9724913A GB 2331678 A GB2331678 A GB 2331678A
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- data
- clock signal
- synchronous clock
- amount
- frequency
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/05—Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate
Abstract
The apparatus controls a flow of data being transmitted via a buffer 34, in order to prevent the buffer from being overflowed or underflowed, by continuously detecting an amount of data contained in the buffer and producing a synchronous clock signal SYN having a variable frequency which varies according to the amount of data contained in the buffer. That is, if a surplus amount of data is contained in the buffer, the synchronous clock signal having a lower frequency is produced in order to reduce an amount of data being inputted to the buffer. On the other hand, if the buffer does not contain a proper amount of data therein, the synchronous clock signal having a higher frequency is generated to increase the amount of data being inputted to the buffer. By controlling the data flow as described above, data compression and decompression, Fig.5, (not shown), are continuously implemented and the data throughput through the encoding system 32, the transmission channel, and the decoding system can be also improved.
Description
'f.
2331678 METHOD AND APPARATUS FOR CONTROLLING A DATA FLOW IN A SYNCHRONOUS DATA COMPRESSION SYSTEM The present invention relates to a synchronous data compression system; and, more particularly, to a method and apparatus capable of effectively controlling a data flow in the synchronous data compression system in order to improve a data throughput.
is The available frequency bandwidth of a conventional transmission channel is limited so that, in order to transmit a large amount of data therethrough, various types of data transmission systems such as a modem employs effective data compression techniques capable of compressing or reducing the volume of transmission data.
one of the compression techniques is the CCITT V.42 bis standardization employing an asynchronous data compression algorithm which was standardized by the international Telecommunication Union (ITU). By using the asynchronous data compression algorithm, digital data, e.g., strings of characters received from a data terminal equipment (DTE), can be normally compressed without seriously affecting its integrity because there usually exist certain correlationships or redundancies therein. The compressed data, i.e., codewords - 1 0 1 1 is are coupled to a buffer and then outputted at a predetermined data rate to a transmission channel having a limited bandwidth.
Since, however, an input data transmission rate of the buffer is different from an output data transmission rate thereof and a data capacity of the buffer is limited, it can occur a data overflow or underflow at the buffer. Accordingly, in order to prevent the buffer from being overflowed or underflowed, a data flow in the data transmission system is controlled by the volume of data stored at the buffer.
In Figs. 1 and 2, there are provided exemplary data encoding and decoding systems, respectively. Hereinafter, their operations will be described with reference to Fig. 3 providing an exemplary timing diagram of control signals used at the encoding and the decoding systems.
In the asynchronous data compression, input data supplied from a data providing unit, e.g., a data terminal equipment, is sequentially fed to a data storage block 10 to be stored temporarily. The input data is then coupled to an encoder 12 in response to an asynchronous clock signal ASYN derived from a controller 16. The encoder 12 compresses the input data coupled from the data storage block 10 by using known data compression techniques such as a discrete cosine transform (DCT) and a variable length coding techniques and provides coded data, i.e., codewords, to a transmission channel via a 2 c b buffer 14.
in the above encoding system, to produce the asynchronous clock signal ASYN controlling the data output operation of the data storage block 10, the controller 16 detects whether an amount of codewords stored at the buffer 14 exceeds a predetermined threshold_high, or reaches below a predetermined threshold_low, and then generates an enable signal ENABLE corresponding to the detection result, wherein the threshold_high corresponds to a maximum amount of codewords stored at the buffer 14 capable of preventing the data overflow and the threshold_low corresponds to a minimum amount of codewords stored at the buffer 14 capable of precluding the data underflow. The enable signal ENABLE is changed from a logic high level to a logic low level if the amount of codewords stored at the buffer 14 becomes greater than or equal to the threshold_high. On the other hand, if the amount of codewords becomes smaller than or equal to the threshold-low, the enable signal ENABLE is changed from a logic low level to a logic high level.
once the enable signal ENABLE is generated as shown in Fig. 3, the asynchronous clock signal ASYN containing a plurality of periods, e.g., Al, B1, A2, and B2, is produced based on the enable signal ENABLE and a clock signal CLOCK having a constant frequency generated at a clock generator 18. That is, the asynchronous clock signal ASYN contains enabled clock signals if the enable signal ENABLE is in a high level, 3 - 1 is and is disabled if otherwise. Therefore, in case the asynchronous clock signal ASYN is in the periods Al and A2, the input data stored at the data storage block 10 can be inputted to the encoder 12. On the other hand, in case the asynchronous clock signal ASYN is in the periods B1 and B2, the input data stored at the data storage block 10 cannot be supplied to the encoder 12 and the periods 21 and B2 are referred to as idle. At an idle period, the data compression procedure at the encoder 12 is not implemented. Accordingly, it is noticed that the data compression procedure at the encoder 12 is repeatedly interrupted according to the data storage status at the buffer 14 and the interruption of the data compression can deteriorate a data throughput.
In the meanwhile, similar to the data encoding system, in the data decoding system in Fig. 2, the codewords transmitted through the transmission channel are sequentially fed to a codeword storage block 20 which, in turn, the codeword storage block 20 provides the codewords stored therein to a buffer 22 in response to an asynchronous clock signal ASYN retrieved from a controller 26, wherein the asynchronous clock signal ASYN is determined in the same manner as in the encoding system. in other words, referring to Fig. 3, the controller 26 checks an amount of codewords BT stored at the buffer 22; produces an enable s-ignal ENA LE based on the checking result; and generates the asynchronous clock signal ASYN by using the enable signal ENABLE and a 4 L'11 1 is clock signal CLOCK having a constant frequency derived from a clock generator 28.
Referring back to Fig. 2, the buffer 22 outputs the codewords fed thereto to a decoder 24 and the decoder 24 converts the transferred codewords into decoded data by using known decompression techniques such as an inverse discrete cosine transform (IDCT) and a variable length decoding techniques.
During the data decompression, the data flow between the codeword storage block 20, the buffer 22, and the decoder 24 is continuously adjusted by the asynchronous clock signal ASYN. However, as can be seen in Fig. 3, since the control signals used in the decoding system also have almost same signal patterns as those of the encoding system, it is readily understood that the data flow in the decoding system is repeatedly interrupted according to the data storage status at the buffer 22 and it may make the effective usage of the codeword storage block 20 and the buffer 22 difficult.
To overcome the drawbacks of the asynchronous data compression, a synchronous data compression has been introduced. However, apart from the existing CCITT V.42 bis standard for the asynchronous data compression, the synchronous data compression is not yet standardized.
Also, in the conventional data compression, e.g., the asynchronous data compression, if the data overflow or underflow occurs at the buffer, the data compression or b decompression process is stopped and then resumed after the problems being resolved. Since, however, the synchronous data compression requires a continuous data compression, the above data flow control technique used at the asynchronous data compression cannot be applied to the synchronous data compression.
It is, therefore, a primary object of the invention to provide a data flow control method and apparatus which can be properly applied to a synchronous data compression and decompression and can improve a data throughput.
In accordance with one aspect of the present invention, there is provided a method for controlling a data flow in a synchronous data compression system for processing input data, which comprises the steps of: (a) receiving the input data and sequentially providing it in response to a synchronous clock signal having a variable frequency; (b) storing,the provided data and supplying it at a predetermined data transmission rate; (c) detecting an amount of the stored data and comparing it with threshold values; (d) generating a new synchronous clock signal based on the comparison result and updating the synchronous clock signal at the step (a) by using the new synchronous clock signal; and (e) repeating the steps (a) to (d) until all of the input data are processed.
In accordance with another aspect of the present 6 0 1 is invention, there is provided an apparatus for controlling a data flow in a synchronous data compression system for processing input data, which comprises: a data storage block for receiving the input data and sequentially providing it in response to a synchronous clock signal having a variable frequency; a buffer for reserving the provided data and supplying it at a predetermined data transmission rate; a controller for detecting an amount of the reserved data and generating a frequency control signal by comparing the amount of the reserved data with threshold values; 'and a clock generator for producing a new synchronous clock signal in response to the frequency control signal and providing the new synchronous clock signal as the synchronous clock signal to the data storage block.
The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which:
Fig. 1 illustrates a block diagram of an encoding system for an asynchronous data compression; Fig. 2 provides a block diagram of a decoding system for an asynchronous data compression; Fig. 3 is a timing diagram of control signals used at the encoding system in Fig. 1; 7 -i b Fig. 4 represents a block diagram of an enqoding system in accordance with the present invention; Fig. 5 shows a block diagram of a decoding system in accordance with the present invention; and Fig. 6 depicts a timing diagram of control signals used at the embodiments of the present invention.
Referring to Fig. 4, there is provided a block diagram of an encoding system in accordance with the present invention.
As in the prior art shown in Fig. 1, input data is inputted to a data storage block 30 and stored therein temporarily. The input data stored at the data storage block 30 is supplied to an encoder 32 in response to a synchronous clock signal SYN derived from a clock generator 38.
The encoder- 32 codes the input data data storage block 30 by using known techniques to thereby produce coded data The codewords are first coupled to a transmitted through a transmission channel The buffer 34 provides the codewords appropriate data transmission rate to channel.
However, since the input data coupled to the encoder 32 are encoded into codewords having various lengths, the output provided from the data compression i.e., codewords. buffer 34 to be fed thereto at an the transmission - 8 h data transmission rate of the encoder 32 cannot be constant all the time and an overf low or underf low at the buf f er 34 can occur.
In order to preclude the buffer 34 from being overflowed or underflowed, a controller 36 connected to the buffer 34 detects an amount of codewords stored at the buffer 34 to thereby produce a frequency control signal S FC For example, if the amount of codewords is greater than or equal to a threshold_high, the frequency control signal S FC is changed from a logic high level to a logic low level and maintains its present level until the amount of codewords reaches a threshold_low. On the other hand, if the amount of codewords becomes smaller than or equal to the threshold_low, the level of the frequency control signal S FC is changed from a logic low to a logic high and maintains its present level until the amount of codewords reaches the threshold_high again. The frequency control signal S FC determined by detecting a data storage status at the buffer 34 is coupled to the clock generator 38.
The clock generator 38 creates a synchronous clock signal SYN having a variable frequency by using the frequency control signal S FC inputted thereto.
As shown in Fig. 6 representing a timing diagram of control signals used at the present invention, the synchronous clock signal SYN is determined based on the frequency control signal S FC ' If the frequency control signal S FC has a logic In A high level, i. e -, in the period C1 or C2, the synchronous clock signal SYN is produced to have a higher frequency in order_to effectively use the buffer 34 and improve a data throughput. Thereafter, if the amount of codewords stored at the buffer 34 approximates to the threshold_high by the rapid data compression at the encoder 32 and, accordingly, the amount of codewords becomes greater than or equal to the threshold_high, the frequency control signal S FC is levelchanged to a logic low level. As a result, if the frequency control signal S FC has a logic low level, i.e., in the period Di or D2, the synchronous clock signal SYN having a lower frequency is generated to reduce the amount of codewords stored at the buffer 34. The synchronous clock signal SYN determined as above is delivered to the data storage block 30 in order to control the data output operation thereof.
As aforementioned, under the control of the synchronous clock signal SYN, the data storage block 30 outputs the input data to the encoder 32. According to data transmission characteristics, the amount of data to be transmitted from the data storage block 30 to the encoder 32 is proportional to the frequency of the synchronous clock signal SYN. Therefore, when the synchronous clock signal SYN has a higher frequency, the amount of data to be transmitted becomes larger.
In this way, during the data compression, the data flow between the data storage block 30 and the encoder 32 is continuously adjusted by the synchronous clock signal SYN is based on the amount of codewords included in the buffer 34 to thereby control the volume of codewords contained at the buffer 34 and prevent the buffer 34 from being overflowed or underflowed.
Meanwhile, referring to Fig. 5, there is shown a decoding system in accordance with the present invention and its operation will also be explained with reference to Fig. 6.
The codewords transmitted through the transmission channel are secluentially inputted to a codeword storage block 40. Then, the codewords are provided from the codeword storage block 40 to a buffer 42 clock signal SYN derived from a The buffer 42 outputs the in response to a synchronous clock generator 48.
codewords fed thereto to a decoder 44 which converts the codewords to decoded data. Since, however, an amount of codewords processed during the data decompression at the decoder 44 is not uniform, the buffer 42 may be overflowed or underflowed similarly to the buffer 34 in the encoding system in Fig. 4. Therefore, similar to the encoding system, a controller 46 connected to the buffer 42 generates a frequency control signal S FC in the same manner in the encoding system in Fig. 4; and a clock generator 48 provides a synchronous clock signal SYN based on the frequency control signal S FC as shown in Fig. 6.
Accordingly, the volume of codewords contained in the buffer 42 is also appropriately controlled to thereby prevent the buffer 42 from being overflowed or underflowed by using 11 1 the above data flow control process. During the data decompression, the data flow between the codeword storage block 40, the buffer 42, and the decoder 44 is continuously adjusted by the feedback control process.
In Fig. 6, although the frequency control signal S FC has two logic levels, in accordance with another embodiment of the present invention, the frequency control signal S FC can have multi-levels according to the amount of codewords contained in the buffer and thus the synchronous clock signal SYN can be also generated to have a variable' frequency having more than two different frequencies in response to the multileveled frequency control signal S FC' By controlling the data flow through the use of the feedback control process described above, the data compression and decompression are continuously performed and,' as a result, the data throughput through the encoding system, the transmission channel, and the decoding system can also be improved. In addition, the effective usage of the encoding and decoding systems can be possible.
While the present invention has been described with respect to certain preferred embodiments only, other modifications and variations may be made without departing from the scope of the present invention as set forth in the following claims.
12 1
Claims (13)
- Claims:is 1 - A method for controlling a data flow in a synchronous data compression system for processing input data, which comprises the steps of:(a) receiving the input data and sequentially outputting it in response to a synchronous clock signal having a variable frequency; (b) storing the outputted data and supplying it at a predetermined data transmission rate; (c) detecting an amount of the stored data and comparing it with threshold values; (d) generating a new synchronous clock signal based on the comparison result and updating the synchronous clock signal at step (a) with the new synchronous clock signal; and (e) repeating the steps (a) to (d) until all of the input data are processed.
- 2. The method according to claim 1, wherein the synchronous clock signal is produced to have one of two different frequencies, a lower one and a higher one, and the step (d) includes the steps of:(di) producing the synchronous clock signal having the lower frequency if the amount of the stored data is greater than or equal to a threshold_high; and (d2) generating the synchronous clock signal having the - 13 1 I higher frequency if the amount of the stored data is smaller than or equal to a threshold-low.is
- 3. The method according to claim 2, wherein the threshold_high represents a maximum amount of the stored data capable of preventing a data overflow at the step (b).
- 4. The method according to claim 2, wherein the threshold_low depicts a minimum amount of the stored capable of precluding a data underflow at the step (b).
- 5. The method according to claim 1, wherein the synchronous clock signal is generated to have more than two different frequencies and the frequency of the synchronous clock signal becomes lower as the amount of the stored data increases.
- 6. An apparatus for controlling a data flow in a synchronous data compression system for processing input data, which comprises: means for receiving the input data and sequentially outputting it in response to a synchronous clock signal having a variable frequency; means for reserving the outputted data and supplying it at a predetermined data transmission rate; means for detecting an amount of the reserved data and generating a frequency control signal by comparing the amount - 14 n k is of the reserved data with threshold values; and means for producing a new synchronous clock signal in response to the frequency control signal and providing the new synchronous clock signal as the synchronous clock signal to the receiving and outputting means.
- 7. The apparatus according to claim 6, wherein the frequency control signal is level-changed based on the comparison result and the frequency of the synchronous clock signal is changed by detecting the level change of the frequency control signal.
- 8. The apparatus according to claim 7, wherein the frequency control signal is determined as:(pi) if the amount of the reserved data is smaller than or equal to a threshold_low, the frequency control signal is level-changed from a logic low to a logic high; (p2) if the amount of the reserved data is greater than or equal to a threshold_high, the frequency control signal is level-changed from a logic high to a logic low; and (P3) if the amount of the reserved data is between the threshold_high and the threshold_low, the frequency control signal maintains a preceding logic level.
- 9. The apparatus according to claim 8, wherein the synchronous clock signal is generated to have one of two different frequencies, a lower one and a higher one, and the - is I synchronous clock signal is producing as:(ql) if the frequency control signal is changed from a logic high to a logic low, the synchronous clock signal has the lower frequency; and (q2) if the frequency control signal is changed from a logic low to a logic high, the synchronous clock signal has the higher frequency.
- 10. The apparatus according to claim 9, wherein the threshold-high represents a maximum amount of' 'the reserved data capable of preventing the reserving means from being overflowed.
- 11. The apparatus according to claim 9, wherein the threshold_low depicts a minimum amount of the reserved data capable of precluding the reserving means from being underflowed.
- 12. The apparatus according to claim 6, wherein the synchronous clock signal is generated to have more than two different frequencies and the frequency of the. synchronous clock signal becomes lower as the amount of the reserved data increases.
- 13. An apparatus constructed and arranged substantially as herein described with reference to or as shown in Figures 4 16 -1 t to 6 of the accompanying drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9724913A GB2331678A (en) | 1997-11-25 | 1997-11-25 | Controlling data flow in a synchronous data compression system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9724913A GB2331678A (en) | 1997-11-25 | 1997-11-25 | Controlling data flow in a synchronous data compression system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9724913D0 GB9724913D0 (en) | 1998-01-28 |
| GB2331678A true GB2331678A (en) | 1999-05-26 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9724913A Withdrawn GB2331678A (en) | 1997-11-25 | 1997-11-25 | Controlling data flow in a synchronous data compression system |
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| GB (1) | GB2331678A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2347326A (en) * | 1999-02-26 | 2000-08-30 | Mitel Inc | Text-to-speech converter |
| GB2350533A (en) * | 1999-05-28 | 2000-11-29 | Mitel Corp | Avoiding underflow or overflow in a circular buffer |
| GB2407180A (en) * | 2003-10-13 | 2005-04-20 | Lg Electronics Inc | Preventing overflow in a buffer by halting an encoder/ compressor |
| US10896021B2 (en) | 2019-02-26 | 2021-01-19 | Nvidia Corporation | Dynamically preventing audio underrun using machine learning |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0345608A2 (en) * | 1988-06-09 | 1989-12-13 | Digital Recording Research Limited Partnership | Data compression system and method with buffer control |
| EP0515101A2 (en) * | 1991-05-23 | 1992-11-25 | AT&T Corp. | Buffer control for variable bit-rate channel |
| US5434891A (en) * | 1991-05-31 | 1995-07-18 | U.S. Philips Corporation | Data transfer arrangement permitting variable rate data transfer between a modem and a synchronous terminal |
| GB2307151A (en) * | 1995-11-10 | 1997-05-14 | British Broadcasting Corp | Digital coding of video signals |
-
1997
- 1997-11-25 GB GB9724913A patent/GB2331678A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0345608A2 (en) * | 1988-06-09 | 1989-12-13 | Digital Recording Research Limited Partnership | Data compression system and method with buffer control |
| EP0515101A2 (en) * | 1991-05-23 | 1992-11-25 | AT&T Corp. | Buffer control for variable bit-rate channel |
| US5434891A (en) * | 1991-05-31 | 1995-07-18 | U.S. Philips Corporation | Data transfer arrangement permitting variable rate data transfer between a modem and a synchronous terminal |
| GB2307151A (en) * | 1995-11-10 | 1997-05-14 | British Broadcasting Corp | Digital coding of video signals |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2347326A (en) * | 1999-02-26 | 2000-08-30 | Mitel Inc | Text-to-speech converter |
| US6546366B1 (en) | 1999-02-26 | 2003-04-08 | Mitel, Inc. | Text-to-speech converter |
| GB2347326B (en) * | 1999-02-26 | 2004-04-14 | Mitel Inc | Text-to-speech converter |
| GB2350533A (en) * | 1999-05-28 | 2000-11-29 | Mitel Corp | Avoiding underflow or overflow in a circular buffer |
| GB2350533B (en) * | 1999-05-28 | 2001-07-04 | Mitel Corp | Method to control data reception buffers for packetized voice channels |
| US6721825B1 (en) | 1999-05-28 | 2004-04-13 | Mitel Corporation | Method to control data reception buffers for packetized voice channels |
| GB2407180A (en) * | 2003-10-13 | 2005-04-20 | Lg Electronics Inc | Preventing overflow in a buffer by halting an encoder/ compressor |
| GB2407180B (en) * | 2003-10-13 | 2005-12-21 | Lg Electronics Inc | Server system and method for performing communication over wireless network |
| US7581018B2 (en) | 2003-10-13 | 2009-08-25 | Lg Electronics Inc. | Server system for performing communication over wireless network |
| US10896021B2 (en) | 2019-02-26 | 2021-01-19 | Nvidia Corporation | Dynamically preventing audio underrun using machine learning |
| US11567728B2 (en) | 2019-02-26 | 2023-01-31 | Nvidia Corporation | Dynamically preventing audio artifacts |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9724913D0 (en) | 1998-01-28 |
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| Date | Code | Title | Description |
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| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |