GB2331599A

GB2331599A - Content addressable memory

Info

Publication number: GB2331599A
Application number: GB9724653A
Authority: GB
Inventors: Robert Fairlie
Original assignee: Motorola Ltd
Current assignee: Motorola Solutions UK Ltd
Priority date: 1997-11-22
Filing date: 1997-11-22
Publication date: 1999-05-26
Also published as: GB9724653D0

Abstract

A CAM array (20) uses a plurality of CAM cells to compare data stored in the CAM cells with input data and assert match signals upon detecting matches between the stored data and the input data. A plurality of sequence matching blocks (SMB n) are coupled to corresponding rows of CAM cells. Each sequence matching block asserts a sequence match signal in response to asserting the corresponding match signal received at a first input and the assertion of an adjacent sequence match signal received at a second input representing a match between second stored data and the input data. The sequence match signals are used to update a counter that keeps track of the length of the sequence match in the CAM array from which the starting location can be derived. Data can be compressed as the starting location (of a sequence of matches) and count of matches, in a history file.

Description

2331599 CONTENT ADDRESSABLE MEMORY CIRCUIT AN-D METHOD

Background of the Invention

The present invention relates in general to memory circuits and, more particularly, to content addressable memory with sequence matching blocks.

Content addressable memory (CAM) is used in a variety of applications where it necessary or desirable to compare incoming data with data stored in the memory. The classic CAM has a static data scorage cell, for example back to back inverters, and a comparison circuit. The comparison circuit compares the contents of the static storage cell with the incoming data and asserts a control signal upon detecting a match.

One application of a CAM is in the field of data compression. Computer backup systems use data compression techniques to reduce the storage requirements. By compressing the data, the backup media need only have a fraction of the capacity of the source media. Data compression is also used in communication systems to reduce the amount of data transmitted from source to destination.

A common data compression method involves comparing the incoming data to data stored in a history file implemented as a CAM. If a string of matches are found, then the incoming data is encoded as the starting location and length of the sequence match in the history file. The data compression method reduces the amount of stored or transmitted data by sending the starting location and length of the match relative to the history file instead of storing or transmitting the entire incoming data sequence. The history file is updated with the incoming data following the comparison.

Brief Description of the Drawings

FIG. 1 is a block diagram illustrating a computer backup system utilizing data compression; FIG. 2 is a block diagram illustrating the data compression block of FIG. 1; FIG. 3 is a schematic diagram illustrating further detail of the sequence matching block of FIG. 2; FIG. 4 is a schematic diagram illustrating an alternate embodiment of the sequence matching block; and FIG. 5 is a schematic diagram illustrating an alternate embodiment of the sequence matching block.

Detailed Description of the Preferred Embodiment

Referring to FIG. 1, a computer system is shown with backup capabilities. To backup computer 10, data is sent to data compression and signal processing block 12 where the data is compressed and formatted for storage on backup media 14. Examples of backup media 14 includes tape drives, external disk drives, writable CD ROM, or other suitable backup storage. The function of data compression block 12 is to compress the incoming data from computer 10 such that the storage requirements on backup media 14 are a fraction of the source volume. For example, 100 Mbytes of data from computer 10 may be compressed into 50 Mbytes on backup media 14.

Another application for data compression involves the transmission of data from source to destination. Data can be compressed at the source end, transmitted over a communication channel having a smaller bandwidth than would be required for uncompressed data, and then decompressed on the receiving end. The cost and overhead of compressing and decompressing data is acceptable especially given the smaller bandwidth and greater throughput of the communication channel.

An exemplary data compression methodology is described as follows. A history file of 1024 6-bit bytes is established in a CAM array. Each incoming data byte is compared to the history file looking for a match. If a match is found, then the next incoming data byte is compared to the subsequent entry in the history file attempting to find a sequence. Once a sequence of two or more bytes matches is identified, then the data compression method encodes the incoming data as the starting location and length of the sequence relative to the history file. For example, assume the history file contains consecutive entries 1ABCD11 in locations Ll, L2, L3, and L4. The incoming data pattern is 0ABCE". For the first incoming data "Am, the CAM array identifies a match in location Ll. The second and third incoming data "B" and 9W match the subsequent locations L2 and L3 in the history file to establish a sequence. The fourth incoming data "E" fails match the contents of location L4 and continue the sequence so the incoming data "ABC" is encoded as location LI, length 3. The incoming data "E" is checked for a match elsewhere in the history file and possibly establishes the beginning of another sequence. Any incoming data that does not establish a sequence in the history file is output as a literal, i.e. the value of the data preceded by a zero which marks it as a literal.

The relevant detail of data compression and signal processing block 12 is shown in FIG. 2. A CAM array 20 includes a plurality of CAM cells arranged in columns and rows representing the history file. Each CAM cell represents one bit of data. As an illustrative example, CAM array 20 has 8 columns and 1024 rows of CAM cells. CAM array 20 is typically implemented with dual ports, i.e. separate data and address ports allowing simultaneous read and write operations. Each row represents one byte, e.g. row n-1 for byte n-1, row n for byte n, row n+l for byte n+l, etc. Each CAM cell includes a 1-bit static storage element and a comparison circuit. Each column of CAM cells receive DATA and DATA signals, representing one bit of 1 data, which update the contents of the CAM cell (s) according to address and control signals. The COMP and COMP signals applied to each column of CAM cells represent one bit of the present incoming data to be compared with the contents of the CAM cells. Only one set of DATA and DATA and COMP and COMP signals are shown for the f irst column of CAM cells to simplify the explanation. The other seven columns of CAM cells would each have corresponding DATA and DATA and COMP and COMP ports for the other seven bits of the 8-bit byte.

CAM array 20 allows one byte of incoming data to be simultaneously compared with all 1024 bytes, i.e. all rows, in the history file. The comparison is performed on one byte of incoming data with respect to the entire history file. If the incoming data matches the stored data, then a corresponding MATCH signal is asserted. In the above example, if the incoming data "Bn matches the first row of CAM cells (byte n) shown in FIG. 2, then MATCH n goes to logic one. All other MATCH signals that do not match the incoming data "B" are logic zero. If the incoming data "C" matches the second row of CAM cells (byte n+l), then MATCH n+l goes to logic one. All other MATCH signals that do not match the incoming data "C" are logic zero.

The MATCH signals from CAM array 20 are processed through corresponding sequence match blocks (SMB) Each SMB receives the MATCH signal from one row of CAM cells and a SEQUENCE MATCH signal from a previous SMB. The SMB asserts its SEQUENCE MATCH signal if the MATCH signal is asserted and the SEQUENCE MATCH signal from the previous SMB is asserted. For example, SMB n generates SEQUENCE MATCH n as logic one if SEQUENCE MATCH n-1 is logic one and MATCH n is logic one. SEQUENCE MATCH n is logic zero otherwise. SMB n+l generates SEQUENCE MATCH n+l as logic one if SEQUENCE MATCH n is logic one and MATCH n+l is logic one. SEQUENCE MATCH n+l is logic zero otherwise. The SEQUENCE MATCH signals provide useful information as to the sequence of matches between the incoming data and the history file. Further detail of SMB n is shown in FIG. 3. The other 5MBs follow a similar construction and operation. The MATCH n signal is routed through flipflop 26 to one input of AND logic gate 28. OR gate 30 receives SEQUENCE MATCH n-1 and a FIRST control signal. The FIRST control signal is an initializing signal asserted as logic one at the beginning of each new sequence search. The output of OR 10 gate 30 is coupled to a second input of AND gate 28. The output of AND gate 28 is coupled to the data input of flipflop 32. The Q-output of flipflop 32 provides SEQUENCE MATCH n. Flipflops 26 and 32 are clocked by a SYSTEM CLOCK signal. Alternately, SEQUENCE MATCH n can be taken at the 15 output of AND gate 28. In the above example, the data compression process begins with the FIRST control signal at logic one. If incoming data "A" matches the contents of the CAM cell row n-1 (byte n-1), then MATCH n-1 is logic one. The output of 20 the OR gate 30 in SMB n-1 is logic one because the FIRST control signal is logic one, and the output of the AND gate 28 in SMB n-1 is thus logic one. SEQUENCE MATCH n-1 at the Q-output of flipflop 32 in SMB nl goes to logic one with the next SYSTEM CLOCK. A possible sequence match is in 25 process so FIRST returns to logic zero. The output of the OR gate 30 in SMB n is logic one with SEQUENCE MATCH n-1 at logic one. If incoming data "B" matches the contents of the CAM cell row n (byte n), then MATCH n is logic one and the output of the AND gate 28 in SMB n is logic one. 30 SEQUENCE MATCH n at the Q-output of flipflop 32 in SMB n goes to logic one with the next SYSTEM CLOCK indicating that the sequence continues.

The SEQUENCE MATCH n-1 returns to logic zero, assuming MATCH n-1 is now logic zero, as SEQUENCE MATCH n goes to logic one. If incoming data "C" matches the contents of the CAM cell row n+l (byte n+l), then MATCH n+l is logic one and the output of the AND gate 28 in SMB n+l is logic one. SEQUENCE MATCH n+l at the Q-output of flipflop 32 in SMB n+l goes to logic one with the next SYSTEM CLOCK indicating that the sequence continues. The SEQUENCE MATCH n returns to logic zero, assuming MATCH n is now logic zero, as SEQUENCE MATCH n+l goes to logic one. The next incoming data uE" does not match the contents of the CAM cell row n+2 (byte n+2) and the output of the AND gate 28 in SMB n+2 is logic zero. SEQUENCE MATCH n+2 at the Q-output of flipflop 32 in SMB n+2 goes to logic zero with the next SYSTEM CLOCK indicating that the sequence does not continue. The SEQUENCE MATCH n-1, SEQUENCE MATCH n and SEQUENCE MATCH n+l signals are used to update a counter (not shown) that keeps track of the length (3) of the sequence match in CAM array 20 from which the starting location (byte n-1) can be derived.

One advantage of the present invention is the continuous processing of incoming data without wasting clock cycles. The result of the previous sequence match is readily available to the next SMB to ascertain the continuity of the match sequence. For example, by feeding SEQUENCE MATCH n to SMB n+l, the AND logic gate can combine the result of the present match (byte n+l) with the result of the previous match (byte n) to determine whether the match sequence is continuing.

An alternate embodiment of the SMBs is shown in FIG. 4 with OR gate 30 eliminated. The FIRST control signal is applied to a set input of flipflop 34 in each SMB. A logic one FIRST control signal sets the Q- output of flipflop 34 in each SMB to logic one. With all SEQUENCE MATCH signals at logic one, the AND gate 36 in the SMB corresponding to the CAM cell row that matches the incoming data transitions to logic one. The SEQUENCE MATCH signal corresponding to the SMB that receives a match for the incoming data goes to logic one indicating the beginning of a match sequence. The SEQUENCE MATCH signals corresponding to the SMBs that do not receive a match for the incoming data go to logic zero indicating the absence of a match sequence. The FIRST control signal returns to logic zero and the sequence matching process continues as described above.

In the above discussion, at the end of one data matching sequence, the previous incoming data that did not match the data matching sequence must be re-applied to start a new data matching sequence. In addition, the FIRST control signal must be asserted to initialize each data matching sequence. The initialization process for each new data matching sequence involves one or more clock cycles. New data must be held up during and re-applied after the initialization process for each data matching sequence.

In order to improve the throughput of data compression block 12, an additional feature as described below avoids the initialization process at each new data matching sequence and allows new data to be presented to data compression block 12 every clock cycle. It is preferable to use a minimum number of clock cycles to detect a present match and ascertain whether the sequence match continues.

Turning to FIG. 5, another embodiment of the SMB includes flipflop 40 having a data input coupled for receiving MATCH n. The Q-output of flipflop 40 is coupled to one input of AND gate 42 and to one input of multiplexer 44. The second input of AND gate 42 receives SEQUENCE MATCH n1, and the output of AND gate 42 is coupled to a second input of multiplexer 44. The output of multiplexer 44 is coupled to a data input of flipflop 46. The Q-output of flipflop 46 provides SEQUENCE MATCH n. Multiplexer 44 is controlled by the output of AND gate 42. The output of each AND gate 42 in all 1024 SMBs is applied to inputs of NOR gate 48. NOR gate 48 can be implemented in a wired-NOR configuration. The output of NOR gate 48 is coupled to one input of OR gate 50. The FIRST control signal is applied to a second input of OR gate 50. Additional control signals (not shown), e.g. end-ofrecord or maximum sequence match, can be applied to other inputs of OR gate 50 to initialize a matching sequence. The output of OR gate 50 is coupled to the control input of multiplexer 44.

The FIRST control signal is asserted once at the beginning of the data compression. The incoming data is applied to CAM array 20 and one or more MATCH signals is set to logic one. Again assume that the incoming data "A" matches the contents of the CAM cell row n-1 so that MATCH nl is logic one. Following one SYSTEM CLOCK, the Q-output of flipflop 40 in SMB n-1 is logic one. The FIRST control signal is logic one for the beginning of the data compression so the output of OR gate 50 is logic one and multiplexer 44 passes the logic one from flipflop 40 through its conduction path to the data input of flipflop 46. SEQUENCE MATCH n-1 goes to logic one with the next SYSTEM CLOCK indicating the start of a data matching sequence. FIRST returns to logic zero.

If the next incoming data "B" matches the contents of CAM cell row n, then the Qoutput of flipflop 40 in SMB n is logic one. If the SEQUENCE MATCH n-1 is logic one, then the output of AND gate 42 in SMB n is logic one. As long as NOR gate 48 receives at least one logic one its output is logic zero. OR gate 50 sends a logic zero to multiplexer 44 which passes the logic one from AND gate 42 through its conduction path to the data input of flipflop 46. SEQUENCE MATCH n goes to logic one with the next SYSTEM CLOCK. The SEQUENCE MATCH n-1 returns to logic zero as SEQUENCE MATCH n goes to logic one. The data matching sequence continues.

If the next incoming data "B" did not match the contents of CAM cell row n, then the Q-output of flipflop 40 in SMB n is logic zero after the next SYSTEM CLOCK. The output of AND gate 42 in SMB n is logic zero. Assuming no other AND gate 42 in the other SMBs is logic one, the output of NOR gate 48 is logic one and the logic zero from flipflop 40 passes through multiplexer 44. Flipflop 46 latches- the logic zero at next SYSTEM CLOCK indicating termination of the data matching sequence.

If the next incoming data "C" matches the contents of CAM cell row n+l, then MATCH n+l is logic one and the Qoutput of flipflop 40 in SMB n+l is logic one after the next SYSTEM CLOCK. If SEQUENCE MATCH n is logic one then the output of AND gate 42 in SMB n+l is logic one. SEQUENCE MATCH n+ l goes to logic one with the next SYSTEM CLOCK. The SEQUENCE MATCH n returns to logic zero as SEQUENCE MATCH n+l goes to logic one. The data matching sequence continues.

If the next incoming data uE" does not match the contents of CAM cell row n+2, then MATCH n+2 is logic zero. The Q-output of flipflop 40 in SMB n+2 is logic zero and the output of AND gate 42 in SMB n+2 is logic zero. Assuming no other AND gate 42 in the other SMBs is logic one, the output of NOR gate 48 is logic one and the logic zero from flipflop 40 passes through multiplexer 44 to flipflop 46. SEQUENCE MATCH n+2 goes to logic zero with the next SYSTEM CLOCK indicating the end of a matching sequence. The SEQUENCE MATCH n-1, SEQUENCE MATCH n and SEQUENCE MATCH n+l signals update the counter to keep track of the length of the sequence match in CAM array 20 from which the starting location can be derived.

with the SMB embodiment in FIG. 5, the fact that incoming data "E" did not continue the previous match sequence does not require the process to begin again. When a match sequence fails to continue, then in every SMB either the MATCH signal is logic zero or the SEQUENCE MATCH signal from the previous SMB is logic zero. Therefore, the output of every AND gate 42 in the SMBs is logic zero. If the incoming data "E" matches CAM cell row n+3, then MATCH n+3 is logic one. However, SEQUENCE MATCH n+2 is logic zero as discussed above so the output of AND gate 42 in SMB n+3 is logic zero. With all AND gates 42 in the SMBs providing logic zeroes, the output of NOR gate 48 is logic one and the output of OR gate 50 is logic one. Multiplexer 44 switches to pass the logic one from flipflop 40 to the data input of flipflop 46. The SEQUENCE MATCH n+3 goes to logic one indicating the start of another potential sequence without consuming extra clock cycles or reapplying the incoming data.

In summary, the present invention uses a CAM array having a plurality of CAM cells which compares data stored in the CAM cells with input data and asserts match signals upon detecting matches between the stored data and the input data. A plurality of SMBs are coupled to corresponding rows of CAM cells. Each SMB asserts a sequence match signal in response to asserting the corresponding match signal received at a first input and the assertion of an adjacent sequence match signal received at a second input representing a match between second stored data and the input data. The sequence match signals are used to update a counter that keeps track of the length of the sequence match in CAM array 20 from which the starting location can be derived. The sequence matching process provides efficient tracking of the sequence by using a minimum number of clock cycles to determine a present match and a continuation of the match sequence.

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Claims

1. A content addressable memory (CAM) array, comprising: a plurality of CAM cells (20) for comparing stored data in the CAM cells with an input data and asserting a first match signal upon detecting a match between first stored data and the input data; and a first sequence matching block (SMB n) which asserts a first sequence match signal in response to asserting the first match signal received at a first input and asserting a second sequence match signal received at a second input where the second sequence match signal represents a match between second stored data and the input data.

2. The CAM array of claim 1 further including a second sequence matching block (SMB n+l) coupled for receiving the first sequence match signal and a second match signal from the plurality of CAM cells and asserting a third sequence match signal when the first sequence match signal and the second match signal are asserted.

3. The CAM array of claim 2 wherein the first sequence matching block includes: a first logic gate (28) having a first input coupled for receiving the first match signal, and a second input coupled for receiving the second sequence match signal; and a first flipflop (32) having a data input coupled to an output of the first logic gate, a clock input coupled for receiving a clock signal, and an output for providing the first sequence match signal.

4. The CAM array of claim 3 wherein the first sequence matching block further includes a second logic gate (30) having a first input coupled for receiving the second sequence match signal, a second input coupled for receiving an initializing control signal, and an output coupled to the second input of the first logic gate.

5. The CAM array of claim 4 wherein the second sequence matching block further includes a second flipflop (26) having a data input coupled for receiving the first match signal, a clock input coupled for receiving the clock signal, and an output coupled to the first input of the first logic gate.

6. The CAM array of claim 3 wherein the first flipflop further includes a set input coupled for receiving an initializing control signal.

7. The CAM array of claim 2 wherein the first sequence matching block includes: a first logic gate (42) having a first input coupled for receiving the first match signal, and a second input coupled for receiving the second sequence match signal; a multiplexer (44) having a first input coupled to an output of the first logic gate, and a second input coupled for receiving the first match signal; a second logic gate (48) having an input coupled to an output of the first logic gate, and an output coupled to a control input of the multiplexer; and 30 a first flipflop (46) having a data input coupled to an output of the multiplexer, a clock input coupled for receiving a clock signal, and an output for providing the first sequence match signal.

8. The CAM array of claim 7 wherein the first sequence matching block further includes a second flipflop (40) having a data input coupled for receiving the f irst match signal, a clock input coupled for receiving the clock signal, and an output coupled to the first input of the first logic gate and to the second input of the multiplexer.

9. A method of identifying data sequence matches, comprising the steps of:

comparing data stored in a plurality of CAM cells with an input data and asserting a first match signal upon detecting a match between first stored data and the input data; and asserting a first sequence match signal in response to asserting the first match signal and asserting a second sequence match signal representing a match between second stored data and the input data.

10. A CAM array substantially as hereinbefore described with reference to the accompanying drawings.

11. A method of identifying data sequence matches substantially as hereinbefore described with reference to the accompanying drawings.