GB2322526A

GB2322526A - Encoding and decoding data

Info

Publication number: GB2322526A
Application number: GB9703715A
Authority: GB
Inventors: Martin Robert Evans
Original assignee: Technology Partnership PLC
Current assignee: Technology Partnership PLC
Priority date: 1997-02-22
Filing date: 1997-02-22
Publication date: 1998-08-26
Also published as: GB9703715D0

Abstract

Algorithms for encoding and decoding Frame Check Sequences (FCS) currently perform a standard modulo-2 addition using a feedback shift register. The algorithm is equivalent to: clocking a stream of m bits through a n stage division register, where n½m; and combining input bits with bits emerging from said division register to give a bit combination used to modify said division register's state, which only on its initial state and the bit stream. The fast algorithm is implemented in a digital processor having a q-bit division register and a look-up table store. In operation, the division register is initialised to zero and the following steps are performed repeatedly, p times: - adding a next group of N input bits, modulo-2, to a least significant group of N bits in the division register, in a first adder; - using the result as an index to a look-up table parameter, stored in said look-up table store; - shifting the contents of said division register N bits to the right and adding, modulo-2, the indexed look-up table parameter to the content of the division register, in a second adder. After completion of p steps, the FCS is derived from said division register contents. Application is to GSM mobile telephone systems.

Description

Improvements in. or Relating to Encoding and Decoding Data The present invention relates to data decoders, data encoders, data transmission systems and methods of decoding data, having particular application to data transmission over GSM mobile telephony systems.

Algorithms for encoding and decoding Frame Check Sequences (FCS) for Radio Link Protocol (RLP) frames have been defined in the GSM Standard 04.22, published by ETSI (European Telecommunications Standards Institute).

The data to be transmitted is encoded in the form of a cyclic error detecting code.

Such algorithms may be implemented on ASICs (Application Specific Integrated Circuit), using VHDL (VLSI Hardware Description Language), for incorporation into a Data Terminal Adaptor (DTA).

The algorithm currently used for FCS with RLP and implemented in VHDL for the DTA, performs a standard modulo-2 addition using a feedback shift register. This register is clocked 240 times as the input data stream is fed in to generate the checksum. The realisation of this implementation within an ASIC, or an FPGA (Field Programmable Gate Array) is compact and sufficiently fast and is, therefore, the most appropriate way of providing this function if an ASIC, or FPGA, is to be used. However, if a faster algorithm were available, suitable for software implementation within a processor, the ASIC, or FPGA, could be removed from the DTA, yielding a significant cost saving. In addition, other products, entirely software based, could contain a fast implementation of the algorithm, making it possible to provide data services where previously lack of performance would have meant that this was not feasible.

It is an object of the present invention to provide a fast algorithm for calculating a FCS from a cyclically coded bit stream, a method of implementing the algorithm using a digital processor and look-up table, a decoder operating said method, transceivers containing said decoders and a digital transmission system including said transceivers.

According to a first aspect of the present invention, there is provided an encoder, having a bit stream input and a digital processor, for encoding data in a cyclic code by adding an FCS to said data, said FCS being determined by means of an FCS algorithm, which is equivalent to: - clocking a bit stream of m bits through a n stage division register, where n < < m; - combining input bits with bits emerging from said division register to give a bit combination; and - using said bit combination to modify said division register's state; said division register's state depending only on its initial state and said bit stream, characterised in that said digital processor has a q-bit division register and look-up table storage means, and in that in operation, said division register is initialised to zero and the following steps are performed repeatedly, p times: - adding a next group of N input bits, modulo-2, to a least significant group of N bits in the division register, in a first adder means, to yield a result; - using the result as an index to a iook-up table parameter, stored in said look-up table storage means; - shifting the contents of said division register N bits to the right and adding, modulo-2, the indexed look-up table parameter to the content of the division register, in a second adder means; and, after completion of p steps, deriving said FCS from said division register contents.

Preferably, p = mlN, and said division register contents, after completion of p steps, is said FCS.

Said look-up table storage means may be a read only memory.

Alternatively, said look-up table storage means may be a logic array.

Alternatively, said look-up table storage means may be a random access memory.

Said look-up table may be generated at compile-time as a read only table.

Alternatively, said look-up table may be generated at run-time when said digital processor means starts-up.

Said FCS algorithm may be the FCS algorithm defined in GSM Standard 04.22 for RLP frames.

The value of m may be equal to 216.

Said encoder may be adapted for use with a GSM mobile telephone system.

The values of N, q and p may be 8, 24 and 27 respectively.

Said look-up table may be generated by calculating the final value of the division register for all possible values of an input value, said input value being a modulo-2 sum of the input bits and the first N bits in said register.

Said look-up table may be generated by: - for each input value, setting a division register in said digital processor to zero and adding the rightmost bit of said input value, modulo-2, to the rightmost bit of said division register to yield a sum; - if said sum is zero adding a generator polynomial to said division register; - shifting the division register one place to the right, a "1" being shifted in if said sum is not zero; - shifting said input bit stream one place to the right; and - continuing the process until all input bits have been consumed.

According to a second aspect of the present invention, there is provided a decoder, having a bit stream input for frames of m-bits followed by N FCS-bits and a digital processor, for decoding data encoded in a cyclic code by using an FCS algorithm, which is equivalent to: - clocking a bit stream of m bits through a n-stage division register, where n < < m; - combining input bits with bits emerging from said division register to give a bit combination; and - using said bit combination to modify said division register's state; said division register's state depending only on its initial state and said bit stream, characterised in that said digital processor encodes said m-bits to derive a local value for an FCS therefrom using an encoder as set forth in any preceding paragraph, in that said local value of said FCS is compared with said N-FCS bits in a comparator means, and in that an error signal is generated if a difference between said N-FCS bits and said local value of said FCS is detected.

According to a third aspect of the present invention, there is provided a data transmission system, characterised in that said data transmission system includes a data transmitter having an encoder, as set forth in any preceding paragraph, and a data receiver having a decoder as set forth above.

Said data transmission system may be compliant with the GSM standards, and said data transmission system may include a plurality of mobile transceivers each having a decoder as set forth above and an encoder, as set forth in any preceding paragraph.

Said data transmission system may include at least one fixed transceiver having an encoder, for encoding data, as claimed in any preceding paragraph and a decoder as set forth above.

According to a fourth aspect of the present invention, there is claimed a mobile GSM transceiver, characterised in that said mobile transceiver has a decoder, as set forth above and an encoder, as set forth in any preceding paragraph.

Said encoder and decoder may share a single digital processor and a single look-up table.

According to a fifth aspect of the present invention, there is provided a GSM base station having a fixed transceiver, characterised in that said fixed transceiver has a decoder, as hereinbefore defined and an encoder, set forth in any preceding paragraph.

According to a sixth aspect of the present invention, there is provided a method of decoding data encoded in a cyclic code by using an FCS algorithm, which is equivalent to: - clocking a bit stream of m-bits through a n-stage division register, where n < < m; - combining input bits with bits emerging from said division register to give a bit combination; and - using said bit combination to modify said division register's state; said division register's state depending only on its initial state and said bit stream, characterised by initialising a q-bit division register to zero and performing the following steps repeatedly, p times: - adding a next group of N input bits, modulo-2, to a least significant group of N bits in said q-bit division register, to yield a result; - using the result as an index to a look-up table to an indexed look up table parameter; and - shifting the contents of said division register N bits to the right and adding, modulo-2, the indexed look-up table parameter to the content of the division register; and, after completion of said p steps, deriving said FCS from said division registers contents.

Preferably, p = m/N, and said division register contents, after completion of p steps, is said FCS.

Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 illustrates an implementation of a slow algorithm for calculating an FCS, according to GSM standard 04.22.

Figure 2 illustrates one step in the slow algorithm illustrated in Figure 1.

Figure 3 illustrates the combination of four steps in the slow algorithm illustrated in Figure 1.

Figure 5 illustrates, in diagrammatic form, apparatus for implementing the fast algorithm of the present invention.

To understand the present invention, it is necessary to first explain the operation of the slow algorithm, specified in GSM standard 04.22, and its implementation using a shift register.

The FCS algorithm is completely deterministic, based on a modulo-2 division process within a 24-bit division register. Figure 1 shows an outline of the implementation of the "slow" algorithm. An input bit stream, comprising frames of 216 bits, is input to an exclusive OR gate 1, which has an output bit stream as its second input. The output from exclusive OR gate 1, is passed via invertor 2, to an input of a division register having n stages, 5, each stage acting as a one bit delay.

The output of exclusive OR gate 1 is also passed to an AND gate whose second input is a "mode" condition. The mode condition is set during the period when an FCS is being calculated and is un-set when an FCS is being read from the division register. The bits gl to 923 of a generator polynomial are bit-wise multiplied with the input bit stream by means of AND gates 3, and the result is bit-wise added to the contents of the division register by exclusive OR gates 4.

The input data stream is 216 bits long and is clocked through the register, the contents of the register at the end of this process providing the checksum, FCS. In principle, the calculation could be done using a single look-up table, as any given 216-bit input data stream maps onto a 24-bit result. Unfortunately, the look-up table would require a 216-bit address, rendering this approach totally impossible to implement in practice. However, the state of the division register, at all times, depends only on its initial state and the values of the input bits subsequently fed into it. Therefore, if a group of input bits is taken together with the current state of the division register, it would be possible to use a look-up table to determine the new state of the division register. By repeating this princess, an appropriate number of times (depending on the size of the input bit groups), the FCS can be calculated.

Consider a look-up table with two inputs: first, the group of input bits, and second, the current state of the division register. The output of the look-up table would then be the new state of the division register. Unfortunately, a very large table is still required; the state of the register requires 24 bits and so the number of address bits would be 24 plus the size of the group of input bits. Even for the degenerate case of input bits grouped in ones, this requires a look-up table with 225 locations, each of 24 bits (96 Mbyte).

Fortunately, a dramatic reduction in size can be made by taking note of the fact that it is only necessary to know the states of the first N bits in the division register, where N is the size of the input groups. This is because the division process combines the input bits with the bits emerging from the division register as they are shifted out to determine how to modify the register. None of the contents of the register beyond the first N bits can have any influence on the result. The contents of the table can be made the value to be added, modulo-2, to the initial value of the register to form the final value, so it is no longer necessary to make the entire initial contents of the register one of the input values.

This look-up table requires only 2N address bits. At this stage, a manageable size for the look-up table and a realistic implementation have been attained.

Further consideration of the workings of the algorithm allows a further dramatic reduction in the look-up table size to be made. Figure 2 illustrates one step in the "slow" algorithm.

Bit i0 of the input stream is added, modulo-2, to bit ro of the division register. Depending upon the value of the sum of these bits, one of two possible values for 90...923, the generator polynomial, is added to the register after it has been shifted one place right. The result becomes the new value of the register.

For the next step, the next input bit, il, will be compared with r'0, which was formed by adding rl to the appropriate value of g0. At each step the new value of the register will depend on the next input bit and the sum of all the previous additions. Figure 3 shows four steps brought together.

The first of the four steps adds i0 to rO and the value of the sum, S0, determines which of the two values for 90...923 is added. The next step adds il to the sum of r1 and g0 to form SI, which determines the next value to be added, and so on. As the order of the additions doesn't matter (addition is associative) i0...i3 can be added to rO...r3 before performing the four steps to generate the answer. The four steps can then be performed as a single lookup table operation which can be given the sum i0...i3 and rO...r3 as an input and generates the difference to the initial value of the division register. In the general case, the lookup table now only requires N input bits and 24 output bits, where N is the group size of the input bits (which is 4 in the above example).

The gain in speed provided by this fast algorithm will depend on the group size, N, of the input bits. The greater the value of N, the fewer steps are required to generate the FCS but the larger the look-up table will have to be. This represents a time/space trade-off; the more memory that can be devoted to the lookup table, the fewer steps must be performed by the algorithm and, generally speaking, the quicker the answer is obtained. However, there are other factors which may influence the choice of N, including the packing of the input data and the relative efficiency of the processor in handling different sized groups of bits.

For instance, it may be much more efficient to handle the data in 8-bit units than in 12-bit units as the advantage of the smaller number of steps would be offset by the additional complexity required within each step. There is also a limited choice of values for N, which must also be taken into account. The number of steps needed in the "slow" algorithm is 216 and the value of N should be chosen so that it is a factor of this number. The "slow" algorithm has N equal to one and performs 216 steps. Other possible values are given in the table below.

N 2 3 4 6 8 9 12 18 24 etc.

Steps 108 72 54 36 27 24 18 12 9 etc.

Values for N above 24 are not given as the look-up table for these values would be rather large.

For a given value of N it is possible to write algorithms to generate the corresponding lookup table and to use the table to generate an FCS from any given input stream. A value of N equal to 8, leads to a lookup table size of 256x24 bits.

The algorithm for calculating the FCS from the lookup table is as follows.

First a 24-bit division register must be initialised to zero and then the same step repeated 27 times. This step takes the next input byte and adds it, modulo-2, to the least significant byte of the division register. The result is used as an index into the lookup table. The division register is shifted right by one bit and the contents of the address location of the lookup table are added to it, modulo-2.

When all 27 steps have been completed the division register contains the FCS.

The lookup table is generated by calculating the final value of the division register for all possible values of the input value, this input value being the modulo2 sum of the input bits and the first N bits of the register. For N equal to 8, there are 256 (28) possible input values and each value requires the performance of 8 additions to generate the table entry. For each input value, a division register is set to zero and then the rightmost bit of the input value added modulo-2 to the rightmost bit of the register. If the sum is zero, the generator polynomial is added to the register. The register is then shifted right one place, a one being shifted in if the generator polynomial was not added to the register. The input bit stream is then shifted one place to the right and the loop repeats until all the input bits have been consumed.

The lookup table may be generated at compile time as a read-only table or it may be calculated at run-time when the processor which computes the FCS starts up.

A C implementation of the table generation and FCS calculation is shown in the listing below, based on a group size, N, of 8.

CODE LISTINGS /**************************************************************************/ /* */ /* Fast version of ENCODE imlementted using a look-up */ /* table technique */ /* */ /**************************************************************************/ &num;define BYTE~SIZE 8 &num;define FCS~SIZE 24 &num;define GENERATOR Ox5bObbbL static Int32 Table[1 < < BYTE SIZE]; It Look-up table */ static void CreateLookupTable(void) It /* Creates the look-up table used by the fast It encoder. Takes each possible input byte and /* runs the standard algorithm loop 8 times to It create the table entry for that input byte. */ /* */ lnt16 I; /* The input byte Int16 j; /* Bit counter for the byte */ Int16 Current; /* The current input lnt32 Divider; It The division register for( I = 0; I < (1 < < BYTE~SIZE); I++) { Divider = OL; It Initialise the register Current = 1; It Get the next input byte */ for (j = 0; j < BYTE~SIZE; j++) Divider A ((Current & 1) == (lnt16) (Divider & 1L))? GENERATOR:(1L < < FCS~SIZE); Divider > > = 1; Current > > = 1; Table[i] = Divider; /* Update the table */ static Int32 FastEncode (Int8 *Data) It /* Calculates the FCS using the fast algorithm */ /* supported by a look-up table */ /* */ Int16 I; /* Counter */ lnt8 Input; I Next input byte Int32 Divider; /* The encoding divider /* Initialise */ Divider = OL; /* Preset divider for(I = 0; I < (DATA~SIZE/BYTE~SIZE); I++) Input = (*Data++) A (Int8)(Divider & BYTE~MASK); Divider = (Divider > > > > BYTE~SIZE) A Table[lnput]; return(Divider); A further explanation of the operation of the present invention will now be given, with reference to Figure 4. The input data, in blocks of 8 bits, is bit-wise combined in exclusive OR gates with the output of the 8 right most bits in the division register, to generate an 8 bit index for the look-up table, held in RAM, or ROM, or implemented as a logic tree. The 24 bit look up table parameter is bitwise combined with 24 bits, 8 through to 31, in the division register and input into the division register. The contents of the division register are then shifted 8 bits to the right and the process is repeated 27 times. The final content of the division register is the FCS.

In the general case, blocks of N-bits are used and the process is repeated p times. If the number of bits in a frame is m, then N must, for the simplest realisation of the present invention, be a factor of m and p = mlN. However, it is possible to use any value N. If N is not a factor of m, then p is the integer part of mlN and the content of the division register will require further manipulation after the completion of p process steps, in order to derive the FCS.

Where the FCS is to be used for error detection only, the same process can be used for encoding and decoding data. Since the FCS is added to the bits in a data stream before transmission, it is only necessary, when decoding data to re-encode the data in the bit frame to derive a local FCS and to compare the local FCS with the transmitted FSC. If the two FCSs are not identical, there is an error and the bit frame must be re-transmitted. In the present example, where a bit frame contains 216 bits, and the FCS contains 24 bits, a received bit frame will contain a total of 240 bits. To decode the data, the 24 bits of the FCS are stripped out from the bit frame and a local FCS is derived by re-encoding.

The present invention has particular application to GSM transceivers, which may be used in either mobile GSM handsets, or fixed base stations. Of course, the receiver and transmitter parts of a transceiver can share the same digital processor for encoding and share a common look-up table.

Claims

CLAIMS 1. An encoder, having a bit stream input and a digital processor, for encoding data in a cyclic code by adding an FCS to said data, said FCS being determined by means of an FCS algorithm, which is equivalent to: - clocking a bit stream of m bits through a n stage division register, where n < < m; - combining input bits with bits emerging from said division register to give a bit combination; and - using said bit combination to modify said division register's state; said division register's state depending only on its initial state and said bit stream, characterised in that said digital processor has a q-bit division register and look-up table storage means, and in that in operation, said division register is initialised to zero and the following steps are performed repeatedly, p times: - adding a next group of N input bits, modulo-2, to a least significant group of N bits in the division register, in a first adder means, to yield a result; - using the result as an index to a look-up table parameter, stored in said look-up table storage means; - shifting the contents of said division register N bits to the right and adding, modulo-2, the indexed look-up table parameter to the content of the division register, in a second adder means; and, after completion of p steps, deriving said FCS from said division register contents.
2. An encoder, as claimed in claim 1, characterised in that p = mlN, and in that said division register contents, after completion of p, steps is said FCS.
3. An encoder, as claimed in claim 1, or claim 2, characterised in that said look-up table storage means is a read only memory.
4. An encoder, as claimed in claim 1, or claim 2, characterised in that said look-up table storage means is a logic array.
5. An encoder, as claimed in claim 1, or claim 2, characterised in that said look-up table storage means is a random access memory.
6. An encoder, as claimed in claim 5, characterised in that said look-up table is generated at compile-time as a read only table.
7. An encoder, as claimed in claim 5, characterised in that said look-up table is generated at run-time when said digital processor means starts-up.
8. An encoder, as claimed in any previous claim, characterised in that said FCS algorithm is the FCS algorithm defined in GSM Standard 04.22 for RLP frames.
9. An encoder, as claimed in any previous claim, characterised in that m = 216.
10. An encoder, as claimed in claim 9, characterised in that said encoder is adapted for use with a GSM mobile telephone system.
11. An encoder, as claimed in any previous claim, characterised in that N is 8, q = 24 and p = 27.
12. An encoder, as claimed in any previous claim, characterised in that said look-up table is generated by calculating the final value of the division register for all possible values of an input value, said input value being a modulo-2 sum of the input bits and the first N bits in said register.
13. An encoder, as claimed in claim 12, characterised in that: - for each input value, a division register in said digital processor is set to zero and the rightmost bit of said input value is added modulo-2 to the rightmost bit of said division register to yield a sum; - if said sum is zero a generator polynomial is added to said division register; - the division register is shifted one place to the right, a "1" being shifted in, if said sum is not zero; - said input bit stream is shifted one place to the right; and - the process is continued until all input bits have been consumed.
14. A decoder, having a bit stream input for frames of m-bits followed by N FCS-bits and a digital processor, for decoding data encoded in a cyclic code by using an FCS algorithm, which is equivalent to: - clocking a bit stream of m bits through a n-stage division register, where n < < m; - combining input bits with bits emerging from said division register to give a bit combination; and - using said bit combination to modify said division register's state; said division register's state depending only on its initial state and said bit stream, characterised in that said digital processor encodes said m-bits to derive a local value for an FCS therefrom using an encoder as claimed in any of claims 1 to 13, in that said local value of said FCS is compared with said N-FCS bits in a comparator means, and in that an error signal is generated if a difference between said N-FCS bits and said local value of said FCS is detected.
15. A data transmission system, characterised in that said data transmission system indudes a data transmitter having an encoder, as claimed in any of claims 1 to 13, and a data receiver having a decoder as claimed in claim 14.
16. A data transmission system, as claimed in claim 15, characterised in that said data transmission system is compliant with the GSM standards, and in that said data transmission system includes a plurality of mobile transceivers each having a decoder as claimed in claim 14, and an encoder, as claimed in any of claims 1 to 13.
17. A data transmission system, as claimed in claim 16, characterised in that said data transmission system includes at least one fixed transceiver having an encoder, for encoding data, as claimed in any of claims 1 to 13 and a decoder as claimed in claim 14.
18. A mobile GSM transceiver, characterised in that said mobile transceiver has a decoder, as claimed in claim 14 and an encoder, as claimed in any of claims 1 to 13.
19. A GSM base station having a fixed transceiver, characterised in that said fixed transceiver has a decoder, as claimed in claim 14 and an encoder, as claimed in any of claims 1 to 13.
20. A data transmission system, or mobile GSM transceiver, or base station, as claimed in any of claims 15 to 19, characterised in that said encoder and decoder share a single digital processor and a single look-up table.
21. A method of decoding data encoded in a cyclic code by using an FCS algorithm, which is equivalent to: - clocking a bit stream of m-bits through a n-stage division register, where n < < m; - combining input bits with bits emerging from said division register to give a bit combination; and - using said bit combination to modify said division register's state; said division register's state depending only on its initial state and said bit stream, characterised by initialising a q-bit division register to zero and performing the following steps repeatedly, p times: - adding a next group of N input bits, modulo-2, to a least significant group of N bits in said q-bit division register, to yield a result; - using the result as an index to a look-up table to an indexed look up table parameter; and - shifting the contents of said division register N bits to the right and adding, modulo-2, the indexed look-up table parameter to the content of the division register; and, after completion of said p steps, deriving said FCS from said division registers contents.
22. A method, as claimed in claim 21, characterised by p = m/N, and by said division register contents, after completion of p steps, being said FCS.
23.. A method, as claimed in either claim 21, or claim 22, characterised by generating said look-up table at compile-time as a read only table.
24. A method, as claimed in either claim 21, or claim 22, characterised by generating said look-up table at run-time.
25. A method, as claimed in any of claims 21 to 24, characterised by said FCS algorithm being equivalent to the canonical form of the FCS algorithm defined in GSM Standard 04.22 for RLP.
26. A method as claimed in any of claims 20 to 25, characterised by m = 16.
27. A method, as claimed in claim 20 to 26, characterised in that said method is employed in a GSM mobile telephone system.
28. A method, as claimed in any of claims 21 to 27, characterised by N = 8, q = 24 and p = 27.
29. A method, as claimed in any of claims 21 to 28, characterised by generating said look-up table by calculating the final value of the division register for all possible values of an input value, said input value being a modulo-2 sum of the input bits and the first N bits in said register.
30. A method, as claimed in claim 29, characterised by setting a division register to zero, and: - for each input value, adding the rightmost bit of said input value, modulo-2, to the rightmost bit of said division register to yield a sum; - if said sum is zero, adding a generator polynomial to said division register; - shifting said division register one place to the right, a "1" being shifted in if said sum was not zero; - shifting said input bit stream one place to the right; and - continuing the process until all input bits have been consumed.
31. An encoder, substantially as hereinbefore described with reference to Figure 4 of the accompanying drawings.
32. A data transmission system, including a data receiver having a encoder, substantially as hereinbefore described with reference to Figure 4 of the accompanying drawings.
33. A mobile GSM transceiver having a encoder, substantially as hereinbefore described with reference to Figure 4 of the accompanying drawings.
34 A method, substantially as hereinbefore described with reference to Figure 4 of the accompanying drawings.
35. A decoder, substantially as hereinbefore described with reference to Figure 4 of the accompanying drawings.
36. A GSM base station, substantially as hereinbefore described with reference to Figure 4 of the accompanying drawings.