GB2309803A - Processing cycle control in data processing apparatus - Google Patents
Processing cycle control in data processing apparatus Download PDFInfo
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- GB2309803A GB2309803A GB9602024A GB9602024A GB2309803A GB 2309803 A GB2309803 A GB 2309803A GB 9602024 A GB9602024 A GB 9602024A GB 9602024 A GB9602024 A GB 9602024A GB 2309803 A GB2309803 A GB 2309803A
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- 238000010977 unit operation Methods 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims description 9
- 230000004044 response Effects 0.000 claims description 8
- 230000001419 dependent effect Effects 0.000 claims description 7
- 230000008569 process Effects 0.000 description 2
- 101100238304 Mus musculus Morc1 gene Proteins 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000001343 mnemonic effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
- G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
Abstract
A data processing system (2, Fig 1) utilises data processing instruction words having a first field 31 specifying one of a plurality of arithmetic logic unit operations to be performed and a second field 28 specifying one of a plurality of shift operations 40 to be performed. The first and the second fields are independent. The instruction decoder (10) is responsive to both of these fields to vary the number of processing cycles allowed for each such instruction word in dependence upon the particular combination of the first field and the second field.
Description
PROCESSING CYCLE CONTROL IN DATA PROCESSING APPARATUS
This invention relates to the ficld of data processing. More particularly, this invention relates to the control of thc number of processing cycles allowed for execution of instructions within a data proccssing system.
It is known within data processing systems that different data processing instruction words take different numbers of processing cycles (clock cycles) to execute before a following instruction can be startcd. One instruction word may only require a very limited amount of processing to be performed by the system (e.g. a swap register data instruction), where anothcr instruction (c.g. a multiple load instruction) may take very many proccssing cycles to complete.
It is also known that within instructions of a single type, it is possible to execute some specific instructions morc rapidly than othcrs, e.g. a simple shift through a low number of bits directly specified by a constant within an instruction can be executed in fewer processing cycles than a complicated arithmetic shift through many bits where the number of shift bits is spccificd by a value retricvcd from a register.
Another trend within computing is the increascd number of bits within program instruction words. There has bccn a move from -bit or 16-bit instruction words to 32-bit or 64-bit instruction words. In order to cfficicntly use the instruction set space within such larger instructions, it has been proposcd in microprocessors such as the
ARM6 produced by Advanced RISC Machines Limited to include program instruction words having more than one field, each field specifying a particular type of arithmetic logic unit operation or shift operation. In this way, the coding density can be improved.This technique is particularly suitcd to reduced instruction set computing devices in which the alternative of utilising the increased instruction set bit space to provide increased number of more complex and specialised instructions is inappropriate.
An additional complication ariscs with program instruction words having more than one field, with each field specifying one of a type of instruction, in that the different types of instructions may both wish to utilise a single hardware resource within the processor, e.g. a shiftcr or an addcr. This increases the number of processing cycles that must be allowed for thcir program instruction word to execute in order that all conflicting requirements for hardware rcsourccs can be satisfied. This moves against the constant aim within data processing systems of achieving more rapid execution.
Viewed from one aspect, the present invention provides apparatus for processing data in response to a data processing instruction word having a first field specifying one of a plurality of arithmetic logic unit operations and a second field specifying one of a plurality of shift operations, said second field being independent of said first field, said apparatus comprlsillg:: an arithmetic logic unit for pcrforniing an arithmetic logic unit operation specified by said first field in a number of processing cycles dependent upon which of said plurality of arithmetic logic operations is specified by said first field;
a shifter for performing a shift operation specified by said sccond field in a number of processing cycles dcpcndent upon which of said plurality of shift operations is specified by said second ficld;; and
an instruction decoder for varying, in dependence upon both said first field and said second field, the number of proccssing cycles allowed for execution of said data processing instruction word before commencing execution of a next processing instruction word.
The invention recogniscs that within a data processing system in which data processing instruction words have ficlds that indcpendently specify an arithmetic logic unit operation and a shift operation, then evcn if those operations may share common hardware resources, it is neverthclcss possible to select the number of processing cycles allowed in dependence upon both of the ficlds. In this way, only the worst case scenarios of combinations of arithmetic logic unit operations and shift operations need be allowed a high number of processing cycles, whilst more common and simple combinations are permitted to use a lowcr number of processing cycles.
The above described technique could be utilised in circumstances in which the arithmetic logic operation and the shift operation were quite independent, but nevertheless certain combinations required a longer total time to operate than others.
However, the invention is particularly advantageous in cmbodiments in which for one or more combinations of arithmetic logic operation and shift operation said arithmetic logic unit and said shifter sequentially perform said arithmetic logic operation and said shift operation.
The sequential performing of the arithmetic logic operation and the shift operation makes each more sensitive to the time taken to complete the other when determining whether an increase in the total number of processing cycles required for that data processing instruction word needs to he madc.
The difference between shift operations that are slow compared to those that are fast may be considered as one in which said shift operation is one of:
a full shift operation with a shift amount equal to or greater than a predetermined level; and
a simple shift operation with a shift amount less than said predetermined level.
Shift Operations with a shift amount less than the predetermined level may be handled by their own bespoke shifter that is not shared with other operations. In this way, such small shifts may be handlcd more quickly. The shift operations that are selected to the handled by thcir own bespoke shiftcr are chosen to be those that are relatively easily to decode and implement whilst being relatively common within rypical data processing opcration.
The arithmetic logic unit operations can take many different forms. One way of considering these operations to be divided is that in which an arithmetic logic unit operation is one of:
a logical operation upon one or more operands; and
an arithmetic operation upon one or more operands.
Typically, an arithmetic operation is considerably more complex than a logical operation and takes longer to process (c.g. through the nced to handle carries along a chain of bit values).
The above described division between the types of arithmetic logic unit operation and shift operation may be effectively exploited in embodiments in which in response to a data processing instruction including a full shift operation and a logical operation or a simple shift operation and arithmetic operation, said instruction decoder allows X processing cycles before commencing execution of a next processing instruction word; and
in response to a data processing instruction including a full shift operation and an arithmetic, said instruction decoder allows Y proccssing cycles before commencing execution of a next processing instruction word. Y being greater than X.
It will be appreciated that the valucs of X and Y could take any different level providing that Y is greater than X. Howcvcr, in a typical highly optimiscd processing apparatus (e.g. a RISC processor) then Y = 2 and X = 1.
Viewed from anothcr aspcct the present invention provides a method of processing data in response to a data processing instruction word having a first field specifying one of a plurality of arithmetic logic unit operations and a second field specifying one of a plurality of shift opcrations, said second field being independent of said first field, said method comprising the steps of:
performing an arithmetic logic unit operation spccificd by said first field in a number of processing cycles dependent upon which of said plurality of arithmetic logic operations is specified by said first field::
performing a shift operation specified by said second field in a number of processing cycles dependent upon which of said plurality of shift operations is specified by said second field; and
varying, in dependence upon borh said first field and said second field, the number of processing cycles allowed for execution of said data processing instruction word before commencing execution of a next processing instruction word.
An embodiment of the invention will now he described, by way of example only, with reference to the accompanying drawings in which:
Fig. 1 illustrates the functional elements within a microprocessor;
Fig. 2 illustrates the form and content of a data processing instruction word with independent fields specifying an arithmetic logic unit operation and a shift operation; and
Fig. 3 illustrates the decoding of the instruction of Fig. 2 to determine the number of processing cycles to be allowed for the data processing instruction word to complete.
Fig. 1 illustrates a microprocessor circuit 2. The microprocessor circuit 2 includes an address register 4 for storing an address currently being asserted upon an address bus (not shown). An address inerementer circuit 6 scrvcs to perform a high speed increment upon the address storcd within the address register 4, as is desirable for high speed sequential access to memory locutions and the likc. An instruction pipeline and read data register unit X serves to store data processing instruction words recovered from memory to be applied to the microprocessor circuit 2.The data processing instruction word at the top of the instruction pipeline 8 is applied to an instruction decoder and control logic unit I() where it is at least partially decoded to an extent that the instruction decoder and control logic unit 8 may appropriately drive the other elements within the microprl)cessor circuit 2 to full! process that data processing instruction word. A register bank 12 is provided for storing data words to be manipulated. Spccific processing units within the microproccssor circuit 2 that are optimised for given functions include a multiplicr 14. a barrel shifter 16 and an arithmetic logic unit 18.These functional units perform the bulk of the processing manipulation needed within the microproccss.)r circuit 2. A debug circuit 2() provides support for hardware debugging of a system incorporating the mieroprocessor circuit 2 during development. A write data register bank 22 serves to buffer data values to be written out from the microproccssor circuit 2.
Fig. 2 illustrates a data processing instruction word having a first field 32 specifying one of a plurality of arithmetic logic unit operations and a second field 28 specifying one of a plurality of shift operations. This example instruction is taken from the instruction set of the ARM6 processer produced by Advanced RISC
Machines Limited. An example of the operation of the present invention will be described in terms of a modification to the manncr in which this data processing instruction word is dccoded and applied.
The data processing instruction word includcs a condition field 24 as bits 31 to 28. This condition field 24 allows for conditional execution of the whole data processing instruction word in dependence upon status flags within the microprocessor circuit 2 matching or not matching conditions specified within the condition field 24.
The bits 27 and 26 are always both zeros for this particular data processing instruction word.
The bit 25 is termed the I bit that spccifics the manner in which the least significant 12 bits (i.e. bits 11 to ()) of the data processing instruction word are interpreted, i.e. whether an immediate value is used or a value stored within a register.
The first field 32 (bits 24 | to 21) spccifics an operation code (OpCode) that selects one of a plurality of arithmetic logic unit operations to be performed by the arithmetic logic unit 18 in combination with other elements of the microprocessor circuit 2. There are 16 possible arithmetic logic unit operations and there form is shown in Figure 2. Of these 16 arithmetic logic unit operations, 8 are arithmetic operations (SUB, RSB, ADD. ADC. SBC, RSC. CMP and CMN) and 8 are logic operations (AND, EOR TST. TEQ, ORR, MOV. BIC and MVN).
Bit 2(), termed the S bit 33 spccifics whether the condition flags to which the conditional field 24 is responsive will be altered by the present data processing instruction word.
The next 4 bits 34 (bits 19 to 1() specify the number of the register within the register bank 12 that will provide the first operand of this data processing instruction word.
The next four bits 36 (bits 15 to 12) specify the register within the register bank 12 where the rcsult of the data processing instruction word will be written.
The final 12 bits 28 (bits 11 to (ì) specify the shift operation that is to be performed. As previously mentioncd, the manncr in which the least significant 12 bits 78 are interpreted is dependent upon the I bit 3(). If I = (), then the least significant 4 bits 38 (bits 3 to 0) specify the register within the register bank 12 from which a value is to be taken and shiftcd to form the second opcrand. The most significant 8 bits 4() (bits 11 to 4) then specify the nature and amount of the shift to be performed.
The shift may be a left logical shift, a right logical shift, an arithmetic right shift or a right rotate shift depending upon the bits within the field 4(). The field 40 also either points to a register within the register bank 12 holding the value of the shift amount to be performed or directly spccifics this shift amount as an immediate value.
When I = 1, then the least significant 8 bits (bits 7 to ()) specify an immediate value upon which a shift is to be performed. This shift is specified by the 4 remaining bits (bits 11 to 8).
In the context of this embodiment, left logical shifts by eithcr (), 1, 2 or 3 bit positions are treated as simple shifts that may he rapidly performed by a special purpose shifter. All rcmaining shifts are treated as full shifts that take longer to perform.
Fig. 3 illustrates the manner in which the instruction decoder and control logic 1() decodes the first field 32 spccifying the arithmetic logic unit operation and the second field 28 specifying the shift operation. The relevant bits from these ficlds are fed to respective combinational logic blocks 42, 44 that produce outputs indicating whether a logic operation or an arithmetic operation is specified and whether a simple shift or a full shift is specified.These two outputs are fcd to an AND gate 46 that produces as its output a value of 1 if both a full shift and an arithmetic operation are specified With an" other combination, the output of the AND gate 46 is a 0. The output of the AND gate 46 is utilised to control the advance of instructions along the instruction pipeline X, i.e. to control the amount of time allowed for the present instruction to execute before the next instruction is applied to the instruction decode and control logic 10.
Assembler Operation ALU Action Logical or Number of Mnemonic Code Arithmetic Processing Cycles Allowed Full Simple AND 0000 Opl AND Op2 L 1 1 EOR 0001 Op1 EOR Op2 L 1 1 SUB ()()1() Op] - Op2 A 2 1 RSB ()()11 Op2 - Op] A 2 1 ADD ()1()() Opl + Op2 A 2 1 ADC ()1()1 Op] + Op2 + C A 2 1 SBC 0110 Op1 - Op2 + C - 1 A 2 1 RSC 0111 Op2 - Op1 + C - 1 A 2 1 TST 1000 set Cond on Op1 AND Op2 L 1 1 TEQ 1001 set Cond on Op1 EOR Op2 L 1 1 CMP 1010 set Cond on Op1 - Op2 A 2 1 CMN 1()11 set Cond on Opl + Op2 A 2 1 ORR 1100 Op1 OR Op2 L 1 1 MOV 1101 Op2 L 1 1 BIC 1110 Op1 AND NOT Op2 L 1 1 MVN 1111 NOT Op2 L 1 1
Table l Table 1 (above) illustrates the various combinations of the arithmetic operations and the shift operations that produce respective cycle counts. In a highly optimised microprocessor circuit 2, such as a rcduccd instruction set computing circuit, nearly all of the instructions are able to execute within a single cycle. Only the worst
case situation in which an arithmetic operation and a full shift are simultaneously
specified must allow the microprocessor circuit 2 two clock cycles to complete.
Claims (9)
1. Apparatus for processing data in response to a data processing instruction word having a first field specifying one of a pluralit) of arithmetic logic unit operations and a second field specifying one of a pluralit) of shift operations. said second field being independent of said first field, said apparatus comprising::
an arithmetic logic unit for pcrforming an arithmetic logic unit operation specified by said first field in a number of proccssing cycles dependent upon which of said plurality of arithmetic logic operations is specified hv said first field;
a shifter for performing a shift operation specified by said second field in a number of processing cycles dependent upon which of said pluralit' of shift operations is specified by said second field: and
an instruction decoder for Varying. in dependence upon froth said first field and said second field, the number of processing cycles allowed for execution of said data processing instruction word before commencing execution of a next processing instruction word.
2. Apparatus for processing total as claimed in claim 1. wherein for one or more combinations of arithmetic logic operation and shift operation said arithmetic logic unit and said shifter sequentially perform said arithmetic logic operation and said shift operation.
3. Apparatus as claimed in any one of claims I and 2, wherein said shift operation is one of:
à full shift operation with a shift amount equal to or greater than a predetermined level; and
a simple shift operation with a shift amount less than said predetermined level.
4. Apparatus as claimed in any one of claims 1 2 and 3, wherein said arithmetic logic unit operation is one of:
a logical operation upon one or more operands: and an arithmetic operation upon one or more operands.
Apparatus as claimcd in claims 3 and A, wherein in response to a data processing instructioll including a full shift operation and a logical operation or a simple shift operation and arithmetic operation, said instruction decoder allows X processing cycles be for commencing execution of a next processing instruction word; and
in response to a data processing instruction including a full shift operation and an arithmetic, said instruction decoder allows Y processing cyclcs before commencing execution of a next processing instruction word Y bering greater than X.
Apparatus as claimed in claim , wherein Y = 2 and X = 1.
7. A method of proccssing data in response to a data processing instruction word having a first field specifying one of a plurality of arithmetic logic unit operations and a second field specifying one of a plurality of shift operations, said second field being independent of said first field, said method comprising the stcps of:
performing an arithmetic logic unit opcration specified by said first field in a number of processing cycles dcpcndcnr upon which of said plurality of arithmetic logic operations is specified by said first field: :
performing a shift operation specified by said second field in a number of processing cycles dependent upon which of said plurality of shift operations is specified by said second field; and
varying, in dependence upon both said first field and said second field, the number of processing cycles allowed for execution of said data processing instruction word before commencing execution of a next processing instruction word.
Apparatus for processing data substantially as hereinbefore described with reference to the accompanying drawings.
9. A method of processing data substantially as hereinbefore described with reference to the accompanying drawings.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9602024A GB2309803B (en) | 1996-02-01 | 1996-02-01 | Processing cycle control in a data processing apparatus |
| JP01830897A JP3619343B2 (en) | 1996-02-01 | 1997-01-31 | Data processing apparatus and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9602024A GB2309803B (en) | 1996-02-01 | 1996-02-01 | Processing cycle control in a data processing apparatus |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9602024D0 GB9602024D0 (en) | 1996-04-03 |
| GB2309803A true GB2309803A (en) | 1997-08-06 |
| GB2309803B GB2309803B (en) | 2000-01-26 |
Family
ID=10787933
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9602024A Expired - Fee Related GB2309803B (en) | 1996-02-01 | 1996-02-01 | Processing cycle control in a data processing apparatus |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP3619343B2 (en) |
| GB (1) | GB2309803B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000070446A2 (en) * | 1999-05-13 | 2000-11-23 | Arc International U.S. Holdings Inc. | Method and apparatus for loose register encoding within a pipelined processor |
| US8386972B2 (en) | 1998-10-14 | 2013-02-26 | Synopsys, Inc. | Method and apparatus for managing the configuration and functionality of a semiconductor design |
| US9690630B2 (en) | 2006-12-01 | 2017-06-27 | Synopsys, Inc. | Hardware accelerator test harness generation |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001069411A2 (en) | 2000-03-10 | 2001-09-20 | Arc International Plc | Memory interface and method of interfacing between functional entities |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0048971A1 (en) * | 1980-09-30 | 1982-04-07 | Computer Gesellschaft Konstanz Mbh | Circuit for executing microinstructions with different execution times |
-
1996
- 1996-02-01 GB GB9602024A patent/GB2309803B/en not_active Expired - Fee Related
-
1997
- 1997-01-31 JP JP01830897A patent/JP3619343B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0048971A1 (en) * | 1980-09-30 | 1982-04-07 | Computer Gesellschaft Konstanz Mbh | Circuit for executing microinstructions with different execution times |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8386972B2 (en) | 1998-10-14 | 2013-02-26 | Synopsys, Inc. | Method and apparatus for managing the configuration and functionality of a semiconductor design |
| WO2000070446A2 (en) * | 1999-05-13 | 2000-11-23 | Arc International U.S. Holdings Inc. | Method and apparatus for loose register encoding within a pipelined processor |
| WO2000070446A3 (en) * | 1999-05-13 | 2002-02-07 | Arc Internat U S Holdings Inc | Method and apparatus for loose register encoding within a pipelined processor |
| US9690630B2 (en) | 2006-12-01 | 2017-06-27 | Synopsys, Inc. | Hardware accelerator test harness generation |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09223009A (en) | 1997-08-26 |
| JP3619343B2 (en) | 2005-02-09 |
| GB2309803B (en) | 2000-01-26 |
| GB9602024D0 (en) | 1996-04-03 |
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| Date | Code | Title | Description |
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| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20140201 |