GB2299188A - Communicating between two microprocessors - Google Patents
Communicating between two microprocessors Download PDFInfo
- Publication number
- GB2299188A GB2299188A GB9606211A GB9606211A GB2299188A GB 2299188 A GB2299188 A GB 2299188A GB 9606211 A GB9606211 A GB 9606211A GB 9606211 A GB9606211 A GB 9606211A GB 2299188 A GB2299188 A GB 2299188A
- Authority
- GB
- United Kingdom
- Prior art keywords
- microprocessor
- latch
- data
- microprocessors
- buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
Abstract
First and second microprocessors (1,2) communicate through a parallel data bus (5) through apparatus (3). The apparatus (3) comprises a first latch (7) and a first buffer (8) located in the data bus (5) for transferring data in individual eight bit data words from the first to the second microprocessors (1,2) and a second latch (9) and a second buffer (10) for transferring data in individual eight bit data words from the second microprocessor to the first microprocessor (2,1). First and second interrupt lines (14,16) transmit an interrupt signal from the appropriate first and second microprocessor (1,2) after a data word has been written to the appropriate first and second latch by the first or second microprocessor (1,2), and interrupt acknowledge lines (15,17) transmit an interrupt acknowledge signal from the microprocessor of the first and second microprocessors (1,2) after a data word has been read from the appropriate latch (7,9) through the appropriate buffer (8,10).
Description
"Communication apparatus for communicating
two microprocessors"
The present invention relates to apparatus for communicating data between a first microprocessor and a second microprocessor on a parallel data bus, and the invention also relates to a pair of microprocessors which may be similar or dissimilar communicating with each other through the apparatus according to the invention.
In general, where it is desirable to communicate two microprocessors, the communication is usually carried out using a serial exchange technique whereby the data is clocked between serial ports of the respective microprocessors. While in relatively large and complex installations, this is the most effective way of transferring data between microprocessors, it is relatively complex and can be over sophisticated for use in relatively simple installations where the rate of data transfer is not particularly critical.
There is therefore a need for a less complex apparatus for transferring data between a pair of microprocessors, and between a pair of dissimilar microprocessors.
The present invention is directed towards providing such an apparatus.
According to the invention there is provided apparatus for communicating data between a first microprocessor and a second microprocessor on a parallel data bus which communicates the first and second microprocessors, the apparatus comprising:
a first latch and a first buffer disposed in the parallel data bus so that data can be written from the first microprocessor to the first latch and read from the first latch by the second microprocessor through the first buffer,
a second latch and a second buffer being disposed in the parallel data bus so that data can be written from the second microprocessor to the second latch and read from the second latch by the first microprocessor through the second buffer,
a first interrupt line for communicating an interrupt signal from the first microprocessor to the second microprocessor on data being written to the first latch,
a first interrupt acknowledge line for communicating an interrupt acknowledge signal from the second microprocessor to the first microprocessor on data being read from the first latch by the second microprocessor,
a second interrupt line for communicating an interrupt signal from the second microprocessor to the first microprocessor on data being written to the second latch, and
a second interrupt acknowledge line for communicating an interrupt acknowledge signal from the first microprocessor to the second microprocessor on data being read from the second latch by the first microprocessor.
In one aspect of the invention the first latch and the first buffer are connected together in series and the second latch and the second buffer are connected together in series, the first latch and the first buffer being disposed in the parallel data bus in parallel with the second latch and the second buffer.
Preferably, the data is written to the respective first and second latches sequentially in individual data words of predetermined bit length, and sequentially read from the first and second latches as respective individual data words of the predetermined bit length.
In one aspect of the invention each data word is an eight bit data word.
In another aspect of the invention the first and second microprocessors are dissimilar.
Additionally the invention provides a pair of microprocessors connected together by a parallel data bus for communicating data therebetween, and apparatus according to the invention located in the parallel data bus between the microprocessors for communicating the respective microprocessors with each other.
Additionally, the invention provides a method for communicating data between a first microprocessor and a second microprocessor on a parallel data bus which communicates the first and second microprocessors, the method comprising the steps of transmitting the data sequentially from one microprocessor to the other in a plurality of data words of predetermined bit length, the data words being written sequentially by the first microprocessor to a first latch, and being read by the second microprocessor sequentially from the first latch through a first buffer, the first microprocessor transmitting an interrupt signal to the second microprocessor on a first interrupt line on each data word having been written to the first latch for indicating to the second microprocessor that a data word has been written to the first latch, and the first microprocessor writing the next data word to the first latch on receiving a first interrupt acknowledge signal from the second microprocessor on a first interrupt acknowledge line which communicates the first and second microprocessors on the second microprocessor having read the previous data word from the first latch through the first buffer, and the data words being written sequentially by the second microprocessor to a second latch, and being read by the first microprocessor sequentially from the second latch through a second buffer, the second microprocessor transmitting a second interrupt signal to the first microprocessor on a second interrupt line communicating the first and second microprocessors on each data word having been written to the second latch for indicating to the first microprocessor that a data word has been written to the second latch, and the second microprocessor writing the next data word to the second latch on receiving a second interrupt acknowledge signal from the first microprocessor on a second interrupt acknowledge line communicating the first and second microprocessors on the first microprocessor having read the previous data word from the second latch through the second buffer.
In one aspect of the invention each data word is an eight bit data word.
In another aspect of the invention the first and second microprocessors are dissimilar.
The invention will be more clearly understood from the following description of a preferred embodiment thereof which is given by way of example only, with reference to the accompanying drawing which illustrates a pair of microprocessors communicating according to the invention through apparatus also according to the invention.
Referring to the drawing there is illustrated a pair of dissimilar microprocessors, namely, a first microprocessor 1 and a second microprocessor 2 which communicate with each other through communication apparatus 3 on a single parallel data bus 5. The communication apparatus 3 comprises a first latch 7 and a first buffer 8 which are connected in series and disposed in the data bus 5 for facilitating transfer of data from the first microprocessor 1 to the second microprocessor 2. A second latch 9 and a second buffer 10 for transferring data from the second microprocessor 2 to the first microprocessor 1 are connected in series and are disposed in the data bus 5 in parallel with the first latch 7 and the first buffer 8.A first interrupt line 14 connects the first microprocessor 1 with the second microprocessor 2 for communicating an interrupt signal from the first microprocessor 1 to the second microprocessor 2 after an eight bit data word which is to be transferred from the microprocessor 1 to the second microprocessor 2 has been written to the first latch 7. A first interrupt acknowledge line 15 connected between the first microprocessor 1 and the second microprocessor 2 communicates an interrupt acknowledge signal from the second microprocessor 2 to the first microprocessor 1 on the second microprocessor 2 having read the data word in the first latch 7 through the first buffer 8 for initiating the transfer of the next data word from the first microprocessor 1 to the second microprocessor 2.A second interrupt line 16 connected between the first microprocessor 1 and the second microprocessor 2 communicates an interrupt signal from the second microprocessor 2 to the first microprocessor 1 after an eight bit data word which is to be transferred from the second microprocessor 2 to the first microprocessor 1 has been written to the second latch 9. A second interrupt acknowledge line 17 connecting the first and second microprocessors 1 and 2, respectively, communicates an interrupt acknowledge signal from the first microprocessor 1 to the second microprocessor 2 after the first microprocessor 1 has read the data word from the second latch 9 through the second buffer 10 for initiating transfer of the next data word from the second microprocessor 2 to the first microprocessor 1.
In use, data to be transferred from the first microprocessor 1 and the second microprocessor 2 to the other of the two microprocessors 1 and 2 is transmitted in individual eight bit data words. For example, where data is to be transmitted from the first microprocessor 1 to the second microprocessor 2 the data is prepared in a plurality of eight bit data words. The first eight bit data word is written by the first microprocessor 1 to the first latch 7, and an interrupt signal is communicated on the first interrupt line 14 to the second microprocessor 2.At an appropriate time after receipt of the interrupt signal on the first interrupt line 14, the second microprocessor 2 reads the data word in the first latch 7 through the first buffer 8, and then communicates an interrupt acknowledge signal from the second microprocessor 2 to the first microprocessor 1 on the first interrupt acknowledge line 15. On receipt of the interrupt acknowledge signal the first microprocessor 1 writes the next eight bit data word to the first latch 7, and transmits an interrupt signal on the first interrupt line 14.That data word in the first latch 7 is then read by the second microprocessor 2 through the first buffer 8, and an interrupt acknowledge signal is again transmitted on the first interrupt acknowledge line 15, and so the transfer of data from the first microprocessor 1 to the second microprocessor 2 continues until all the data words have been transferred.
Transfer of data from the second microprocessor 2 to the first microprocessor 1 is similar with the exception that the data words are written from the second microprocessor 2 to the second latch 9 and are read from the second latch 9 through the second buffer 10 by the first microprocessor 1. The appropriate interrupt signals and interrupt acknowledge signals are applied to the second interrupt line 16 and the second interrupt acknowledge line 17, respectively.
The advantages of the invention are many. The communicating apparatus provides relatively low cost communication between two microprocessors which may be similar of dissimilar. The two microprocessors can operate independently during the transfer of data.
Additionally, the transfer of data is independent of clock speed of either of the microprocessors. A further advantage of the invention is that the rate of data transfer adapts automatically to the loading of the two microprocessors. A further advantage of the invention is that the apparatus can be implemented in surface mount technology, and could be implemented in a single programmable array logic device.
It will be appreciated that while the apparatus has been described for writing the data in individual eight bit data words, the apparatus may also be used for writing data in individual sixteen and thirty-two bit data words with appropriately sized latches and buffers.
Claims (12)
1. Apparatus for communicating data between a first microprocessor and a second microprocessor on a parallel data bus which communicates the first and second microprocessors, the apparatus comprising:
a first latch and a first buffer disposed in the parallel data bus so that data can be written from the first microprocessor to the first latch and read from the first latch by the second microprocessor through the first buffer,
a second latch and a second buffer being disposed in the parallel data bus so that data can be written from the second microprocessor to the second latch and read from the second latch by the first microprocessor through the second buffer,
a first interrupt line for communicating an interrupt signal from the first microprocessor to the second microprocessor on data being written to the first latch,
a first interrupt acknowledge line for communicating an interrupt acknowledge signal from the second microprocessor to the first microprocessor on data being read from the first latch by the second microprocessor,
a second interrupt line for communicating an interrupt signal from the second microprocessor to the first microprocessor on data being written to the second latch, and
a second interrupt acknowledge line for communicating an interrupt acknowledge signal from the first microprocessor to the second microprocessor on data being read from the second latch by the first microprocessor.
2. Apparatus as claimed in Claim 1 in which the first latch and the first buffer are connected together in series and the second latch and the second buffer are connected together in series, the first latch and the first buffer being disposed in the parallel data bus in parallel with the second latch and the second buffer.
3. Apparatus as claimed in Claim 1 or 2 in which the data is written to the respective first and second latches sequentially in individual data words of predetermined bit length, and read sequentially from the first and second latches as respective individual data words of the predetermined bit length.
4. Apparatus as claimed in Claim 3 in which each data word is an eight bit data word.
5. Apparatus as claimed in any preceding claim in which the first and second microprocessors are dissimilar.
6. Apparatus for communicating data between a first microprocessor and a second microprocessor on a parallel data bus which communicates the first and second microprocessors, the apparatus being substantially as described herein with reference to and as illustrated in the accompanying drawing.
7. A pair of microprocessors connected together by a parallel data bus for communicating data therebetween, and apparatus according to any preceding claim being located in the parallel data bus between the microprocessors for communicating the respective microprocessors with each other.
8. A pair of microprocessors connected together by a parallel data bus for communicating data therebetween, the pair of microprocessors being connected together substantially as described herein with reference to and as illustrated in the accompanying drawing.
9. A method for communicating data between a first microprocessor and a second microprocessor on a parallel data bus which communicates the first and second microprocessors, the method comprising the steps of transmitting the data sequentially from one microprocessor to the other in a plurality of data words of predetermined bit length, the data words being written sequentially by the first microprocessor to a first latch, and being read by the second microprocessor sequentially from the first latch through a first buffer, the first microprocessor transmitting an interrupt signal to the second microprocessor on a first interrupt line on each data word having been written to the first latch for indicating to the second microprocessor that a data word has been written to the first latch, and the first microprocessor writing the next data word to the first latch on receiving a first interrupt acknowledge signal from the second microprocessor on a first interrupt acknowledge line which communicates the first and second microprocessors on the second microprocessor having read the previous data word from the first latch through the first buffer, and the data words being written sequentially by the second microprocessor to a second latch, and being read by the first microprocessor sequentially from the second latch through a second buffer, the second microprocessor transmitting a second interrupt signal to the first microprocessor on a second interrupt line communicating the first and second microprocessors on each data word having been written to the second latch for indicating to the first microprocessor that a data word has been written to the second latch, and the second microprocessor writing the next data word to the second latch on receiving a second interrupt acknowledge signal from the first microprocessor on a second interrupt acknowledge line communicating the first and second microprocessors on the first microprocessor having read the previous data word from the second latch through the second buffer.
10. A method as claimed in Claim 9 in which each data word is an eight bit data word.
11. A method as claimed in Claim 9 or 10 in which the first and second microprocessors are dissimilar.
12. A method for communicating data between a first microprocessor and a second microprocessor on a parallel data bus which communicates the first and second microprocessors, the method being substantially as described herein with reference to and as illustrated in the accompanying drawing.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IES950209 IES950209A2 (en) | 1995-03-24 | 1995-03-24 | Communication apparatus for communicating two microprocessors |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9606211D0 GB9606211D0 (en) | 1996-05-29 |
| GB2299188A true GB2299188A (en) | 1996-09-25 |
| GB2299188B GB2299188B (en) | 2000-03-22 |
Family
ID=11040691
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9606211A Expired - Fee Related GB2299188B (en) | 1995-03-24 | 1996-03-25 | Communication apparatus for communicating two microprocessors |
Country Status (2)
| Country | Link |
|---|---|
| GB (1) | GB2299188B (en) |
| IE (1) | IES950209A2 (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1575868A (en) * | 1977-03-01 | 1980-10-01 | Ericsson Telefon Ab L M | Address and break signal generator for generating addresses and break signals |
| US4698746A (en) * | 1983-05-25 | 1987-10-06 | Ramtek Corporation | Multiprocessor communication method and apparatus |
| EP0283628A2 (en) * | 1987-02-24 | 1988-09-28 | Digital Equipment Corporation | Bus interface circuit for digital data processor |
| US4827398A (en) * | 1984-07-17 | 1989-05-02 | Societe D'applications Generales D'electricite Et De Mecanique Sagem | Process for interconnecting microprocessors |
| EP0378401A2 (en) * | 1989-01-13 | 1990-07-18 | International Business Machines Corporation | Data communications system |
| EP0602769A2 (en) * | 1992-12-18 | 1994-06-22 | Fujitsu Limited | A multiprocessor system |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4669044A (en) * | 1984-07-02 | 1987-05-26 | Ncr Corporation | High speed data transmission system |
| DE3501194C2 (en) * | 1985-01-16 | 1997-06-19 | Bosch Gmbh Robert | Method and device for data exchange between microprocessors |
-
1995
- 1995-03-24 IE IES950209 patent/IES950209A2/en not_active IP Right Cessation
-
1996
- 1996-03-25 GB GB9606211A patent/GB2299188B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1575868A (en) * | 1977-03-01 | 1980-10-01 | Ericsson Telefon Ab L M | Address and break signal generator for generating addresses and break signals |
| US4698746A (en) * | 1983-05-25 | 1987-10-06 | Ramtek Corporation | Multiprocessor communication method and apparatus |
| US4827398A (en) * | 1984-07-17 | 1989-05-02 | Societe D'applications Generales D'electricite Et De Mecanique Sagem | Process for interconnecting microprocessors |
| EP0283628A2 (en) * | 1987-02-24 | 1988-09-28 | Digital Equipment Corporation | Bus interface circuit for digital data processor |
| EP0378401A2 (en) * | 1989-01-13 | 1990-07-18 | International Business Machines Corporation | Data communications system |
| EP0602769A2 (en) * | 1992-12-18 | 1994-06-22 | Fujitsu Limited | A multiprocessor system |
Also Published As
| Publication number | Publication date |
|---|---|
| IES65387B2 (en) | 1995-10-18 |
| GB2299188B (en) | 2000-03-22 |
| IES950209A2 (en) | 1995-10-18 |
| GB9606211D0 (en) | 1996-05-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20000622 |