GB2297652A - Microchip module assemblies - Google Patents

Microchip module assemblies Download PDF

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Publication number
GB2297652A
GB2297652A GB9601609A GB9601609A GB2297652A GB 2297652 A GB2297652 A GB 2297652A GB 9601609 A GB9601609 A GB 9601609A GB 9601609 A GB9601609 A GB 9601609A GB 2297652 A GB2297652 A GB 2297652A
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United Kingdom
Prior art keywords
solder
substrate
module
printed circuit
accordance
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Granted
Application number
GB9601609A
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GB2297652B (en
GB9601609D0 (en
Inventor
David John Pedder
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Plessey Semiconductors Ltd
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Plessey Semiconductors Ltd
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Priority claimed from GBGB9502178.8A external-priority patent/GB9502178D0/en
Application filed by Plessey Semiconductors Ltd filed Critical Plessey Semiconductors Ltd
Priority to GB9601609A priority Critical patent/GB2297652B/en
Publication of GB9601609D0 publication Critical patent/GB9601609D0/en
Publication of GB2297652A publication Critical patent/GB2297652A/en
Application granted granted Critical
Publication of GB2297652B publication Critical patent/GB2297652B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10439—Position of a single component
    • H05K2201/10477—Inverted
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

Low profile microchip module assemblies are formed by first mounting one or more active semiconductor integrated circuit chips 2,3 on a multilayer metallisation and dielectric structure on a substrate 1 of, say, silicon or alumina, by wire bonding or flip-chip solder bonding, and then inverting the substrate and mounting it on a printed circuit board 9 by means of solder bump connections 8. The solder bump connections are sufficiently high for the chips to be held clear of the printed circuit board.

Description

Microchip Module Assemblies The present invention relates to microchip module (MCM) assemblies.
Modern microelectronic system construction is demanding ever greater levels of integration and the use of packaging techniques that provide cost effective, compact assemblies and sub-assemblies. The demand is particularly strong in the area of portable electronic products where assembly size, weight, power consumption and cost are critical. The emergence of the PCMCIA computer industry standard for miniaturised circuit card expansion slots in portable computing equipment also places a growing emphasis on the physical height of electronic assemblies.
A variety of thin film deposited technologies, known as MCM-D, have been developed to provide islands of high density integration in such electronics assemblies.
The MCM-D assemblies involve multiple silicon, GaAs and related active devices mounted on the MCM-D substrate by wire bonding or by flip chip solder bonding. The MCM-D substrate provides a multilayer metallisation and dielectric structure defined on a silicon, alumina or other suitable base substrate layer to provide ground, power and signal routing structures and, in certain MCM-D processes, a full range of integrated thin film passive components, including resistors, capacitors and inductors. The substrate is manufactured by IC-like processing methods and employs feature sizes that are between those of standard IC and pcb processes.
A variety of techniques may be employed for packaging MCM-D assemblies.
High reliability, high thermal dissipation MCM-D designs may be packaged in hermetic ceramic enclosures manufactured by established methods. Module designs that require an hermetic environment for reasons of device performance stability, for example where SAW devices are included within the package structure, may also employ ceramic packaging techniques. The package form factor will be selected according to the application and may include leadless ceramic chip carriers, leaded ceramic flatpacks, e pin grid arrays, land grid arrays and ball grid arrays.
Plastic packaging techniques may also be employed with MCM-D8assembliest Substrate assemblies may be mounted on metallic lead frames, wire bonds made between the substrate and the lead frame and the plastic package body defined by injection moulding. Alternatively, where compatible base substrate materials, such as alumina are employed, the package leads may be brazed directly to the MCM-D base material and this assembly then processed through the plastic moulding stage. Plastic packaging usually involves lower packaging costs than ceramic packaging and is therefore a preferred option where the level of module integration, thermal dissipation, device stability and compatibility allow.
The above MCM-D packaging techniques all involve greater physical thickness than single chip IC packaging, due to the presence of separate substrate and chip layers.
According to the present invention there is provided a module on board structure in which a microchip module assembly, comprising a microchip module substrate and at least one active semiconductor device mounted on said substrate, is mounted on and connected directly to electrical conductors formed on a surface of a fine line printed circuit board by means of an array of solder bump connections, with said active device between said microchip module substrate and said surface.
Such a structure allows very low profile, low cost assembly and packaging of thin film deposited, MCM-D assemblies directly onto the surface of fine line printed circuit boards. The structure utilises an MCM-D substrate onto which active silicon, GaAs and related devices are assembled by wire bonding or flip chip bonding. This assembly is inverted and mounted on and connected directly to the printed circuit board by an array of solder sphere connections. The mounted assembly may be protected from environmental degradation by filling the space between the inverted MCM-D assembly and the circuit board with a filled epoxy material that has an expansion coefficient closely matched to that of the solder sphere material.
A module on board structure will now be described with reference to the drawing, which shows the structure diagrammatically in cross-section.
Referring to the drawing the MCM-D substrate 1 comprises a silicon, alumina or other suitable base substrate on which is defined the multilayer metallisation and dielectric structure that provides the ground, power and signal routing functions and integrated passive components (not shown). Active devices 2 and 3 are attached to the substrate I and interconnected by wire bonding 4 or by flip chip solder bonding 5, the latter technique being preferred in this case. In either case, the device thickness should be minimised. GaAs devices are conventionally manufactured at 100 to 200 micrometres thickness and are therefore immediately compatible with this structure.
Silicon ICs, that are manufactured at 525 micrometres thickness and above, require back lapping to thicknesses of 200 to 300 micrometres in order to be compatible with this approach. The MCM-D substrate base layer will be typically the same thickness as standard silicon IC wafers, i.e. 525 micrometres.
Where flip chip solder bonding 5 is employed, the gap between the chip and the MCM-D substrate is filled with a suitable filled polymeric encapsulent material 6.
Such materials are filled with inorganic filler compounds to ensure that the final thermal expansion coefficient is close to that of the solder alloy composition employed in the flip chip solder bonds 5. The underfill material 6 ensures good thermal and power cycling and the absence of voids when the board level assembly is finally encapsulated.
The flip chip encapsulent material 6 is applied by a capillary action, infiltration process at a slightly elevated temperature (60 to 100qC) from a series of lines of the uncured encapsulent material dispensed along one or more sides of the flip chip device 2. The underfill material is then cured by a suitable thermal treatment to develop its final properties.
Where wire bonding 4 is employed, film or other adhesive materials 7 may be employed to attach the die to the substrate. The wire bonding is required to be low profile to ensure compatibility with the module on board structure. After wire bonding, polymeric encapsulation of the wires may be employed to provide mechanical protection in subsequent handling operations.
The MCM-D substrate 1 is further provided with larger diameter solder bump connection points 8 to provide the electrical connections to the printed circuit board 9 in the final assembly. These solder bumps 9 will commonly be defined around the perimeter of the module substrate 1, although connections within the substrate area may be employed to advantage in some applications. The solderable metallisation and solder layers for these solder bumps may be applied in the same process steps that are employed to define the solder bumps for the active device attachment. Typical materials for these layers include solderable CrCuAu multilayer metallisations and 95%Pb-5%Sn solder (wt%). The dimensions and separations of these larger diameter bonds will be determined primarily by the height of the mounted devices 2 and 3 on the MCM-D substrate 1.The bond height must be greater than the mounted component height, i.e. typically greater than 200 micrometres. The bond diameter is likely to be in the range from 100 to 500 micrometres. A proportion of the solder volume required in the final module-to-board connections may be supplied in the substrate bumping process. This may involve a substrate bump thickness between 15 and 125 micrometres. Additional solder volume may be added to the module-to-board connections in the form of discrete solder spheres that are alloyed with the deposited solder layer. Such solder spheres may employ high melting point 90%Pb-10%Sn solder or low melting point eutectic solder as required.
After device assembly to the MCM-D substrate 1 and completion of the underfill and encapsulation processes, the module is functionally tested prior to assembly to the printed circuit board 9.
The fine line printed circuit board 9 to which the MCM-D substrate 1 is attached is provided with a matching array of solderable copper lands and solder bumps as required. The board level solder bumps may be defined using solder plating techniques in which solder is applied over an area larger than the land area and then reflowed to increase the local solder bump height. Alternatively discrete solder spheres may be employed as described earlier. The solderable regions of the copper metallisation on the board are defined by means of a suitably patterned solder resist masking layer.
The prepared substrate module is inverted and soldered onto the bumped printed circuit board 9 using standard surface mounting pick and place and solder reflow equipment. Suitable flux materials may be employed to improve wetting of the solder joints. After solder bonding the flux residues may be removed by appropriate solvent cleaning procedures. The overall solder connection geometries are designed to give a separation between the MCM-D substrate active surface and the circuit board surface of about 400 micrometres.
After solder bonding, the cap between the board and the MCM-D assembly may be filled, in a similar manner to that employed for the MCM-D flip chip devices 2, with a suitable, filled polymeric encapsulent material 10. As noted earlier, such materials are filled with inorganic filler compounds to ensure that the final thermal expansion coefficient is close to that of the solder alloy composition employed in the flip chip solder bonds themselves. The underfill material 10 ensures good thermal transfer between module 1 and the board 9, and high solder joint reliability under conditions of thermal and power cycling. The reliability enhancement aspect is of particular importance as a result of the mismatch of thermal expansion coefficients between the silicon or alumina MCM-D substrate 1 and the printed circuit board material.The module encapsulent material is also applied by a capillary action, infiltration process at a slightly elevated temperature (60 to 100 C) from a series of lines of the uncured encapsulent material dispensed along one or more sides of the module assembly. The underfill material is then cured by a suitable thermal treatment to develop its final properties. Acceptable reliability is anticipated for such module assemblies up to l5mm on a side between silicon MCM-D substrates and standard, FR4 printed circuit card materials under commercial environmental conditions.
The overall MCM-D module on board structure provides a low profile assembly, with a height equal to the total of the MCM-D substrate thickness and the solder connection height (typically up to 1.0 mm). The area of the assembly is equal to the module substrate area plus the small surrounding miniscus area associated with the incorporation of the underfill material. This then allows the attachment of local heat sink or electrical screening structures (not shown) to the rear of the MCM-D substrate 1. Local screening structures may also be incorporated into the printed circuit board construction below the assembly.
The structure described above also involves the absolute minimum volume of packaging materials and, through the use of the solder connection method, the use of a single mounting and bonding operation. This must therefore lead to a minimal packaging cost for the particular module on board function.

Claims (7)

1. A module on board structure in which a microchip module assembly, comprising a microchip module substrate and at least one active semiconductor device mounted on said substrate, is mounted on and connected directly to electrical conductors formed on a surface of a fine line printed circuit board by means of an array of solder bump connections, with said active device between said microchip module substrate and said surface.
2. A module on board structure in accordance with Claim 1 wherein said active device is mounted on said substrate by flip-chip solder bonding, and spaces left between said device and said substrate after solder bonding are arranged to be substantially filled with a polymer material having a coefficient of thermal expansion substantially matched to that of the solder bonding.
3. A module on board structure in accordance with Claim 1 or Claim 2 wherein the solder bumps are of diameters between 100 and 500 micrometres and the final spacing between the substrate and the surface of the printed circuit board is up to 400 micrometres.
4. A method of making a structure in accordance with Claim 2 wherein solderable metallisation and solder layers for the flip chip bonding and for the solder bump connections are applied to the substrate in the same process steps.
5. A method of making a structure in accordance with Claim I wherein solder bumps are defined on connection lands of the printed circuit board by solder plating a larger area than that of each land and then melting the solder plating such that reflow by surface tension increases the height of the solder layer over each respective land.
6. A method of making a structure in accordance with Claim 1 wherein discrete solder bodies are utilised to add solder volume to the solder bump connections.
7. A module on board structure substantially as hereinbefore described with reference to the accompanying drawing.
GB9601609A 1995-02-03 1996-01-26 Microchip module assemblies Expired - Fee Related GB2297652B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB9601609A GB2297652B (en) 1995-02-03 1996-01-26 Microchip module assemblies

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB9502178.8A GB9502178D0 (en) 1995-02-03 1995-02-03 MCM-D Assemblies
GB9601609A GB2297652B (en) 1995-02-03 1996-01-26 Microchip module assemblies

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GB9601609D0 GB9601609D0 (en) 1996-03-27
GB2297652A true GB2297652A (en) 1996-08-07
GB2297652B GB2297652B (en) 1999-03-31

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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EP1137067A2 (en) * 2000-03-20 2001-09-26 Agere Systems Guardian Corporation Multi-chip ball grid array ic packages
EP1137067A3 (en) * 2000-03-20 2007-09-26 Agere Systems Guardian Corporation Multi-chip ball grid array ic packages
US6632704B2 (en) 2000-12-19 2003-10-14 Intel Corporation Molded flip chip package
US6838313B2 (en) 2000-12-19 2005-01-04 Intel Corporation Molded flip chip package
WO2002082577A1 (en) * 2001-04-06 2002-10-17 Koninklijke Philips Electronics N.V. Microwave circuit
US6833775B2 (en) 2001-04-06 2004-12-21 Koninklijke Philips Electronics N.V. Microwave circuit
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WO2002101812A1 (en) * 2001-06-08 2002-12-19 Intel Corporation Chip lead frames
WO2003030255A2 (en) * 2001-10-03 2003-04-10 Formfactor, Inc. Multiple die interconnect system
WO2003030255A3 (en) * 2001-10-03 2003-10-30 Formfactor Inc Multiple die interconnect system
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GB9601609D0 (en) 1996-03-27

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