GB2277659A - Attenuation of digital signals during transmission - Google Patents

Abstract

A system is shown for determining the effect of a transmission medium 15 upon a digital (e.g. serial video) signal transmitted over said medium (e.g. coaxial cable). A clock signal is extracted from a digital data signal using phase lock loop 20. The positions of transitions of said clock signal are compared at 19 against the positions of transitions of said data signal and an output signal is produced indicative of said comparison, (e.g. if an error threshold is exceeded). <IMAGE>

Description

TRANSMITTING DIGITAL SIGNALS The present invention relates to determining the effect of a transmission medium upon a digital signal transmitted by said medium.

The transmission characteristics of many types of transmission media are well documented. For example, coaxial cable will attenuate signals at a rate proportional to the length of the cable and proportional to the reciprocal of the square root of the transmission frequency. Thus, such a transmission medium will tend to distort digital signals, given that the level of attenuation will be different for different frequency components of the signal.

When transmitting high speed digital data, for example, at a rate greater than 100 megabits per second, it is desirable to engineer transmission paths for optimum performance with respect to the signals they are intended to transmit. In particular, it is undesirable to have a transmission bandwidth which is significantly greater than the minimum bandwidth necessary for transmitting the signals. A transmission medium having a significantly higher bandwidth than necessary will tend to be more expensive than a medium having optimum bandwidth.

Furthermore, it is desirable to discourage the transmission of signals or signal components having a frequency higher than the necessary maximum because such high frequency components, while not conveying any more information, increase the likelihood of inductive interference. Thus, additional cost may be added to the system if measures have to be taken to remove interference, therefore, it is desirable to minimise intereference at source.

In recent years, digital standards for the transmission of video signals have developed and such signals may now be transmitted as serial bit streams.

For example, D1 component video signals may be transmitted as a serial bit stream at 270 megabits per second. Similarly digitized composite signals (D2) may be transmitted at 177 megabits per second for PAL or at 144 megabits per second for NTSC. In addition, higher bit rates have been proposed for wide screen video signals and for high definition video signals.

Within a video facility, such as an editing suite, a post production facility or a broadcasting facility, it is desirable to use serial digital transmission because this significantly reduces the amount of physical signal transmission media required. Thus, digital serial video signals are, by convention, transmitted over coaxial cable and chip-sets are commercially available for effecting conversion between serial and parallel form.

If a video facility, which may have in excess of 300 digital serial video transmission cables, cable of a suitable type will be selected, so as to optimise transmission performance. During the commissioning of such a system, equipment will be made available to check that each transmission path provides optimum transmission characteristics, thereby ensuring error-free transmission along the path of interest with minimal re-transmission of unwanted high frequency signals, which could induce noise in other transmission paths.

A problem with systems of this type is that, while functioning perfectly well in their original configuration, problems may be encountered if attempts are made to reconfigure the system and, in particular, to extend the length of cables in the system. Although a cable may transmit a signal perfectly well in its original configuration, a significant amount of equipment is required to determine the extent to which a cable may be extended before a critical limit is reached, after which intolerable levels of errors are introduced.

In an attempt to determine an extent to which a cable run may be extended before catastophic errors are introduced, it is known to insert lengths of cable of increasing lengths and to thereafter test the transmission paths. Thus, for example, an additional fifty meters of cable may be introduced into the cable path and a simple test may be performed by checking whether the system is still functional.

However, a fifty metre length of coaxial cable is quite bulky and heavy when coiled up and is difficult to maneouvre within confined spaces.

A cable simulating device is disclosed in United Kingdom Patent Application 9208087.8, filed on 13 April 1992 which, in response to operating a number of small switches, is capable of emulating varying lengths of cable. However, such an approach has a problem in that it is still necessary to perform tests on the system, thereby introducing a level of subjective analysis. Furthermore, an assessment as to the integrity of the cable run is also dependent, in such circumstances, upon all of the other circuit elements between a signal source and a signal display apparatus. Thus, a decision may be made to the effect that a cable length cannot be increased, in circumstances where a cable of the required length would be suitable if modifications were made to the system elsewhere.Thus, it would be desirable to provide a more accurate and reliable procedure for determining the extent to which a cable may be extended or the extent to which other modifications may be made to a system without the need for large, expensive and sophisticated equipment.

According to a first aspect of the present invention, there is provided an apparatus for determining the effect of a transmission medium upon a digital signal transmitted over said medium, characterised by extracting a clock signal from said data signal, comparing the position of transitions of said clock signal against the positions of transitions of said data signal and producing an output signal indicative of said comparison.

The invention will now be described by way of example only, with reference to the accomanying drawings in which: Figure 1 illustrates a transmission environment for serial digital signals; Figure 2 illustrates ideal and practical transmission waveforms; Figure 3 shows a first embodiment of the present invention; Figure 4 shows a second embodiment of the present ivention; and Figure 5 shows a third embodiment of the present invention.

The embodiments of the invention relate specifically to the transmission of serial digital video signals, although it should be appreciated that the techniques are equally applicable to the transmission of digital signals representing any quantity when transmitted at similar transmission rates.

A transmission system for serial digital video signals is shown in Figure 1, in which said signals are transmitted over a 200 metre coaxial cable 15.

Signals are supplied to said cable from an amplifier 16, after conversion from parallel form to a serial time divided multiplex. At the receiving end of the coaxial cable 15, the signal is amplified an equalised by an equalizer 17, before being re-digitized or sliced by a comparator 18. The output from the comparator 18 is supplied to a processing circuit 19 and also to a phase locked loop 20. The phase locked loop 20 re-generates a clock signal from the sliced input signal and supplies said clock signal to the processor 19.

The equalizer 17 compensates for the frequency response of the cable 15. As previously stated, the attenuation of the cable 15 varies with frequency, which will in turn disort the digital signal being supplied over the cable. Thus, the equalizer 17 provides complementary amplification, effectively boosting the higher frequency components to a greater extent than the lower frequency components.

An input sequence of ones and zeros is shown in Figure 2, consisting of the string 1, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0. Waveform 21 represents an idealised digital signal for this data stream and signal 22 represents the positions at which the data stream 21 should be interrogated, to determine whether is is conveying a data level one or a data level zero. When transmitting serial D1 composite signals, data are required at a rate of 270 times per second, which requires the transmitted signal to be capable of representing a transition from one level to another at said rate of 270 megabits per second. Each cycle of a transmitted signal consists of two transitions, therefore the minimum bandwidth requirement for transmitting such a signal is 135 megahertz which, in turn, would result in a signal being transmitted of the type identified by reference 23.Thus, it should be appreciated that the actual transmitted waveform, identified by 23, differs significantly from the idealized waveform, identified at 21. Transmission bandwidth is minimised so as to optimise transmission over the channel, reduce the cost of the transmission channel medium and reduce the high energy content, so as to inhibit cross-talk.

Edges of the transmitted signal 23 are detected and provide the means for regenerating a clock signal, using the phase lock loop 20. A clock signal regenerated from signal 23 is identified by reference 24. The rising edges of the clock signal 24 are actually out of phase with the ideal sampling points, identified by reference 22, therefore modification to the clock signal is required in the processing means 19, so as to ensure that the equalized and sliced signal supplied to the processor 19 is sampled at the correct positions.

As shown in Figure 2, sampling positions 22 are centrally located within data slots of the idealized transmission signal 21. These sampling points may occur anywhere within the data slot, except at the actual transition points. Thus, the margin for placing the data signal 21 in phase with the sampling points 22 is very large, that is to say, significant phase shifts may be tolerated before data corruption occurs. The range over which the signal may be successfully sampled is referred to as the sampling window. As the integrity of the transmitted signal 23 decreases, the size of the sampling window also decreases, until a point is reached at wiiich the sampling window is so small that it is no longer possible to transmit signals without an intolerable degree of errors.

As is well known in the art, the transmitted signal 23 may be displayed on an oscilloscope, with a level of persistence such that a plurality of scans are displayed simultanenously. The resulting display shows distinctive eye-shaped regions bounded by examples of the waveform. As is known, the previously defined window is related to the height of the eyes shown in the display and reference may be made to eye-height.

Providing a display on an oscilloscope and measuring eye height is time consuming and requires a significant amount of equipment. The present embodiments are, effectively, directed towards providing an indication of eye-height or sampling window width and provide an indication of to the extent to which a channel may be degraded, before an intolerable level of errors are introduced into a transmitted signal.

For any particular transmission standard, the interval between the rising edge of the regenerated clock signal and the next sampling point is known, therefore, a suitable delay period may be introduced to the regenerated clock signal in order to generate a sampling signal.

As shown in Figure 2, the regenerated clock signal is generated in phase with transitions occuring in the equalised and sliced input transmitted signal. As the transmitted signal is corupted, the comparator 18 will produce transitions in the signal supplied to processor 19 at positions where, ideally, they should not occur. Thus, under allowable operating conditions, the actual transitions should occur within an allowable window with reference to the regenerated clock signal. Furthemore, the actual position of the transition within the window gives an indication of the integrity of the transmission medium 15 and, in particular, an indication as to the extent to which the length of the transmission path may be increased.

A first embodiment of the invention is shown in Figure 3. As shown in Figure 1, the signal received from the transmission path is equalised by an equaliser 17 and then sliced, to regenerate the digital signal, as shown at 26 in Figure 2.

A phase locked loop 20 is synchronized to the transitions occuring within the regenerated data, averaging temporal jitter, so as to regenerate the clock signal, as indicated at 24 in Figure 2.

Referring the regenerated clock signal indicated at 24 to the orignal sampling positions indicated at 22, it can be seen that the rising edges of the regenerated clock signal coincide with the edges of the data, rather than the sampling positions. Thus, a suitable delay is introduced to the clock signal by a delay device 31, to produce a regenerated sampling signal, identified at 25 in Figure 2.

The phase locked loop 20 will average out the received data signal due to its inherent resonance. However, as previously stated, the positions of transitions, on a bitby-bit basis, within the regenerated data signal 26, will depart form their idealised positions, indicated at 21,as signal degradation occurs. This degradation will occur due to transmission losses within the transmission medium 15 and also due to timing jitter.

Under normal operation, the regenerated data signal cannot be expected to perfectly follow the original input data and transitions within the regenerated data will drift from their idealised positions. Initially, this will not cause problems and the original data will be reconstituted without error. However, a window exists within which the data can be regenerated satisfactorily but beyond which data corruption becomes fatal. The embodiments shown in Figure 3 is arranged to give an indication of the position of transitions within the regenerated datastream, with reference to the regenerated sampling signal.

The regenerated sampling signal, from comparator 18 is supplied to a series of delay elements D1,D2, D3 etc, via a differentiating circuit 31.

The differentiating circuit 31 modifies the regenerated pulses, to provide pulses occurring at equivalent positions but with a known duration of 0.5 nanoseconds.

In the embodiment, for 601 component digital video, the data has a transition rate of 270 megabits per second and each data pulse differentiated by circuit 31, is clocked through the delay lines D1, D2 etc at ten times this rate. Thus,the tap T1 produces a data pulse at clock rate plus 0.1 of clock rate, tap T2 produces pulses at clock plus 0.2 and tap T3 at clock plus 0.3 etc, such that tap T9 produces signals at clock plus 0.9. Thus, after being clocked out of delay element D9, during the next internal clock period, the output from the differentiating circuit 31 will be clocked into the first delay element D1.

The duration of the differentiated signal produced by circuit 31 is such that, during its transmission through the delay elements D1 to D9, only one of the taps, at any time, produces an output at logic level one, the remainder being at logic level zero.

The output from the comparator 18 is also used, as shown in Figure 1, to regenerate the clock signal and is, therefore, supplied to the phase locked loop 20, which regenerates the clock signal identified at 24 in Figure 2.

A delay element 32 is arranged to delay the regenerated clock signal to produce a regenerated sampling signal, identified at 25 in Figure 2. This regenerated sampling signal is then differentiated in a differentiating circuit 33, similar to circuit 31. Thereafter, sampling pulses, having a duration of 0.5 nanoseconds, for example, are simultaneously supplied to gates G1 to G2.

Each gate also receives, at its second input, a respective tap from the delay line, that is to say, tap T1 is supplied to gate G1, tap T2 to gate G2 and tap T3 to gate G3 etc.

When a positive transition occurs to the regenerated data signal, shown at 26, a differentiated pulse will be supplied to the delay line D1 to D9. Each tap will supply the differentiated pulse to its respective gate G1 to G9 and, at one of these gates, as the delayed and differentiated data signal is being received from a tap, the delayed, differentiated and regenerated sampling signal will also be received at the gate's other input. Thus, for each data pulse, a coincidence will occur, in that the delayed data pulse arid the differentiated sample pulse both be presen-t arrive at a gate and thereby change the state of that gate.

Under ideal operating conditions, a differentiated data pulse will be supplied to gate G5 from delay element D5 in when a differentiated sampling pulse is supplied to all of gates G1 to G9. Thus, for each differentiated data pulse, representing a logic level one, gate G5 will be placed into its active condition, resulting in a signal being supplied to its respective latch circuit L5.

Each gate G1 to G9 has a latch circuit associated therewith, with latch L1 detailed in Figure 3. Thus, each latch L1 to L9 includes a bistable element, which is set by receiving an active signal from its respective gate and reset by receiving a reset signal on line 34.

Under most operating conditions, the phase relationship between the regenerated sampling signal and the regenerated data signal will not be ideal and gates other than gate G5 may be activated. Thus, if the data timing advances with reference to the sampling signal, the data signal will advance Further along the delay line, such that gates G6 and above may be activated. Similarly, if the data transition is delayed, propagation on along the delay line D1 to D9 will not be so advanced when the regenerated sampling signal arrives, therefore gates G4 or below may be activated.

In an operating environment, it may, for example, be determined that, say, variations in phase resulting in any of gates G3 to G7 being activated represents tolerable transmission. However, if data transitions drift beyond this, resulting in gates G1, G2, G8 or G9 being activated, this represents unsatisfactory data transmission and suitable measures may be taken.

The output from each latch L1 to L9 is supplied to a processing circuit 35. The processing circuit analyses the output from each of the latches L1 to L9 and provides a reset signal to reset line 34.

The delay lines D1 to D9 operate at a very high rate, the data being clocked therethrough at ten times the data transmission rate. Similarly, gates Gl to G9 and latches L1 to L9 must operate at very high rates, to ensure that the short differentiated signals are correctly gated and latched. However, it is not necessary for circuit 35 to be capable of operating at these rates, because the circuit is arranged to provide an indication of limits, rather than a statistical analysis of data variations. has, processing circuit 35 is not arranged to provide an output stating how many times a particular gate has operated, although, in an alternative embodiment, the system could be configured in this way.The latches L1 to L9 are provided so that processing circuit 35 can be simplified, using circuit elements operating at a much lower clock rate.

Thus, processing circuit 35 is not arranged to determine how many times a particular gate has activated but is arranged to say whether, over a predetermined period, a particular gate has activated at least once, resulting in its respective latch being set. Thus, for example, the latches L1 to L9 may be interrogated after, say, 1,00C clock pulses, whereafter, each latch Ll to L9 is interrogated and a reset pulse is supplied to the reset line 34.

A second embodiment is shown in Figure 4 which, rather than being able to identify the position of any transition in the data stream, it is directed solely towards detecting error conditions and producing all output when an error has been detected.

Referring to Figure 3, it is assumed that an error condition exists if, during operation, transitions occuring in the data signal are such that gate G1 or gate G9 are activated. Thus, the circuit shown in Figure 4 is a simiplified version of the circuit shown in Figure 3, which is only concerned with identifying these error conditions.

The data signal is differentiated in a circuit 41, similar to circuit 31 shown in Figure 3. The differentiated pulses are then supplied to a delay line, consisting of delays D1 to D9, similar to devices D1 to D9 in Figure 3. However, the circuit is only concerned with phase relationships which would activate gate 1 or gate 9, therefore a tap T1 is provided after delay D1 and a second tap T9 is provided after the delay D9, with no additional taps being provided. Taps T1 and T9 are supplied to respective gates G1 and G9, which also receive inputs from the differentiated clock signal, supplied via a differentiator 42, similar to differentiator 33 in Figure 3.

Thus, if when the differentiated sampling signal is supplied to both gate G1 and G9, an error signal will be produced if the data pulse is being clocked out of delay element D1 or out of delay element D9.

At all other positions, an error value is not produced.

Outputs from gates G1 and G9 are supplied to an OR gate 43 which in turn provides an output to z latch circuit 44. Thus, if either gate G1 or gate G9 produce an output, OR gate 43 will produce an output and the latch 44 will be set. In this embodiment, the latch 44 remains set and produces an error signal until a reset signal is generated by a resetting device 45.

Thus, the circuit shown in Figure 4 may be connected to a transmission position and data may Pe supplied for a period of time. If during this period of time no error signals are produced by the latch 44, the transmission medium may be considered error free.

A third embodiment is shown in Figure 5, in which the phase of the sampling signal is modified and then compared againtst the regenerated data signal.

The sampling signal is supplied to a divider 41, which produces a sequence of pulses for each sampling pulse. These pulses are supplied to an integrator 42, which in turn supplies a signal ramp to a comparator 43. The comparator 43 receives a variable reference signal, via control device 44.

As a sampling pulse is received, divided pulses will start to be generated by circuit 41 and the ramp from circuit 42 will start to build uF from an Initial zero level. When the output produced by the integrator 42 exceeds the value produced by the reference, controlled by device 44, the compartor 43 produces an output which is supplied to a gate 45. A display device 46 indicates a condition at which the pulse produced by comparator 43 is coincident with the pulse received from the regenerated data stream.

Thus, the relative phase between the regenerated dta transitions and the sampling signals may be determined by the level of adjustment required to device 44.

Claims (4)

CLAIMS:

1. An apparatus for determining the effect of a transmission medium upon a digital signal transmitted over said medium, characterised by extracting a clock signal from said data signal, comparing the position of transmissions of said clock signal against the positions of transitions of said data signal and producing an output signal indicative of said comparison.

2. A method of determining the effect of a transmission medium upon a digital signal transmitted over said medium, characterised by extracting a clock signal from said data signal, comparing the position of transitions of said clock signal against the positions of transitions of said data signal and producing an output signal indicative of said comparison.

3. Apparatus for determining the effect of a transmission medium upon a digital signal transmitted over said medium, substantially as herein described with reference to Figures 3, 4 and 5.

4. A method of determining the effect of a transmission medium upon a digital signal transmitted over said medium, substantially as herein described with reference to the accompanying drawings.