GB2261971A - Electrically erasable programmable read only memory (EEPROM) device - Google Patents

Abstract

An EEPROM device has a circuit for supplying a voltage having a greater absolute value than a threshold voltage of a non-selected over-erased single transistor memory cell MC21 to a non-selected word line WL2 connected to the control electrode of the non-selected memory cell MC21 in order to enable accurate reading of a selected memory cell MC11 coupled in parallel with the non-selected memory cell MC21 between a selected bit line BL1 and a common source line CS. Further groups of selected cells and over-erased cells (Fig 3) may have their respective source lines CS coupled via transfer transistors (T1-T3) to common source lines (CS1-CS3), the transfer transistors being controlled by address signals (A1-A3). An example of a word line voltage supply circuit is described (Fig 4) for supplying a negative voltage (Vb) of -2 to -5 volts, a voltage of 5 volts and a high voltage (Vpp) of 10 to 12 volts to a word line. In reading data, a lower voltage having an absolute value greater than the absolute value of the threshold voltage of the over-erased memory cell is applied to the non-selected word line WL2 and a voltage of, eg, 5 volts is applied to a gate of the selected memory cell via the selected word line WL1. <IMAGE>

Description

ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY (EEPROM) DEVICE The present invention relates to electrically erasable programmable read only memory devices.

Generally, a memory cell of an electrically erasable programmable read only memory device may be constructed with a first transistor for use in cell selection, and a second transistor for use in cell sensing. Since the size of each memory cell is large, however, the achievement of a highly integrated semiconductor memory device becomes difficult. In an effort to obtain greater integration density, a single transistor memory cell was proposed in 1985 by Excel Co. (see IEDM, 1985, pp. 616-619). Subsequently, a more reliable flash type memory cell has been developed by Intel Corporation (see Symposium on VLSI Tech., 1988, pp. 31-32).

In a conventional flash type electrically erasable programmable read only memory cell, a floating gate and a control gate are deposited on a gate oxide layer formed over a channel region between a drain and a source. A distributed bit line is in contact with the drain. The floating gate overlaps a portion of the source and data is erased by the tunnelling of electrons between the floating gate and the source. In order to read data, a gate voltage of 5 volts for example, a drain voltage ranging from zero to 5 volts, and a source voltage of zero volts may be applied. Then the data is read from the memory cell by sensing a threshold voltage of a transistor. When programming the data, voltages of about 12.5, 6.5 and zero volts are applied to the gate, drain and source respectively.

One transistor memory cells of matrix form are arranged in an electrically erasable programmable read only memory device with bit lines connected to the drains to form a memory cell array. Thus, a specific word line is selected by address decoding, and memory cells connected to the word line can be simultaneously erased or programmed. While reading a specific memory cell array, a gate voltage of a neighbouring memory cell connected to a non-selected word line is usually at zero volts, and consequently the transistor of the neighbouring memory cell is turned off.

Typically, threshold voltages of erased or programmed cells have a Gaussian distribution with the threshold voltage of the erased cells having a lower value than the programmed cells. While memory cells exhibiting threshold voltages indicating either an over-erased state or an incompletely erased state can be corrected by repeating the erasing and programming operations, some memory cells exhibit negative threshold voltages. An example of a method for correcting over-erased memory cells is disclosed in Korean Patent No. 91-14096 (=- GB Patent Application 92 17371.5).If there is an over-erased memory cell having a negative threshold voltage in a memory cell array and that over-erased memory cell is a non-selected cell, even if a non-selected word line voltage of zero volts is applied to the gate electrode of that over-erased non-selected memory cell, the non-selected cell can be turned on. When, for example, a potential difference between a gate voltage of.a non-selected memory cell exhibiting a negative threshold voltage and its bit line voltage becomes more negative than the threshold voltage, the potential difference may be larger than a threshold voltage of the memory cell; consequently the non-selected memory cell may be turned on together with selected memory cell. Hence, data of the selected memory cell can not be correctly read out, with the result that a read operation is liable to malfunction.

Preferred embodiments of the present invention aim to provide an improved electrically erasable programmable read only memory.

Another aim is to provide a process and an electrically erasable programmable read only memory device capable of performing an accurate read operation even if there is an over-erased memory cell.

It is still another aim to provide a process and device enabling selected memory cells of an electrically programmable read only memory to be reliably and accurately read even while a non-selected neighbouring memory cell is in an over-erased state.

According to one aspect of the present invention, an electrically erasable programmable read only memory device has an over-erased memory cell provided with one transistor, and a circuit for supplying a voltage having a lower absolute value than a threshold voltage of the over-erased memory cell to a word line connected to the over-erased memory cell.

According to another aspect of the present invention, there is provided an electrically erasable programmable read only memory device having a predetermined operational state, and comprising: a first memory cell comprising a first and single transistor coupled to a bit line and to a first word line; a second memory cell comprising a second and single transistor coupled to said bit line and to a second word line; and voltage supply means for providing to said first word line, during the predetermined operational state, a first voltage having a first absolute value less than a second absolute value of a threshold voltage of said first transistor, and for providing a second and different voltage to said second word line to enable determination of a state of a binary characteristic of said second memory cell, said second and different voltage having a polarity opposite to said first voltage.

Preferably, the voltage supply means further comprises: means for generating said second voltage for reading said binary characteristic from the second memory cell during said operational state; and means for generating a third voltage for writing said binary characteristic into the second memory cell.

Preferably, the voltage supply means comprises: an address terminal; a third transistor having a principal electrical conduction channel coupled between said address terminal and a first node; a first terminal for receiving said first voltage; a second terminal for receiving said second voltage; a fourth transistor having a principal channel of electrical conduction coupled between said first node and said second terminal, and a control electrode connected to one of said first and second word lines; and means coupled between said first and second terminals, for providing one of said first and second voltages to one of said first and second word lines in dependence upon an address signal applied to said address terminal.

Preferably, the voltage supply means comprises a plurality of voltage supply circuits, each of said voltage supply circuits comprising: an address terminal; a third transistor having a principal electrical conduction channel coupled between said address terminal and a first node; a first terminal for receiving said first voltage; a second terminal for receiving said second voltage; a fourth transistor having a principal channel of electrical conduction coupled between said first node and said second terminal, and a control electrode connected to a corresponding one of said first and second word lines; and means coupled between said first and second terminals, for providing one of said first and second voltages to said corresponding one of said first and second word lines in dependence upon an address signal applied to said address terminal.

Preferably: said first transistor has a first electrode of a principal channel of electrical conduction coupled to said bit line; said second transistor has a first electrode of a principal channel of electrical conduction coupled to said bit line; and a second electrode of said principal channel of said first transistor and a second electrode of said principal channel of said second transistor are coupled to a common node.

A device as above may further comprise transfer means having a control electrode coupled to respond to an address signal, coupled between said common node and a source line.

According to another aspect of the present invention, there is provided an electrically erasable programmable read only memory device, comprising: a plurality of bit lines; a plurality of word lines; a plurality of memory cells each comprising a single transistor, coupled in an array with different pairs of said bit lines and said word line; a first one of said memory cells having a first transistor with a principal channel for electrical conduction coupled between a first one of said bit lines and a common source line, and exhibiting a threshold voltage of conduction; a second one of said memory cells having a second transistor with a principal channel for electrical conduction coupled between said first one of said bit lines and said common sense line; and voltage supply means for providing to said first word line, during an operation for reading a binary characteristic of said second one of said memory cells, a first voltage having a first absolute value less than a second absolute value of said threshold voltage, and for providing to said second word line a second and different voltage having a polarity opposite to said first voltage to enable determination of a state of said binary characteristic, said second and different voltage having a polarity opposite to said first voltage.

Preferably, the voltage supply means further comprises: means for generating said second voltage for reading said binary characteristic from the second memory cell during said operation; and means for generating a third voltage for writing said binary characteristic into the second memory cell.

Preferably, the voltage supply means comprises: an address terminal; a third transistor having a principal electrical conduction channel coupled between said address terminal and a first node; a first terminal for receiving said first voltage; a second terminal for receiving said second voltage; a fourth transistor having a principal channel of electrical conduction coupled between said first node and said second terminal, and a control electrode connected to one of said first and second word lines; and means coupled between said first and second terminals, for providing one of said first and second voltages to one of said first and second word lines in dependence upon an address signal applied to said address terminal.

Preferably, the voltage supply means comprises a plurality of voltage supply circuits, each of said voltage supply circuits comprising: an address terminal; a third transistor having a principal electrical conduction channel coupled between said address terminal and a first node; a first terminal for receiving said first voltage; a second terminal for receiving said second voltage; a fourth transistor having a principal channel of electrical conduction coupled between said first node and said second terminal, and a control electrode connected to a corresponding one of said first and second word lines; and means coupled between said first and second terminals, for providing one of said first and second voltages to said corresponding one of said first and second word lines in dependence upon an address signal applied to said address terminal.

Preferably: said first transistor has a first electrode of a principal channel of electrical conduction coupled to said bit line; said second transistor has a first electrode of a principal channel of electrical conduction coupled to said bit line; and a second electrode of said principal channel of said first transistor and a second electrode of said principal channel of said second transistor are coupled to a common node.

A device as above may further comprise transfer means having a control electrode coupled to respond to an address signal, coupled between said common node and a source line.

According to a further aspect of the present invention, there is provided a process for reading memory cells of a read only memory cell, comprising: applying to a control electrode of a first and single transistor comprising a first memory cell coupled to a selected line, a first potential when reading a binary characteristic of said first memory cell; and while reading said binary characteristic of said first memory cell, applying to a control electrode of a second and single transistor comprising a second memory cell coupled to said selected line, a second potential having a polarity opposite to said first potential, said second transistor having a threshold voltage and said second potential having an absolute value greater than said threshold voltage.

A process as above may comprise the steps of: coupling principal channels for electrical conduction by said first and second transistors in parallel between said selected line and a first node; and while reading said binary characteristic of said first memory cell, applying to a third transistor coupled between said first node and a common line, a third potential enabling conduction of an electrical current between said first node and said common line.

A process as above may comprise the steps of: coupling principal channels for electrical conduction by third and fourth transistors in parallel between said selected line and a first node; and while reading said binary characteristic of said first memory cell, maintaining at a third transistor coupled between said first node and a common line, a third potential preventing conduction of an electrical current between said first node and said common line A process as above may comprise the further steps of: : coupling principal channels for electrical conduction by third and fourth transistors in parallel between said selected line and a second node; while reading said binary characteristic of said first memory cell, maintaining at a fourth transistor coupled between said second node and a source line, a fourth potential preventing conduction of an electrical current between said second node and said source line.

According to another aspect of the present invention, there is provided a process for reading binary characteristics of an electrically programmable read only memory device, comprising the steps of: determining a threshold voltage of a first memory cell; and supplying a first voltage to sustain said first memory cell in an electrically non-conducting state while reading said binary characteristics of a second memory cell coupled in parallel between a selected bit line and a common source line, with said first voltage having a first absolute value greater than a second absolute value of said threshold voltage of said first memory cell.

Preferably, said step of determining said threshold voltage comprises determining said threshold voltage of an over-erased memory cell.

According to a further aspect of the present invention, there is provided a process for reading binary characteristics of an electrically programmable read only memory device, comprising the steps of: supplying, during a first predetermined operational condition, a first voltage to sustain an over-erased memory cell in an off state, said first voltage having a first absolute value greater than a second absolute value of an overerased memory cell; and supplying, during said first predetermined operational condition, a second voltage to turn on a selected memory cell coupled in parallel with said over-erased memory cell between a selected bit line and a common source line.

Preferably, said predetermined operational condition is comprised of a selected one of reading from and writing to said selected memory cell.

According to another aspect of the present invention, there is provided a process for sustaining in an off state, a field effect transistor behaving as an over-erased memory cell in read only memory device, said process comprising the steps of: selecting, during a predetermined operational state, a selected memory cell for a predetermined function; and providing during said predetermined function, to a control electrode of said field effect transistor, a voltage having a first absolute value less than a second absolute value of a threshold voltage exhibited by said field effect transistor while said field effect transistor is behaving as an over-erased memory cell, to sustain said field effect transistor in a non-electrically conducting state.

For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying diagrammatic drawings in which: Figure 1 is a cross-sectional view of a general representation of an electrically erasable programmable read only memory cell; Figure 1A is an equivalent circuit diagram of the memory cell shown in Figure 1; Figure 1B is a characteristic graph illustrating drain currents during erasing and programming states of the cell of Figure 1; Figure 1C is a graph illustrating characteristic threshold voltage distribution of erased and programmed cells in an electrically erasable programmable read only memory cell array; Figure 1D is a schematic circuit diagram of a memory cell array including an over-erased cell that is in a read state;; Figure 2 is a circuit diagram of one example of a memory cell array constructed according to the principles of the present invention; Figure 3 is a circuit diagram of another example of a memory cell array constructed according to the principles of the present invention; and Figure 4 is a circuit diagram of one example of a word line voltage supplying circuit constructed according to the principles of the present invention.

Turning now to the drawings, Figure 1 shows a cross-sectional view of a conventional flash type electrically erasable programmable read only memory cell. The flash type memory cell includes a floating gate 4 and a control gate 6 which are deposited upon a gate oxide layer 3 formed over a channel region between a drain 1 and a source 2. A distributed bit line 7 is in electrical contact with drain 1. The floating gate 4 overlaps a portion of source 2 and data is erased by the tunnelling of electrons flowing between floating gate 4 and source 2. The equivalent circuit diagram of Figure 1 is shown in Figure 1A. When reading data, a gate voltage Vg of 5 volts, a drain voltage Vd ranging from zero to 5 volts, and a source voltage V5 of zero volts are applied. Then the data is read out by sensing the threshold voltage of a transistor.When programming the data, voltages of about 12.5, 6.5 and zero volts are applied to the gate, drain and source respectively. Thus, electrons are injected to the floating gate 4 from the edge of drain 1 that overlaps floating gate 4. Meanwhile, when erasing data, the gate voltage Vg is zero volts and the source voltage V5 is about 11.5 volts. Then, electrons tunnel to source 2 from floating gate 4 to erase the data. That is, a tunnelling phenomenon of electrons caused by an electric field between the control gate 6 and a diffusion region is used. The supply voltages during reading, programming and erasing of data are shown in Table 1.

- Table 1

S read < 5 volts 5 volts zero volts program 6.5 volts 12.5 volts zero volts erase floating zero volts 11.5 volts Referring to the two coordinate graph shown in Figure 1B, when the gate voltage Vg of 5 volts and the drain voltage Vd ranging from zero to 5 volts are applied in order to read a memory cell erased or programmed in the above described manner, a drain current 1d of 100,t4A is detected in the erased memory cell to be read while in an on state, and a drain current Id of zero amperes is detected in the programmed cell to be read while in an off state.

The earlier mentioned one transistor memory cells of matrix form are disposed in an electrically erasable programmable read only memory device with bit lines connected to the drain electrodes to form a memory cell array.

Thus, a specific word line is selected by address decoding, and the memory cells connected to the word line can be simultaneously erased or programmed.

When reading a specific memory cell of an array in these conventional devices, however, since a neighbouring non-selected gate voltage of a memory cell connected to a non-selected word line is zero volts, a transistor of that non-selected memory cell is turned off.

Referring now to Figure 1C, a threshold voltage of erased or programmed cells exhibits a Gaussian distribution. Note that the threshold voltages of the erased cells have lower values than the programmed cells.

Memory cells corresponding to hatched area A exhibit an over-erased state, memory cells corresponding to area B exhibit an incompletely erased state while memory cells corresponding to area C show an incompletely programmed state. The memory cells corresponding to areas B and C can be corrected by repeating the erasing and programming operations. An example of a method for correction of over-erased memory cells is disclosed in Korean Patent No. 91-14096. When re-erasing the memory cells in area A, however, the memory cells may have a negative threshold voltage because the threshold voltage is much lower. That is, if there is an over-erased memory cell having a negative threshold voltage in a memory cell array, and the memory cell is the non-selected cell, even if a non-selected word line voltage of zero volts shown in Table 1 is applied, the non-selected cell can still be turned on.

Figure 1D is a schematic circuit diagram of a memory cell array showing a read state when there is an over-erased memory cell. Assume that a memory cell MC1 is selected on condition that an over-erased memory cell MC2 has a threshold voltage of about - 1.5 volts. Voltages of 5 volts and zero volts are applied to gate lines WL1 and WL2 respectively and thus to the gate electrodes of the transistors forming memory cells MC1, MC2, respectively, and voltages of 3 volts and zero volts are applied to drain lines BL1 and BL2 respectively. Then, since a potential difference between a gate voltage of the non-selected memory cell MC2 and bit line BL1 becomes -3 volts and the absolute value of this potential difference is larger than the threshold voltage of -1.5 volts for memory cell MC2, the unselected memory cell MC2 is undesirably turned on together with the selected memory cell MCl.Hence, data of the selected memory cell MC1 can not be correctly read out, with the result that a read operation is liable to malfunction.

In the following example of embodiments constructed according to the present invention, erasing and programming operations, and voltage state, may be identical to those hereinbefore described. In the circuit represented by Figure 2, if a memory cell MC21 is an over-erased cell and a memory cell MC11 is selected, voltages of 5 volts, 1 to 3 volts and zero volts are applied to a word line WLl, and bit lines BL1 and BL2 respectively, as is shown in Table 2 below. Moreover, a voltage of zero volts is applied to a common source line CS, and a voltage of -2 to -5 volts is applied to a word line WL2 connected to the over-erased memory cell My21.

- Table 2

WL1 WL2 BLI BL2 CS 5 volts -2 to -5 volts 1 to 3 volts zero volts zero volts Then, since a threshold voltage of the over-erased memory cell MC21 has a larger absolute value than a gate-to-source voltage of the memory cell MC21, memory cell MC21 is turned off. Therefore, only the threshold voltage of the selected memory cell MC11 appears on the bit line BL1 and a read operation is performed. Here, the circuit shown in Figure 2 is only a portion of a memory cell array of an electronically erasable programmable read only memory.That is, in consideration of a threshold voltage of an over-erased memory cell, a voltage forestalling the turning on the over-erased memory cell is supplied to a non-selected word line connected to the overerased memory cell.

Referring now to Figure 3, it is assumed that memory cells MC ii and MC12, connected to a word line WL1, and a memory cell My41, connected to a word line WIA, are over-erased memory cells and that a memory cell MC31 connected to a word line WL3 is selected. The sources of memory cells MCi 1, MC12, MC21 and MC22 are commonly connected to a first common source line CS1. Similarly, the sources of memory cells MC31, MC32, MC41 and MC42 are commonly connected to second common source line CS2, and the sources of memory cells MC51, MC52, MC61 and MC62 are commonly connected to a third common source line CS3.Moreover, transfer transistors T1, T2 and T3 each connected to the common source lines CS1, CS2, and CS3 are controlled by address signals Al, A2 and A3 respectively.

In a programming state, voltages of 10 to 12 volts and 5 to 10 volts are applied to the selected word line WL3 and a selected bit line BL1 respectively. Moreover, a voltage of zero volts is supplied to the non-selected word lines WL1, WL2, WIA, WL5 and WL6, non-selected bit line BL2 and the second common source line CS2.

During a read state, however, a voltage of -2 to -5 volts is applied to the non-selected word line WL4 of the memory cell MC41 sharing the source thereof with the selected memory cell My3 1. The first and third common source lines CS1 and CS3 connected to the sources of the non-selected memory cells maintain a floating state and a voltage of zero volts is applied to the address signals Al and A3 to turn off transfer transistors T1 and T3.

Since the address signal A2 of 5 volts is applied to the gate of transfer transistor T2, transistor T2 is turned on and a current path is formed between the source of the selected memory cell MC3 1 and the second common source line CS2. The non-selected word line WL1 commonly connected to the control gates of the non-selected memory cells MCi 1 and MC12 is at a potential of zero volts, and therefore memory cells MCi 1 and MC12 have a condition capable of forming a channel because memory cells Mell and MC12 are in an over-erased state.The sources of the memory cells Mll and M12 however are not in a current pull-down path and the neighbouring nonselected memory cells MC21 and MC22 are in a turned off state, i.e. the sources of memory cells MC21 and MC22 are in a floating state; consequently, memory cells MCi 1 and MC12 have no effect on the potential of the selected neighbouring bit line BL1 on which data of the selected memory cell MC31 appears. In the same way as is shown in Figure 2, the non-selected memory cell MC41 is turned off by a negative voltage of -2 to 5 volts (i. e. a voltage having a polarity opposite to the polarity of the voltage applied to the selected word line WL3) applied to the word line WL4 of the memory cell MC41 sharing the source thereof with the selected memory cell MC31 under the condition of an over-erased state.Therefore, by forming a current path including only the selected bit line BL1, a channel of the selected memory cell MC3 1 and the second common source line CS2, the data can be accurately read from the selected memory cell MC31. During a read operation the supply voltages are as indicated in Table 3.

- Table 3

NhlLl zero Volts WL2 WL2 zero Volts WL3 5 volts WIA -2 to -5 volts WL5 zero Volts WL6 zero Volts BL1 1 to 3 volts BL2 floating Al zero volts A2 5 volts A3 zero volts CS1 floating CS2 zero volts CS3 floating It will be understood by those skilled in the art that the method applied to Figure 2 may also be applied to Figure 3. In this case, the voltage of -2 to -5 volts, that is, a voltage with an amplitude similar to the potential applied to unselected word line WL4 may also by applied to the non-selected word line WL1.

An example of a word line voltage supply circuit for supplying a negative voltage Vb of -2 to -5 volts, a voltage of 5 volts, and a high voltage Vpp of 10 to 12 volts to a word line is shown in Figure 4. In reading data, a lower voltage having an absolute value greater than a threshold voltage (i.e.

having an absolute value greater than the absolute value of the threshold voltage) of an over-erased memory cell is applied to a non-selected word line, and a voltage of, for example, 5 volts is applied to a gate electrode of a selected memory cell via the selected word line. The word line voltage supplying circuit shown in Figure 4 is constructed in each word line and an address signal ADD is generated from a row decoder. An inverter I5 including a PMOS transistor M3 and an NMOS transistor M4 is connected between a terminal of node 3 for power voltage Vcc or the high voltage Vpp, and a terminal 5 for a negative voltage Vb. An output node 4 of inverter IS is coupled to a word line W/L and connected to a gate of a PMOS transistor M2. Transistor M2 has a channel connected between node 3 and an input terminal 2 of inverter I5.An NMOS transistor M1 having a gate coupled to a voltage of 5 volts is connected between input terminal 2 of inverter I5 and terminal 1 for receiving the address signal ADD. When a memory cell along a word line to which node 4 is coupled is selected to be read, a voltage of 5 volts is applied to node 3, and when programmed, a high voltage Vpp of 10 to 12 volts is supplied to node 3. A high voltage generating circuit disclosed in, for example, Korean Patent Nos. 90-12816 or 90-14829, the teachings of both of which patents are expressly incorporated into this specification, may be used to provide the high voltage Vpp.

In reading data, a back bias generator may be used for supplying the negative voltage Vb. In order that the NMOS transistor M4 has a threshold voltage with an absolute value larger than the negative voltage Vb, it is desirable to form the NMOS transistor M4 on a substrate region or well, separated from a substrate region or well on which other NMOS transistors are formed. If the address signal ADD applied to terminal 1 is set to a logic "low" state of zero volts, the PMOS transistor M3 of the inverter IS is turned on and the voltage of about 5 volts is supplied to a selected word line.

Meanwhile, if the address signal ADD applied to terminal 1 is set to a logic "high" state of 5 volts, since the NMOS transistor M4 is turned on, the negative voltage Vb with a potential of, for example, -2 to -5 volts is supplied to a non-selected word line.

The memory cell array disclosed in Figures 2 and 3 may be constructed with NAND gates, but the same memory cell array may, alternatively, be constructed with NOR gates.

As described above, even if there is an over-erased cell coupled to either the same bit line, or to the same common source line as a selected memory cell, the electrically erasable programmable read only memory device can accurately read out data from the selected memory cell.

While preferred embodiments of the present invention have been particularly shown and described, it will be understood by those skilled in the art that foregoing and other changes in form and details may be made without departing from the spirit and scope of the present invention.

The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

Claims (23)

CLAIMS:

1. An electrically erasable programmable read only memory device having a predetermined operational state, and comprising: a first memory cell comprising a first and single transistor coupled to a bit line and to a first word line; a second memory cell comprising a second and single transistor coupled to said bit line and to a second word line; and voltage supply means for providing to said first word line, during the predetermined operational state, a first voltage having a first absolute value less than a second absolute value of a threshold voltage of said first transistor, and for providing a second and different voltage to said second word line to enable determination of a state of a binary characteristic of said second memory cell, said second and different voltage having a polarity opposite to said first voltage.

2. A device according to claim 1, wherein the voltage supply means further comprises: means for generating said second voltage for reading said binary characteristic from the second memory cell during said operational state; and means for generating a third voltage for writing said binary characteristic into the second memory cell.

3. A device according to claim 1, wherein the voltage supply means comprises: an address terminal; a third transistor having a principal electrical conduction channel coupled between said address terminal and a first node; a first terminal for receiving said first voltage; a second terminal for receiving said second voltage; a fourth transistor having a principal channel of electrical conduction coupled between said first node and said second terminal, and a control electrode connected to one of said first and second word lines; and means coupled between said first and second terminals, for providing one of said first and second voltages to one of said first and second word lines in dependence upon an address signal applied to said address terminal.

4. A device according to claim 1, wherein the voltage supply means comprises a plurality of voltage supply circuits, each of said voltage supply circuits comprising: an address terminal; a third transistor having a principal electrical conduction channel coupled between said address terminal and a first node; a first terminal for receiving said first voltage; a second terminal for receiving said second voltage; a fourth transistor having a principal channel of electrical conduction coupled between said first node and said second terminal, and a control electrode connected to a corresponding one of said first and second word lines; and means coupled between said first and second terminals, for providing one of said first and second voltages to said corresponding one of said first and second word lines in dependence upon an address signal applied to said address terminal.

5. A device according to any of the preceding claims, wherein: said first transistor has a first electrode of a principal channel of electrical conduction coupled to said bit line; said second transistor has a first electrode of a principal channel of electrical conduction coupled to said bit line; and a second electrode of said principal channel of said first transistor and a second electrode of said principal channel of said second transistor are coupled to a common node.

6. A device according to claim 5, further comprising transfer means having a control electrode coupled to respond to an address signal, coupled between said common node and a source line.

7. An electrically erasable programmable read only memory device, comprising: a plurality of bit lines; a plurality of word lines; a plurality of memory cells each comprising a single transistor, coupled in an array with different pairs of said bit lines and said word line; a first one of said memory cells having a first transistor with a principal channel for electrical conduction coupled between a first one of said bit lines and a common source line, and exhibiting a threshold voltage of conduction; a second one of said memory cells having a second transistor with a principal channel for electrical conduction coupled between said first one of said bit lines and said common sense line; and voltage supply means for providing to said first word line, during an operation for reading a binary characteristic of said second one of said memory cells, a first voltage having a first absolute value less than a second absolute value of said threshold voltage, and for providing to said second word line a second and different voltage having a polarity opposite to said first voltage to enable determination of a state of said binary characteristic, said second and different voltage having a polarity opposite to said first voltage.

8. A device according to claim 7, wherein the voltage supply means further comprises: means for generating said second voltage for reading said binary characteristic from the second memory cell during said operation; and means for generating a third voltage for writing said binary characteristic into the second memory cell.

9. A device according to claim 7, wherein the voltage supply means comprises: an address terminal; a third transistor having a principal electrical conduction channel coupled between said address terminal and a first node; a first terminal for receiving said first voltage; a second terminal for receiving said second voltage; a fourth transistor having a principal channel of electrical conduction coupled between said first node and said second terminal, and a control electrode connected to one of said first and second word lines; and means coupled between said first and second terminals, for providing one of said first and second voltages to one of said first and second word lines in dependence upon an address signal applied to said address terminal.

10. A device according to claim 7, wherein the voltage supply means comprises a plurality of voltage supply circuits, each of said voltage supply circuits comprising: an address terminal, a third transistor having a principal electrical conduction channel coupled between said address terminal and a first node; a first terminal for receiving said first voltage, a second terminal for receiving said second voltage; a fourth transistor having a principal channel of electrical conduction coupled between said first node and said second terminal, and a control electrode connected to a corresponding one of said first and second word lines; and means coupled between said first and second terminals, for providing one of said first and second voltages to said corresponding one of said first and second word lines in dependence upon an address signal applied to said address terminal.

11. A device according to any of claims 7 to 10, wherein: said first transistor has a first electrode of a principal channel of electrical conduction coupled to said bit line; said second transistor has a first electrode of a principal channel of electrical conduction coupled to said bit line; and a second electrode of said principal channel of said first transistor and a second electrode of said principal channel of said second transistor are coupled to a common node.

12. A device according to claim 11, further comprising transfer means having a control electrode coupled to respond to an address signal, coupled between said common node and a source line.

13. A process for reading memory cells of a read only memory cell, comprising: applying to a control electrode of a first and single transistor comprising a first memory cell coupled to a selected line, a first potential when reading a binary characteristic of said first memory cell; and while reading said binary characteristic of said first memory cell, applying to a control electrode of a second and single transistor comprising a second memory cell coupled to said selected line, a second potential having a polarity opposite to said first potential, said second transistor having a threshold voltage and said second potential having an absolute value greater than said threshold voltage.

14. A process according to claim 13, comprising the steps of: coupling principal channels for electrical conduction by said first and second transistors in parallel between said selected line and a first node; and while reading said binary characteristic of said first memory cell, applying to a third transistor coupled between said first node and a common line, a third potential enabling conduction of an electrical current between said first node and said common line.

15. A process according to claim 13, comprising the steps of: coupling principal channels for electrical conduction by third and fourth transistors in parallel between said selected line and a first node; and while reading said binary characteristic of said first memory cell, maintaining at a third transistor coupled between said first node and a common line, a third potential preventing conduction of an electrical current between said first node and said common line.

16. A process according to claim 14, comprising the further steps of: coupling principal channels for electrical conduction by third and fourth transistors in parallel between said selected line and a second node; while reading said binary characteristic of said first memory cell, maintaining at a fourth transistor coupled between said second node and a source line, a fourth potential preventing conduction of an electrical current between said second node and said source line.

17. A process for reading binary characteristics of an electrically programmable read only memory device, comprising the steps of: determining a threshold voltage of a first memory cell; and supplying a first voltage to sustain said first memory cell in an electrically non-conducting state while reading said binary characteristics of a second memory cell coupled in parallel between a selected bit line and a common source line, with said first voltage having a first absolute value greater than a second absolute value of said threshold voltage of said first memory cell.

18. A process according to claim 17, wherein said step of determining said threshold voltage comprises determining said threshold voltage of an overerased memory cell.

19. A process for reading binary characteristics of an electrically programmable read only memory device, comprising the steps of: supplying, during a first predetermined operational condition, a first voltage to sustain an over-erased memory cell in an off state, said first voltage having a first absolute value greater than a second absolute value of an overerased memory cell; and supplying, during said first predetermined operational condition, a second voltage to turn on a selected memory cell coupled in parallel with said over-erased memory cell between a selected bit line and a common source line.

20. A process according to claim 19, wherein said predetermined operational condition is comprised of a selected one of reading from and writing to said selected memory cell.

21. A process for sustaining in an off state, a field effect transistor behaving as an over-erased memory cell in read only memory device, said process comprising the steps of: selecting, during a predetermined operational state, a selected memory cell for a predetermined function; and providing during said predetermined function, to a control electrode of said field effect transistor, a voltage having a first absolute value less than a second absolute value of a threshold voltage exhibited by said field effect transistor while said field effect transistor is behaving as an over-erased memory cell, to sustain said field effect transistor in a non-electrically conducting state.

22. A memory device substantially as hereinbefore described with reference to Figure 2, 3 or 4 of the accompanying drawings.

23. A process substantially as hereinbefore described with reference to Figure 2, 3 or 4 of the accompanying drawings.