GB2251141A

GB2251141A - Lock security in early/late gate synchronisation PLL

Info

Publication number: GB2251141A
Application number: GB9027634A
Authority: GB
Inventors: Tom Vilhelmsen
Original assignee: Storno AS
Current assignee: Motorola Solutions Danmark AS
Priority date: 1990-12-20
Filing date: 1990-12-20
Publication date: 1992-06-24
Anticipated expiration: 2010-12-20
Also published as: GB2251141B; DE4135531A1; GB9027634D0

Abstract

A phase locked loop (PLL) is provided comprising a signal input, a clock for providing a clocked signal and a phase comparator for comparing the phases of an incoming signal at the signal input and the clocked signal. When the PLL is in a locked state the clocked signal is shifted by phase shifts in opposite directions to maintain the PLL in the locked state, but when in an out-of-lock state, the clocked signal is repeatedly shifted by a phase shift in one direction until the PLL is detected to be in the looked state. The first time the PLL is in the "out of lock" state a decision will be taken as to the direction of phase change to be made, and it is not possible to change the direction until the PLL is back in the in-lock state. 'In lock' may be defined as a phase difference greater than -90 DEG but less than 90 DEG , and a flow diagram of the decision process may be provided. The PLL may lock to a frequency at least four times that of the incoming signal with a divider provided in the loop. The loop provides security of locking. <IMAGE>

Description

1 2251141 LOCK SECURITY IN EARLY/LATE GATE SYNCHRONISATION PLI, This

invention relates to phase locked loops (PLLs) and to security of locking in earlyllate synchronisation PLLs.

Summary of the Prior Art

EP-A-0396970 describes a radio demodulator circuit and a PLI, having an earlyllate gate for synchronisation. In existing earlyllate gate synchronisation PLLs, there exists an "unlocked state" where the PLI, cannot lock to the carrier. This state will only occur if three conditions exist:

1. the SNR is high; 2. the duty cycle of the incoming signal is not exactly 50%; and 3. the phase difference of the recovered carrier and the incoming carrier is 180. If these three conditions, the PLI, will not track to the incoming carrier and the recovered data will be incorrect.

It is an object of the present invention to provide an improved PLL.

Summary of the Invention

According to the present invention, a phase locked loop (PLL) is provided, comprising: a signal input; a clock for providing a clocked signal; phase comparator means for comparing the phases of an incoming signal at a signal input of the clocked signal, characterized by: means for detecting when the PLI, is an out-of- lock state and for detecting when the I'LL is in a locked state; means operable in the locked state for shifting the clocked signal by phased shifts in opposite directions to maintain the PLI, in the locked state; and means operable in the out-of-lock state for repeatedly shifting the clocked signal by a phase shift in one direction until the PLI, is detected to be in the locked state.

Thus, when the PLI, is out of lock, the direction of phase.shift is not allowed to change, until the PLI, reaches the locked state, after 1 2 which time the phase shift is allowed to alternate as required to keep the phase locked.

The "out-of-lock" state is preferably the state in which phase difference between the incoming carrier and the recovered carrier is greater than 90 or less than -90. The "in lock" state is where that phase difference is greater than -90 but less than 90.

The PLL is preferably arranged to lock on a frequency which is about four times the incoming signal and a frequency divider is preferably provided to divide the frequency to the recovered carrier. In this way, the frequency divider can be used to determine the quadrant in which the incoming signal lies in respect to the recovered carrier.

is Brief Description of the Drawings

Fig. 1 shows a phase diagram illustrating the in-lock and out of-lock states.

Fig. 2 shows a circuit diagram of a part of the PLL of the preferred embodiment of the invention.

Fig. 3 shows a timing diagram for the circuit of Fig. 2.

Fig. 4 shows a flow diagram illustrating the operation of the preferred embodiment of the invention.

Detailed Descri12tion of the Preferred Embodiment The following definitions are provided:

e Q& Phased difference between the incoming carrier and the recovered carrier Phase step of the PLL. If the PLL is supposed to lock in NT, where T = llbaud rate then E)A = 180 deg/N.

out of lock 90 deg < E) < -90 deg in lock -90 deg < E) < 90 deg 3 This definition means that if E) = 0 deg the PLL is maximally in lock, and on the opposite site if E) = 180 deg (or -180 deg) the PLL is maximally out of lock.

The normal way to decide which way to make a phase shift is the following:

If 0 deg < E) < 180 deg If -180 deg < E) < 0 deg then 0A = -180/N then E),& = 180/N With these definitions it is easier to explain the lock problem as described above:

If 0 is between 180 and l80-(DC(h)-50N/25-l)l80/N deg and the duty cycle is sorser than 50:L 25/N 19A will be (wrongly) defined to +1801N. Now the next start phase will be above 180 (or -180) in between 180 and 180+(DC(h)-50)N/25-l)180/N. The next decision (on GA) will be -180/N. The opposite way - this means that the PLL will not track Example:

N = 16 Limits on duty cycle 50% 25/N % 48.4%/51-6% Limits on 0 with a dutycycle on 47%/53%: 180 dea + 10.4 deg This example is illustrated in Figure 1.

To overcome the above problem, the PLI, of the preferred embodiment is arranged to track at approximately 4 times the frequency of the incoming carrier (and accordingly 4 times the frequency of the recovered carrier). Any suitable PLI, can be readily constructed by one skilled in the art and reference is made to EP-A-0396970 for further details of such a circuit.

The output of this PLI, is fed to the clock inputs of two flip- flops Q1 and Q2 as shown in Figure 2. Q1 and Q2 are connected in a twisted ring configuration. The Q output of Q1 is fed to the D input of Q2. The negative output of Q2 is fed to the input of Q1. Both Q1 and Q2 are clocked by the output of the I'LL. The circuit described 4 is is a divide-by-4 circuit. The output of Q2 is the recovered carrier. The outputs of Q1 and Q2 are drawn off to be used to determine the time of arrival of a transition in the incoming signal.

Referring to Fig. 3, the outputs of Q1 and Q2 of Fig. 2 are illustrated, as is the clock input. If the transition on the incoming signal occurs between positions (1) and (2), the phase difference between the incoming signal and the recovered carrier is between 0 and 90 degrees. This is indicated by a "V' on the outputs of Q1 and Q2 at the time of arrival of the transition.

Similarly, if the incoming transition occurs between position (2) and (3), the outputs of Q1 and Q2 will be "0" and "1" and the phase difference will be between 90 and 180 degrees. The same principle applies for an incoming transition between positions (3) and (4) and between position (4) and (5).

The sign of 0A is defined once in "out of lock" state. When the PLI, is "in locC state the signal could change each time a transition occurs in the incoming signal. The first time the PLI, gets in the "out of lock" state the following decision will be taken:

2 0If 90 deg < 0 < 180 deg then GA = -180IN If -180 deg < 0 < -90 deg then E),& = 180IN This decision process is illustrated in the flow diagram of Figure 4. Steps 41 and 42 determine that the PLI, is out of lock.

Steps 43 and 44 set the sign of the phase change accordingly and set an "out of locC flag.

If neither decision 41 nor decision 42 determines an out-of lock state, the program passes to steps 45 and 46, which determine whether the PLI, is in lock. If the PLI, is in lock, step 47 or 48 sets the sign of the phase change accordingly and clears the "out of lock" flag. Step 49 checks the "out of lock" flag and if it is not yet cleared, the next earlyllate test is carried out in step 50 and the program returns directly to step 45 (ie. omitting the tests for "out of lock" state - steps 41 and 42). In other words, if the flag is not yet cleared, the sign of 0,& is not allowed to change until E) falls within a range in which it is greater than -90 degrees and less than 90 degrees. Only when it enters that range does step 45 or 46 allow E) to be set again.

Once the "out of lock" flag is cleared, step 49 jumps back to the start of the program and the complete set of tests can be run again, so that steps 41 and 42 come into operation again to determine whether the PLL has jumped to an "out of lock" state.

In normal operation (during tracking), the only steps to be executed are steps 45 to 50.

Other simple rearrangements of the various steps of the Fig. 4 can be devised to achieve the same result.

In summary, the first time the PLL is in the "out of lock" state, the recovered carrier will be sampled and a decision will be taken, and it is not possible to change the direction (the sign of E),&) until the PLL is back in the in-lock state.

A dutycycle other than 50% will take place in a sub-carrier FFSK, FSK, MSK etc system where the group delay varies across the band, thereby causing inter-symbol interference.

A 6

Claims

1. A phase-locked-loop comprising: a signal input; a clock for providing a clocked signal; phase comparator means for comparing the phases of an incoming signal at the signal input and the clocked signal; characterized by means for detecting when the PLL is in an out-of-lock state and for detecting when the PLL is in a locked state; means operable in the locked state for shifting the clocked signal by phase shifts in opposite directions to maintain the PLL in the locked state; and means operable in the out-of-lock state for repeatedly shifting the clocked signal by a phase shift in one direction until the PLL is detected to be in the locked state.

2. A PLL according to claim 1, wherein the means for detecting when the PLL is in the out-of lock state comprises means for determining when the phase difference between the incoming signal and the clocked signal exceeds a predetermined value.

3. A PLL according to claim 2, wherein the predetermined value is approximately 90 degrees.

4. A PLL according to claim 2 or 3, arranged to lock to a frequency at least four times that of the incoming signal and a frequency divider, for dividing the PLL frequency to that of the incoming signal, wherein the means for detecting when the PLL is in the out-of-lock state comprises means for determining the state of the frequency divider at the time of arrival of a transition of the incoming signal.

5. A PLL according to claim 4, wherein the frequency divider comprises two series-connected flip-flops clocked at approximately four times the frequency of the incoming signal, wherein the states of the two flipflops at the time of arrival of a transition of the 7 incoming signal are used to determine whether the PLL is in the locked or out-of-lock state.