GB2250161A

GB2250161A - Arbitration circuits for processors

Info

Publication number: GB2250161A
Application number: GB9025572A
Authority: GB
Inventors: Conrad Charles Cooke; Rodney Hugh Densham
Original assignee: Sony Corp
Current assignee: Sony Corp
Priority date: 1990-11-23
Filing date: 1990-11-23
Publication date: 1992-05-27
Anticipated expiration: 2010-11-23
Also published as: JPH04279956A; GB2250161B; GB9025572D0

Abstract

An arbitration circuit for a processor which is one of a number of processors connected to a common bus is arranged to determine or arbitrate as to whether its associated processor is to have access to the common bus or not, when more than one processor requires access during the same time slot. Arbitration lines A, B, C interconnect the arbitration circuits for the various processors, and each arbitration circuit attempts to impose a priority code on to the arbitration lines. The priority code which remains on the arbitration lines after settling determines which processor wins access to the bus. In order that the arbitration scheme should not be fixed so that particular processors always win priority access, a priority modifying count generator 40 acts to modify each priority code in every arbitration cycle so that the processors have equal priority over a period of time. The arbitration circuits may be connected by a partial or split arbitration line scheme, in order to overcome conflict between particular combinations of priority codes which would otherwise result in no processor winning access to the bus. <IMAGE>

Description

ARBITRATION CIRCUITS FOR PROCESSORS AND PROCESSING SYSTEMS HAVING PLURALITIES OF PROCESSORS This invention relates to arbitration circuits for processors, and in particular to such arbitration circuits for processors to be connected to a common bus, such as in a parallel processor architecture. The invention also relates to processing systems each having a plurality of processors connected to a common bus.

In the situation when a plurality of processors are connected by a common bus, it is necessary for a means to be provided in order to determine or arbitrate as to which processor is to be able to communicate by means of the bus in the event that more than one processor should require access to the bus during the same time slot.

It has been proposed to provide an arbitration circuit in which each processor is connected to a common set of arbitration lines. For example, if eight processors are to be connected to the common bus, three arbitration lines will be provided so that each processor can impose its own unique binary priority based on a node address of the processor on to the arbitration lines. Thus, if the eight processors have node addresses 0 to 7, or in binary 000 to 111, the priority code for each node address can be the inverse thereof, namely 111 to 000, each bit being associated with a corresponding arbitration line. Each processor requiring access during a given time slot imposes its priority code on the arbitration lines, and a predetermined selection scheme is used to decide which priority code is to dominate.For example, in one implementation, a "zero" will dominate if a "zero" and a "one" are presented on a given arbitration line. In this case, if the processor with the node address 0 (000) having a priority code 111, requests access at the same time as the processor with the node address 7 (111) having a priority code 000, the "zeroes" of the node 7 processor will dominate and hence this processor will receive priority access. In other words, the arbitration lines are allowed to settle in each access slot, and if a particular processor 5 priority code is still on the arbitration lines after the lines have settled, that processor wins access to the bus.

One problem with this basic arbitration technique is the existence of a conflict with certain combinations of requests. For example, using the same implementation as given above in which the processor with the node address 7 has the highest priority, if the node 3 and node 4 processors request the bus, the node 3 processor (011) will attempt to impose a priority code of 100 on the arbitration lines whereas the node 4 processor (100) will attempt to impose a priority code of 011 on the arbitration lines. With a "zeroes" dominating arbitration scheme, the combination of the priority codes 100 and 011 will be 000, and hence neither of the processors will gain access to the bus.

Another problem with the basic arbitration technique is that the priority between processors (assuming that there is no priority conflict as outlined above) will always remain the same. Thus, in the example given above, the node 7 processor will always gain priority access over the node 0 processor (or any other). Whereas in certain situations this may not give rise to significant difficulties, in a parallel processor architecture, all the nodes should have equal priority, at least over a given period of time. Accordingly, the basic arbitration technique described above will be inadequate for parallel processing architectures.

According to an aspect of the present invention there is provided an arbitration circuit for a processor connectable to a common bus, the arbitration circuit comprising: means for providing a respective address code identifying the arbitration circuit and its associated processor; means for providing a count value that changes in each arbitration cycle; means for combining the count value with the address code to provide a modified address code that changes in each arbitration cycle; means for supplying a binary priority code derived from the modified address code to common arbitration lines in response to a request signal from the associated processor, the common arbitration lines being connectable to other arbitration circuits associated with other processors connectable to the common bus;; means for establishing a dominant code on the arbitration lines in the event that more than one binary priority code is supplied from more than one arbitration circuit, the dominant code being derived from a selected one of the two possible binary levels on each arbitration line; and means for sending an access enabled signal to the associated processor indicating that the processor has access to the common bus, when the dominant code corresponds to the binary priority code of the arbitration circuit.

In a preferred embodiment, the priority of each arbitration circuit is changed at regular intervals, namely every bus access time slot, by means of combining the changing count value with the address code for each arbitration circuit. This results in all the processors having equal priority access over a period of time.

According to another aspect of the present invention there is provided a processing system having a plurality of processors connected to a common bus, the processing system comprising: a plurality of arbitration circuits respectively associated with the plurality of processors, each arbitration circuit being operable to provide a binary priority code in response to a request signal from its associated processor, the binary priority code being derived from a respective address code identifying the associated processor; and a number of arbitration lines interconnecting the arbitration circuits, each arbitration line being provided for a respective bit of the binary priority codes; wherein each of the arbitration circuits includes means for establishing a dominant code on the arbitration lines in the event that more than one binary priority code is supplied from more than one arbitration circuit, the dominant code being derived from a selected one of the two possible binary levels on each arbitration line, and means for sending an access enabled signal to the associated processor indicating that the processor has access to the common bus, when the dominant code corresponds to the binary priority code of the arbitration circuit; and wherein selected ones of the arbitration lines are split so as to interconnect only specific groups of arbitration circuits in such a way as to avoid conflict resulting from certain combinations of request signals from particular arbitration circuits.

In a preferred embodiment, the arbitration lines are arranged in such a way that the line for the most significant bit connects all of the arbitration circuits together, the line for the least significant bit is split so as to connect only groups of two arbitration circuits together, and the or each line for the or each intermediate bit is split in a correspondingly intermediate manner of groups of arbitration circuits. This split scheme for the arbitration lines has the effect of overcoming conflict between particular combinations of access requests.

The invention will now be described by way of example with reference to the accompanying drawings, throughout which like parts are referred to by like references, and in which: Figure 1 is a circuit diagram of an arbitration circuit according to a basic arbitration technique; Figure 2 is a schematic circuit diagram of eight processors including arbitration lines; Figure 3 is a schematic circuit diagram of eight processors connected by partially-interrupted arbitration lines; and Figure 4 is a circuit diagram of an arbitration circuit according to one embodiment of the invention.

Referring to Figure 1, there is shown an arbitration circuit which is capable of implementing a basic arbitration technique between a plurality of processors connected to a common bus. Each processor has a corresponding arbitration circuit as shown in Figure 1, there being a unique address set by a card address generation circuit 10.

For example, when eight processors are provided, the addresses can be O to 7, 000 to 111 in binary, each bit being present on a respective one of output lines 12A, 12B, 12C from the card address generation circuit 10. The arbitration circuit also includes a request line 14 on which a request signal is present whenever the corresponding processor requires an access to the bus. The output lines 12A to 12C are connected to three respective AND-gates 16A, 16B, 16C, the other inputs of these gates being connected to the request line 14. The outputs of the AND-gates 16A to 16C are connected to the control terminals of respective switches 18A, 18B, 18C, which are operative selectively to connect a logic '0' state voltage to respective terminals of pull-up resistors 20A, 20B, 20C whose other terminals are connected to a logic '1' state voltage. The outputs of the switches 18A to 18C are connected to respective first inputs of EX-OR-gates 22A, 22B, 22C, whose second inputs are respectively connected to the outputs of the AND-gates 16A to 16C. The outputs of the EX-OR-gates 22A to 22C are connected via a three-input NAND-gate 24 to one input of a NOR-gate 26.

The other input of the NOR-gate 26 is connected to the request line 14 via an inverter 28. The output of the NOR-gate 26 is connected to a "win" line 30 on which a win signal is provided if the processor associated with the arbitration circuit is to have access to the bus.

The outputs of the switches 18A to 18C are also connected to respective arbitration lines A, B, C, and the manner in which the arbitration lines A, B, C are used to interconnect with other arbitration circuits and to provide priority bus access for the respective processor will now be described.

Figure 2 shows the manner in which eight processors P-O to P-7 may be connected to a common bus CB, and to respective arbitration circuits AC-O to AC-7, with arbitration lines A, B, C interconnecting all the arbitration circuits AC-O to AC-7. Each of the arbitration circuits AC-O to AC-7 can be as shown in Figure 1. As shown in Figure 2, each arbitration circuit (e.g. AC-O) is connected to its associated processor (e.g. P-O) by the request and win lines 14,30. It will be assumed that the processors P-O to P-7 have respective addresses 0 to 7 (000 to 111) set in the card address generation circuits 10 of the corresponding arbitration circuits AC-O to AC-7.

In operation, when a particular processor requires bus access, it sends a request signal to its associated arbitration circuit.

Assuming, as an example, that the processor P-l (address : 001) has sent a request signal on the request line 14, the AND-gates 16A to 16C will allow the address 001 from the card address generation circuit 10 to pass through in response to the request signal to the switches 18A to 18C. The effect of the pull-up resistors 20A to 20C is for the address 001 to be inverted on the arbitration lines A, B, C as a priority code 110.

Assuming that no other priority code has been applied to the arbitration lines by other arbitration circuits associated with the other processors, in other words no other processor has requested bus access in the same time slot, the priority code 110 and the address 001 are applied to the EX-OR gates 22A to 22C acting as anticoincidence circuits, such that the gates 22A to 22C supply the signal 111 to the three-input NAND-gate 24. The EX-OR gates 22A to 22C and the NAND-gate 24 together form a three-bit anticoincidence comparator, such that, as in the present case, a binary zero is generated only when the priority code (110) on the arbitration lines A, B, C is the inverse of the address (001). Any other combination of codes would generate a binary one.The binary zero from the NAND-gate 24 is then supplied to the NOR-gate 26 along with a binary zero from the request signal inverted by the inverter 28, and this results in a binary one forming the win signal appearing on the win line 30. The win signal is sent to the associated processor to indicate that access to the bus has been won.

If it is now assumed that another processor also requires bus access during the same access slot, that processor will also send a request signal to its associated arbitration circuit. Assuming, as an example, that the processors P-1 (address : 001) and P-7 (address : 111) have both sent request signals on their respective request lines 14, the arbitration circuit AC-1 will, as before, supply the priority code 110 to the arbitration lines A, B, C. However, the arbitration circuit AC-7 will supply the priority code 000 (namely the inverse of its address 111) to the arbitration lines A, B, C. By virtue of the arrangement of the switches 18A to 18C and the pull-up resistors 20A to 20C, a zero bit will dominate on each arbitration line since the respective switch in the corresponding arbitration circuit will pull down the arbitration line state to zero.Thus the application of the priority codes 110 and 000 to the arbitration lines A, B, C will result in a value 000 settling on the arbitration lines, and thus the arbitration circuit AC-1 will not supply a request signal to its processor P-l since the anticoincidence comparator made up of the EX-OR gates 22A to 22C and the NAND-gate 24 will not provide the required binary zero value. On the other hand, the arbitration circuit AC-7 will supply a request signal to its processor P-7 since its anticoincidence comparator provides a binary zero value. This is due to the 000 value on the arbitration lines A, B, C being the inverse of the 111 value supplied from the card address generation circuit 10 via the AND-gates 16A to 16C.Thus the processor P-7 will have priority access to the common bus CB and the processor P-l will need to await another access slot.

A problem with the connection scheme of the arbitration lines A, B, C as shown in Figure 2 is that there is a conflict with certain combinations of requests. For example, if the processors P-3 and P-4 request the bus in the same access slot, their corresponding arbitration circuits AC-3 and AC-4 will attempt to impose the priority codes 100 and 011 respectively (being the inverse of the addresses 011 and 100 respectively), and the zero pull-down effect of the switches 18A to 18C and the resistors 20A to 20C will result in a value of 000 on the arbitration lines A, B, C. Thus neither of the processors P-3 and P-4 will be able to win access to the common bus CB. In order to overcome this, a partial connection scheme for the arbitration lines can be implemented as shown in Figure 3.

Referring to Figure 3, the partial connection scheme for the arbitration lines involves the arbitration line A extending between all of the arbitration circuits AC-O to AC-7 as in Figure 2. However, only the arbitration circuits AC-O to AC3 are connected by an arbitration line B1, the remaining arbitration circuits AC-4 to AC-7 being connected by a separate arbitration line B2. Also, separate arbitration lines C1, C2, C3, C4 are provided respectively to connect the arbitration circuits AC-O and AC-1, AC-2 and AC-3, AC-4 and AC-5, AC-6 and AC-7.

The partial or split arbitration line connection scheme overcomes the problem of conflict with certain combinations of requests. For example, using the same combination as that given above, let it be assumed that the arbitration circuits AC-3 and AC-4 have been instructed by their processors P-3 and P-4 to impose their priority codes on the arbitration lines. The arbitration circuit AC-3 will attempt to impose the priority code 100 on the arbitration lines A, B1, C2. The arbitration circuit AC-4 will attempt to impose the priority code 011 on the arbitration lines A, B2, C3. In accordance with the zero pull-down effect, the arbitration line A will go to zero, and hence the arbitration circuit AC-4 will succeed in winning bus access, since its priority code 011 remains unchanged on the arbitration lines A, B2, C3, whereas the priority code for the arbitration circuit AC-3 on the arbitration lines A, B1, C2 has been changed to 000.

Although the connection scheme of Figure 3 overcomes the problem of conflict with certain request combinations, the operation of the circuit will always give access priority to certain processors. Thus a processor with a higher node number will tend to have priority over those with lower node numbers. This will be undesirable in certain situations such as in a parallel processor architecture in which all processors are to have equal priority. The circuit of Figure 14 achieves this effect by equalizing the priorities of the various processors.

Referring to Figure 4, the illustrated equalised priority arbitration circuit is similar to that shown in Figure 1 (and uses the same reference numerals for similar components) with the addition of a priority modifying count generator 40 and three EX-OR-gates 42A, 42B, 42C. The priority modifying count generator 40 is common to all the arbitration circuits AC-O to AC-7.In this embodiment, the output lines from the card address generation circuit 10 are not applied directly to corresponding inputs of the AND-gates 16A, 16B, 16C, but via corresponding inputs of the EX-OR-gates 42A, 42B, 42C. The count output lines from the priority modifying count generator 40 are connected to the other inputs of the EX-OR-gates 42A, 42B, 42C. The count generator 40 is arranged to change its count value in every arbitration cycle. The change in count value should give equal priority to each count between 0 and 7 and can be arranged in accordance with any suitable predetermined (or possibly random) scheme.

The simplest scheme is for the count to be incremented by one in every arbitration cycle and, after the value 7, for the count to be reset back to 0.

The effect of the count generator 40 and the EX-OR-gates 42A to 42C is to equalise the priority of the various arbitration circuits (and hence their corresponding processors) over a period of time.

Thus, whereas as described above with reference to Figures 1 to 3, the processor with the highest node number tends to have priority access, this will no longer be the case in the circuit of Figure 4, since the priority code of an arbitration circuit will no longer be fixed (for example, as the inverse of its address), but will change in every arbitration cycle according to the result of an "exclusive-or" operation on each address by the priority modifying count.

Accordingly, if a particular processor has priority access in a given arbitration cycle, the probability is that it will lose that priority access in a following arbitration cycle. Some examples of the results of the operation of the EX-OR-gates 42A to 42C and the count generator 40 on the addresses generated by the arbitration circuits AC-O to AC-7 are given below.

AC-O AC-1 AC-2 AC-3 AC-4 AC-5 AC-6 AC-7 address: 000 001 010 011 100 101 110 111 count of 010: 010 011 000 001 110 111 100 101 count of 100: 100 101 110 111 000 001 010 011 count of 011: 011 010 001 000 111 110 101 100 From the above examples, it will be seen that the addresses of the arbitration circuits AC-O to AC-7 are effectively modified by the count values appropriate to each of the arbitration cycles, and hence the priority code which each arbitration circuit attempts to impose on the arbitration lines A, B, C will also differ in each cycle (being the inverse of the count-modified address). Accordingly, no one processor will dominate in winning access to the common bus.

It will be apparent from the above description that the time between priority changes of the arbitration circuits (and hence the processors) will be the time for each access on the bus. A request signal from a processor should be put on and the result (namely win or not) taken off at the priority change boundaries.

The examples given above involve eight processors with eight corresponding arbitration circuits interconnected by three arbitration lines. If a different number of processors are to be provided, the number of arbitration lines may differ. For example, if sixteen processors (and arbitration circuits) are required to share the bus, there should be four arbitration lines. The split or partial connection of the arbitration lines may be similar to that shown in Figure 3. Specifically, the most significant bit line may interconnect all the processors; the next bit line may be split into two groups of eight interconnected processors each; the following bit line may be split into four groups of four interconnected processors each; and the least significant bit line may be split into eight groups of two interconnected processors each.

The arbitration circuits have been shown and described in circuit diagram form as using discrete components. In practice, the circuit operation can be implemented using a fast programmable logic device (PLD), with the hardware present on each card that can access the bus, and with global connections joining the arbitration lines together as required.

Claims

1. An arbitration circuit for a processor connectable to a common bus, the arbitration circuit comprising: means for providing a respective address code identifying the arbitration circuit and its associated processor; means for providing a count value that changes in each arbitration cycle; means for combining the count value with the address code to provide a modified address code that changes in each arbitration cycle; means for supplying a binary priority code derived from the modified address code to common arbitration lines in response to a request signal from the associated processor, the common arbitration lines being connectable to other arbitration circuits associated with other processors connectable to the common bus;; means for establishing a dominant code on the arbitration lines in the event that more than one binary priority code is supplied from more than one arbitration circuit, the dominant code being derived from a selected one of the two possible binary levels on each arbitration line; and means for sending an access enabled signal to the associated processor indicating that the processor has access to the common bus, when the dominant code corresponds to the binary priority code of the arbitration circuit.

2. An arbitration circuit according to claim 1, wherein the means for establishing a dominant code on the arbitration lines is operable to derive each bit of the code with zero being dominant.

3. An arbitration circuit according to claim 1 or claim 2, wherein the means for establishing a dominant code on the arbitration lines comprises a series-connected switch and pull-up resistor combination for each arbitration line, the arbitration line being connected to the junction between the switch and the pull-up resistor.

4. An arbitration circuit according to claim 1, claim 2 or claim 3, wherein the means for sending an access enabled signal comprises a multi-bit comparator for comparing the dominant code on the arbitration lines with the binary priority code of the arbitration circuit.

5. An arbitration circuit according to claim 4, wherein the multibit comparator comprises exclusive-or gating means and a coincidence gating means.

6. An arbitration circuit according to any one of the preceding claims, wherein the means for providing a changing count value comprises an incrementing counter which is incremented by one in each arbitration cycle.

7. An arbitration circuit according to any one of the preceding claims, wherein the means for combining the count value with the address code comprises exclusive-or gating means.

8. An arbitration circuit according to any one of the preceding claims, wherein the means for supplying a binary priority code is operable to provide the binary priority code as an inverse of the modified address code.

9. An arbitration circuit according to claim 8, wherein the means for supplying a binary priority code comprises and-gating means connected to the dominant code establishing means.

10. A processing system having a plurality of processors connected to a common bus, the processing system comprising: a plurality of arbitration circuits respectively associated with the plurality of processors, each arbitration circuit being operable to provide a binary priority code in response to a request signal from its associated processor, the binary priority code being derived from a respective address code identifying the associated processor; and a number of arbitration lines interconnecting the arbitration circuits, each arbitration line being provided for a respective bit of the binary priority codes; wherein each of the arbitration circuits includes means for establishing a dominant code on the arbitration lines in the event that more than one binary priority code is supplied from more than one arbitration circuit, the dominant code being derived from a selected one of the two possible binary levels on each arbitration line, and means for sending an access enabled signal to the associated processor indicating that the processor has access to the common bus, when the dominant code corresponds to the binary priority code of the arbitration circuit; and wherein selected ones of the arbitration lines are split so as to interconnect only specific groups of arbitration circuits in such a way as to avoid conflict resulting from certain combinations of request signals from particular arbitration circuits.

11. A processing system according to claim 10, wherein the arbitration lines are arranged in such a way that the line for the most significant bit of the binary priority codes connects all of the arbitration circuits, the line for the least significant bit of the binary priority codes is split so as to connect only groups of two arbitration circuits together, and the or each line for the or each intermediate bit is split in a corresponding intermediate manner of groups of arbitration circuits.

12. A processing system according to claim 10 or claim 11, comprising means for providing a count value that changes in each arbitration cycle, and wherein each arbitration circuit comprises means for combining the count value with the respective address code to provide a modified address code that changes in each arbitration cycle, the binary priority code being derived from the modified address code.

13. A processing system according to claim 12, wherein the means for providing a changing count value comprises an incrementing counter which is incremented by one in eacti arbitration cycle.

114. A processing system according to any one of claims 10 to 13, wherein for each arbitration circuit, the means for establishing a dominant code on the arbitration lines is operable to derive each bit of the code with zero being dominant.

15. A processing system according to any one of claims 10 to 14, wherein for each arbitration circuit, the means for establishing a dominant code on the arbitration lines comprises a series-connected switch and pull-up resistor combination for each arbitration line, the arbitration line being connected to the junction between the switch and the pull-up resistor.

16. A processing system according to any one of claims 10 to 15, wherein for each arbitration circuit, the multi-bit comparator comprises exclusive-or gating means and a coincidence gating means.

17. A processing system according to claim 16, wherein for each arbitration circuit, the multi-bit comparator comprises exclusive-or gating means and a coincidence gating means.

18. An arbitration circuit for a processor, substantially as herein described with reference to Figure 4 of the accompanying drawings.

19. A processing system substantially as herein described with reference to Figures 1 and 3 or Figures 3 and 4 of the accompanying drawings.