GB2248988A

GB2248988A - Interface circuits

Info

Publication number: GB2248988A
Application number: GB9027194A
Authority: GB
Inventors: Gyo-Jin Han
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1990-10-15
Filing date: 1990-12-14
Publication date: 1992-04-22
Also published as: GB9027194D0; IT9022392A1; FR2668001A1; DE4040046C1; JPH04150411A; IT1244339B; IT9022392A0; KR920009078A; NL9100046A; CN1060724A

Abstract

A double voltage source interface circuit comprises an n channel CMOS transistor (n1) coupled to the output of the circuit by way of a latch circuit (1). The input signal is also coupled to the output by way of an inverter (IVa) and a further n channel transistor (n2). A high level source (VH) is applied to the latch circuit (1), whereas a low level voltage source (VL) is connected to the inverter (IVa). The circuit is able to produce an output switching between a low level and the high level of the voltage source (VH) in response to an input which changes from low level to the lower high level of the voltage source (VL) without an unnecessary dissipation of power. The inverter IVa may be of the type shown at IV1; IV2 in figure 1 (not shown). Depending on whether n1 or n2 conducts in response to input level, the level at P or Q is inverted by IVa or IVb. Spurious conduction affecting output level or state is avoided. <IMAGE>

Description

224 39 ")) A DOUBLE VOLTAGE SOURCE INTERFACE CIRCUIT The present invention

relates to a double voltage source interface circuit.

A double voltage source interface circuit is used, for example, for driving a circuit requiring a high voltage from a source of low voltage in a chip having two kinds of power voltage, for example a low voltage and a high voltage.

A conventional double voltage source interface circuit comprises two inverters, one of which is powered by the low voltage source, and the other of which is powered from the high voltage source. However, with such an arrangement the second inverter may be found to draw power when it should be turned off whereby the overall consumption of power of the circuit is increased. In addition, the output of the second inverter can be turned on, when it ought to be off, thereby providing errors.

The present invention seeks to provide a double voltage source interface circuit in which the disadvantages of the prior art circuits are reduced.

According to the present invention there is provided a double voltage source interface circuit comprising a first inverter coupling an input to an output, and a second inverter coupling the input to the output, and further comprising Latching means coupling said first inverter to the output, and wherein said latching means is arranged to be connected to a first voltage source, and said second inverter is arranged to be coupled to a second voltage source.

Preferably, said first inverter comprises a field i effect transistor whose gate is connected to the input and whose drain- source path is connected to said latching means.

In an embodiment, said second inverter is connected directly to said input and is coupled to said output by way of a third inverter. For example, the third inverter may comprise a field effect transistor.

In a preferred embodiment said first inverter is a first n channel CMOS transistor whose gate is connected to the input and whose drain source path is connected to said latching means, and wherein said latching means is arranged to be connected to a high level voltage source. Said second inverter may be connected directly to said input and is arranged to be connected to a low level voltage source. In this case, the output of said second inverter is preferably connected to the gate of a second n channel CMOS transistor.

For example, said latching means is connected to the drains of said first and second n channel CMOS transistors.

In an embodiment, said latching means comprises two inverters connected in parallel.

The invention also extends to a double voltage source interface circuit comprising n channel CMOS transistor for inputting an input signal to its gate; an inverter for converting the input signal; and a n channel CMOS transistor for inputting the output from the inverter to its gate, wherein a latch circuit having a high voltage source is connected between the drains of the CMOS transistors.

Preferably, the latch circuit is comprised Of two 1 inverters.

Embodiments of the present invention will hereinafter be described, by way of example, with reference to the accompanying drawings in which:

Figure 1 shows the circuit diagram of a known double voltage source interface circuit, Figure 2 shows a general block diagram of a double voltage source interface circuit of the present invention, Figure 3 shows schematically a circuit diagram of the circuit of Figure 2, and - Figures 4A and 4B show the input and output voltages generated at parts of the double voltage source interface circuit as shown in Figures 2 and 3.

Figure 1 shows an example of a conventional double voltage source interface circuit connected to two power sources VL and V H The interface circuit comprises a first inverter IV, and a second inverter IV2. The f irst inverter IV, comprises a p channel CMOS field effect transistor p, whose drain is connected to the voltage source VL The drain-source path of the transistor p, is connected to the drain-source path of a n channel CMOS transistor ni. The gates of the transistors p, and nj are connected to an input to receive an input voltage Vin. The output voltage Vmid of the inverter IV, is taken at the connection of the drain source paths of the two transistors p, and nj and is applied to the gates of similarly arranged p and n channel transistors P2 and n2 forming the second inverter IV2. It will be seen that the drain of the p channel transistor P2 is connected to a high level voltage source VH The output of the interface circuit is taken from the connection between the transistors p2 and nj and it will be seen that a resistor R, forming a current path is connected to the output.

Let us assume that the input voltage Vin changes between a low level of approximately OV and a high level of approximately 3.3V. Let us also assume that the voltage of the source VL is of the order of 3.3V, whereas the voltage of the high level source VH is about 5V.

It will be appreciated that as the voltage Vin applied to the f irst inverter IV, swings between its high and low levels, the output Vmid of the inverter swings correspondingly and also has a low level of about OV and a high level of approximately 3.3V. This voltage output is applied as an input to the inverter IV2. However, because of the level of the voltage of the source VH, when the input Vmid to the inverter IV2 changes between the values of OV and 3.3V, the output of the inverter IV2, which is Vout, swings between OV and 5V.

It will be appreciated that both of the inverters IV, and IV2 operate in the same manner. Thus, when the input voltage is at a low level the n channel transistor nj or n2 is turned of f and the p channel transistor pi or P2 is turned on pulling the ouput Vmid or Vout to the voltage level of the voltage source VL or VH. When the input signal voltage goes high, the p channel transistors pi or P2 are turned off in their turn, the n channel transistors nj or n2 conduct, and the respective output Vmid or Vout is pulled to the low level, for example, to ground. When the output of the f irst inverter IV, is at OV such that the p channel transistor p2 is turned on, a current path through the p channel transistor p2 and the resistor R, is formed.

The voltage on the ouput Vout is at the high level 5V. When the output of the f irst inverter IV, is high, that is 1 at 3.3V, the p channel transistor P2 is turned off, and the n channel transistor n2 is turned on such that the output Vout is low, that is at OV. However, in this case, there is a gate drain voltage across the p channel transistor P2 of approximately 1.7V (5V - 3.3V = 1.7V) and this may be sufficient to turn on the transistor P2 so that current flows by way of the transistor p2 through the resistor R,.

In this case, the consumption of power is increased because there is a current flow when such would not normally be expected. If the resistor R, is not provided, so that there is no current path, the transistor P2 may be fully turned on such that the output voltage Vout becomes high and thereby gives an erroneous output.

Figure 2 shows a general block diagram of a double voltage source interface circuit of the present invention which avoids the problems described above with reference to Figure 1. Figure 3 is a schematic circuit diagram of the circuit of Figure 2 and in particular shows the construction of the latch circuit. The operation of the circuit shown in Figures 2 and 3 will be better understood by reference to Figures 4A and 4B showing input and output wave forms generated by the circuit of the invention.

It will be seen from Figure 2 that the circuit of the invention comprises an input to which the input voltage Vin is applied. First and second inverters ni and IV, are connected to this input. As can be seen, the first inverter is in the form of an n channel CMOS transistor ni having its gate arranged to receive the input Vin and its drain source path connected to a latch circuit 1. The second inverter IVa is also connected directly to the input to receive the input signal Vin. The second inverter IVa may be constructed by any suitable means, but is preferably an inverter of the same type as IV, and IV2 of Figure 1. It will be seen that the low voltage source VL is connected to the second inverter Va whereas the high voltage source % is connected to the latch circuit 1. The output of the latch circuit 1 is connected to the output of the interface circuit at which the voltage Vout appears. The output of the second inverter Va 'S coupled to the output of the circuit by way of a third inverter n2. In the embodiment illustrated this third inverter is a n channel CMOS transistor n2 having its gate connected to the output of the inverter Va and its drain source path connected to the 10 output of the interface circuit.

We shall consider again that the high and low voltage levels for the circuit of Figure 2 are the same as described above with reference to Figure 1. Thus, the low level is approximately OV whereas the high level is either 3.3V, if it emanates from the voltage source VL, Or 5V if supplied from the voltage source VH The input signal Vin can swing between low level and high level, that is between OV and 3.3V, and is applied to the gate of the transistor ni such that the transistor ni is turned of f when Vin is low and turned on when Vin is high. Vin is also applied to the inverter Va such that TME is output and applied to the gate of the transistor n2. It will therefore immediately be appreciated that when transistor nj is turned on, transistor n2 is turned off, and vice versa.

It can be seen from Figure 3 that the latch circuit 1 comprises two inverters IVb and IVc, connected in parallel between nodes P and Q and each connected to the high level voltage source VH' When the input signal Vin changes between a low level and a high level signal, that is between OV and 3.3V, the output signal from node Q of the latch 1 changes between OV and 5V as is indicated in Figures 4A and 4B. Thus, if Vin goes high such that the transistor nj is switched on, the node P goes low and the inverter IVc applies the voltage level of source VH to node Q which thereby goes high. At the same time transistor n2 is turned off such that the high level voltage VH at the node Q is the output Vout.

Similarly, when the input voltage Vin goes low such that transistor nj is switched off, transistor n2 is turned on to put a low level signal on the input to inverter IVb and also to connect Vout to the low level so that Vout also goes low. At this time the node Q will be at OV and thus the inverter IVb connects the voltage level of the source VH to the node P which will thus be at 5V. If then the input signal Vin goes high, so that the transistor nj is turned on and the transistor n2 is turned off, the transistor ni can conduct and thereby pull the node P down to OV. However, it will be appreciated that the current path through Nj is isolated from the output Vout which is switched to the 5V high level.

With the input signal high and Vout similarly high, node Q will be at 5V and node P will be at OV. If Vin then goes low, switching off transistor ni and turning on transistor n2, a current path for the voltage at node Q is formed through the transistor n2 so that the potential of node Q is maintained at OV.

It will be appreciated that the circuit of Figures 2 and 3 acurately brings the voltage at the output of the circuit to the level required, but that there is no current path for dissipating voltage from the high level source % as with the prior art. Accordingly, the unnecessary dissipation of power is reduced.

It will be appreciated that modifications to and developments of the present invention as described and illustrated may be made within the scope of the claims.

-B-

Claims

1. A double voltage source interface circuit comprising a first inverter coupling an input to an output, and a second inverter coupling the input to the output, and further comprising latching means coupling said first inverter to the output, and wherein said latching means is arranged to be connected to a first voltage source, and said second inverter is arranged to be coupled to a second voltage 10 source.

2. A double voltage source interface circuit as claimed in Claim 1, wherein said first inverter comprises a field effect transistor whose gate is connected to the input and whose drain-source path is connected to said latching means.

3. A double voltage source interface circuit as claimed in Claim 1 or 2, wherein said second inverter is connected directly to said input and is coupled to said output by way of a third inverter.

4. A double voltage source interface circuit as claimed in Claim 3, wherein said third inverter comprises a field effect transistor.

5. A double voltage source interface circuit as claimed in any preceding claim, wherein said first inverter is a first n channel CMOS transistor whose gate is connected to the input and whose drain source path is connected to said latching means, and wherein said latching means is arranged to be connected to a high level voltage source.

6. A double voltage source interface circuit as claimed in Claim 5, wherein said second inverter is connected directly to said input and is arranged to be connected to a 1 1 low level voltage source.

7. A double voltage source interface circuit as claimed in Claim 6, wherein the output of said second inverter is connected to the gate of a second n channel CMOS transistor.

8. A double voltage source interface circuit as claimed in Claim 7, wherein said latching means is connected to the drains of said first and second n channel CMOS transistors.

9. A double voltage source interface circuit as claimed in any preceding claim, wherein said latching means comprises two inverters cpnnected in parallel.

10. A double voltage source interface circuit comprising n channel CMOS transistor for inputting an input signal to its gate; an inverter for converting the input signal; and a n channel CMOS transistor for inputting the output from the inverter to its gate, wherein a latch circuit having a high voltage source is connected between the drains of the CMOS transistors.

11. A double voltage source interface circuit as claimed in Claim 10, wherein the latch circuit is comprised of two inverters.

12. A double voltage source interface circuit substantially as hereinbefore described with reference to the accompanying drawings.