GB2247988A - Lead frame for semiconductor device - Google Patents
Lead frame for semiconductor device Download PDFInfo
- Publication number
- GB2247988A GB2247988A GB9119362A GB9119362A GB2247988A GB 2247988 A GB2247988 A GB 2247988A GB 9119362 A GB9119362 A GB 9119362A GB 9119362 A GB9119362 A GB 9119362A GB 2247988 A GB2247988 A GB 2247988A
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- Prior art keywords
- semi
- leads
- lead frame
- inner leads
- thickness
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49558—Insulating layers on lead frames, e.g. bridging members
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
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- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
The present invention provides a semiconductor device comprising a lead frame having integrally formed inner and outer leads, the inner loads (23) being thinner than the outer leads (24), an insulator substrate (25) to which the inner leads and pants of the outer leads are adhered, a semi-conductor element (26) connected to the inner leads, and a package (28) in which the semiconductor element, the insulator substrate, the inner leads and parts of the outer leads are sealed. <IMAGE>
Description
SEMI-CONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME
This invention relates to semi-conductor devices
and their production. More particularly, the invention
relates to semi-conductor packages and their production.
A conventional semi-conductor device, in which a
known wire bonding method is employed, is shown in figure 6 and figure 7.
As shown in these figures, the semi-conductor
device comprises a lead frame 1. In the centre of the
lead frame, a die pad 2 is supported by support arms 3.
A plurality of inner leads 4 project from the lead frame
1 towards the centre, and their ends are positioned
opposite and around the die pad 2 at a prescribed
distance from the die pad 2. A semi-conductor element 5
is attached with an adhesive to the top of the die pad
2, and each of a plurality of bonding pads of the semi
conductor element 5 is connected to a corresponding
inner lead 4 by a wire.
The semi-conductor element 5, connected to a
plurality of the inner leads 4 as described above, is
sealed in a plastics material, comprising an epoxy
resin, together with the inner leads 4 and the die pad 2
to form a package 8, leavina parts of the outer leads 7
exposed. The outer leads 7 projecting from the package
8 are bent and used as terminals, whereby a wire bonding
type of semi-conductor is produced.
Another conventional semi-conductor device, in
which a known TAB method is employed, is shown in figure
8. In this device, the semi-conductor element 5 is
positioned in a hole in a film carrier 10, and fingers
11 on the film carrier 10 are connected to respective
bonding pads on the semi-conductor element 5. The semi
conductor element 5 and parts of the fingers 11 are sealed in a plastics material 12, comprising an epoxy resin, whereby a TAB type of semi-conductor device is produced.
In the prior art wire bonding and TAB types of semi-conductor device, such as those described above, the inner leads 4 of the lead frame 1 and of the fingers 11 on the film carrier 10 are designed and manufactured to conform with the size of the semi-conductor element, the arrangement of the bonding pads and other such factors.
However, as recent electronic devices become more compact and thinner, it is necessary, in order to realise packages with many pins, to make the interval between the inner leads narrower and to increase the number of inner leads. However, in the prior art while bonding semi-conductor devices, the thickness of the outer leads 7 and inner leads 4 of the lead frame 1 is the same, and they cannot be made narrower by etching or pressing. Currently, the interval between the inner leads 4 when the lead frame 1 has a plate thickness of 150 pm, can only be as narrow as 250 pm. Therefore, it is difficult to realise an increase in the number of pins, by narrowing the pitch interval and increasing the number of inner leads 4, while the leaving the lead frame 1 the same thickness. Further, in the TAB method, the thickness of the fingers 11 is 30 pm to 50 pm and so they are lacking in strength.
In the wire bonding type of semi-conductor device, the inner leads 4 must be arranged in a radial pattern with respect to the semi-conductor element 5 in order to achieve a sufficient pitch interval between the inner leads 4, thus increasing the distance between the semiconductor element 5 and the ends of the inner leads 4 and resulting in longer wires 6 that tend to hang down.
Hence, when the semi-conductor element 5 and the inner leads 4 are sealed in the package 8, the wires tend to move, which increases the risk of edge short-circuiting between the hanging wires 6.
The invention at least in its preferred form seeks to solve these problems and to realise a semi-conductor device, with a low cost production method, that is capable of increasing the number of pins in a package whilst preventing edge short-circuiting.
Although the present invention is primarily directed to any novel integer or step, or combination of integers or steps, herein disclosed and/or as shown in the accompanying drawings, nevertheless, according to one particular aspect of the present invention to which, however, the invention is in no way restricted, there is provided the invention comprising a semi-conductor device comprising a lead frame having integrally formed inner and outer leads, wherein the inner leads are thinner than the outer leads, an insulator substrate to which the inner leads and parts of the outer leads are adhered, a semi-conductor element connected to the inner leads, and a package in which the semi-conductor element, the insulator substrate, the inner leads and parts of the outer leads are sealed.
According to another aspect of the present invention, there is provided a method of producing a semi-conductor device including the steps of adhering an insulator substrate on a lead frame plate, half-etching an inner lead area in an inner region of the lead frame plate, forming outer leads outside the inner lead area, etching the inner lead area to produce inner leads, connecting a semi-conductor element to the inner leads, and sealing the semi-conductor element, the insulator substrate, the inner leads and part of the outer leads in a package.
In a wire bonding type of semi-conductor device according to the invention, the inner leads of the lead frame are preferably formed with a thickness one-fifth to one-third the thickness of the outer leads. The thickness of the outer leads may be maintained, thus preserving their strength, while the inner leads and their pitch interval can be made narrower, thus making it possible to increase the number of inner leads.
Further, when during production the thin inner leads attached to the insulator substrate and the bonding pads of the semi-conductor element attached to a die pad are connected by wires, the inner leads are reinforced by the insulator substrate, thus preventing them from becoming loose during the connection of the wires and facilitating a smooth, reliable connection of the wires.
In a TAB type of semi-conductor device according to the invention, the inner leads of fingers on a film carrier are preferably formed so that they are one-fifth to one-third as thick as the outer leads. The inner leads and their pitch interval can thus be made narrower, while maintaining the strength of the outer leads, making it possible to increase the nurwer of inner leads. Also, when the bonding pads of the semiconductor element are connected to the thin inner leads adhered to the insulator substrate during production, the inner leads are reinforced by the insulator substrate and do not move during the connection step, and therefore the connections to the semi-conductor chip can be effected smoothly and reliably.
Wire bonding type of semi-conductor devices according to the invention may conveniently be produced by half-etching an inner lead area in the centre of the top surface of the lead frame plate, having a thickness one-fifth to one-third the thickness of the lead frame plate, then etching the outer leads in the area outside the inner lead area of the lead frame plate.
A die pad in the centre of the inner lead area and inner leads around the centre, whose thickness is onefifth to one-third the thickness of the outer leads, may then be etched before fixing the semi-conductor element on top of the die pad, connecting the bonding pads of the semi-conductor element and the inner leads by wires, and sealing the semi-conductor element, the insulator substrate, the inner leads and parts of the outer leads in a sealing material.
A large number of inner leads with a narrow pitch interval can thus be achieved at a low cost since the strength of the inner leads, which are thinner than the outer leads, is reinforced by the insulator substrate, and since it is possible to perform micro-processing to make the inner leads narrower using conventional etching processes.
In an alternative process, the outer leads formed in the area outside the inner lead area of the lead frame plate may be formed by pressing, whereby the production time may be shortened and lower production costs may be obtained than when using an etching process.
The invention is described further, by way of example, with reference to the accompanying drawings, in which:
Figure 1 is a cross-section through a wire bonding type of semi-conductor device according to the invention;
Figure 2 is a fragmentary perspective view showing the principle parts of the semi-conductor device;
Figures 3a to 3e are explanatory diagrams illustrating the production process for a lead frame of the semi-conductor device;
Figures 4a to 4e are explanatory diagrams illustrating another production process for the same lead frames;
Figure 5 is a cross-section through a TAB type of semi-conductor device according to the invention;
Figure 6 is a perspective view, partially cut away, of a prior art wire bonding type of semi-conductor device;
Figure 7 is a fragmentary perspective view of the principle parts of the semi-conductor device of figure 6; and
Figure 8 is a cross-section through a prior art
TAB type of semi-conductor device.
Figure 1 is a cross-section through a wire bonding type of semi-conductor device according to the invention, and figure 2 is a fragmentary perspective view showing the principle parts of the same semiconductor device.
The semi-conductor device has a lead frame 21, in the centre of which is a die pad 22 adhered to an insulator substrate 25. A plurality of inner leads 23 project from the lead frame 21 towards the centre, and their ends are positioned around and opposite the die pad at a prescribed distance from the die pad 22. Outer leads 24 are integral with the inner leads 23, but the inner leads 23 are thinner than the outer leads 24, being the same thickness as che die pad 22.
In this embodiment of the invention, the inner leads 23 are formed to a thickness of 30 pm to 50 pm, which is much thinner than the 150 pm thickness of the outer leads. Therefore, the width of the ends of the inner leads 23 is 30 pm to 50 pm, and their pitch interval is 50 pm to 100 pm. A surface 23a of the ends of the inner leads 23 is silver plated.
The die pad 22, parts of the outer leads 24, and the inner leads 23 are mounted on the insulator substrate 25 and adhered thereto. A semi-conductor element 26 is attached on top of the die pad 22 with adhesive, and bonding pads of the semi-conductor element 26 and corresponding inner leads 23 are connected with wires 27. Since the inner leads 23 are adhered to the insulator substrate 25, their strength is reinforced, and, when the wires 27 are connected to the inner leads 23, the inner leads 23 do not move so that the wiring connection can be performed smoothly and reliably.
The semi-conductor element 26, that has been connected to a plurality of the inner leads 23 in this manner, is sealed in a plastics package, made from an epoxy resin, together with the inner leads 23, the die pad 22 and the insulator substrate 25, so that parts of the outer leads 24 are left exposed. Following this, the outer leads 24 projecting from the package 28 are bent and their ends are used as terminals, whereby a wiring bonding type of semi-conductor device is produced.
The number of inner leads 23 of the semi-conductor device according to the invention can be increased because the pitch interval of the inner leads 23 is reduced to 50 pm to 100 pm, by comparison with 250 pm in the prior art, even though the outer leads 24 are the same thickness as in the prior art. Therefore, packages 28, in which the number of pins is increased from 200 in the case of the prior art to 400, can be realised for the wire bonding type of semi-conductor device.
Further, since the ends of the inner leads 23 can be brought closer to the semi-conductor element 26, the wires 27 can be made shorter, thus preventing them from hanging down and preventing edge short-circuiting between wires 27 when the semi-conductor element etc. is sealed in the package 28.
Next, the method for the production of the semiconductor device will be explained with reference to figures 3a to 3e.
Figures 3a to 3e show the production process for the lead frame 21 of the wire bonding type of semiconductor device according to the invention. First, a square, 150 pm thick, plate 29 is formed from a suitable lead frame material, such as copper or 4-2 alloy (figure 3a). The insulator substrate 25, which is made from an insulating material, such as polyimide, glass epoxy and ceramic, is adhered with an adhesive to the centre of a bottom surface of the plate 29 as shown in figure 3b.
Next, as shown in figure 3c, a 30 pm to 50 pm thick inner lead area 30 is half-etched in the centre of the top surface of the lead frame plate 29. The insulator substrate 25 can alternatively be attached after the inner lead area 30 is formed in the lead frame plate 29.
Next, as shown in figure 3d, the outer leads 24 are etched in a peripheral area outside the inner lead area 30 of the lead frame plate 29. Then, as shown in figure 3e, etching is again performed to form both the die pad 22 in the centre of the inner lead area 30 and the inner leads 23 around the centre to a thickness of 30 pm to 50 pm. In this way, the lead frame 21 is formed with both outer leads and inner leads and the insulator plate 25 attached to it and with the inner leads one-fifth to one-third as thick as the outer leads.
By making the inner leads 23 thinner than the outer leads and by reinforcing the inner leads 23 with the insulator substrate as described above, it becomes possible to perform micro-processing using conventional etching processes, in such a way as to make the inner leads 23 narrower and to achieve a large number of inner leads 23 without increased cost.
The semi-conductor element 26 is subsequently adhered to the top of the die pad 22 on the lead frame 21, the bonding pads of the semi-conductor element 26 and the inner leads 23 are connected by the wires 27 and the semi-conductor element 26, the insulator substrate 25, the inner leads 23 and parts of the outer leads 24 are sealed in the package 28 made from a sealing material, which is an epoxy resin. The outer leads 24 projecting from the package 28 are then bent and used as terminals, whereby the wire bonding type of semiconductor device is produced.
Figures 4a to 4e show another production process for the lead frame 21 of the wire bonding type of semiconductor device, the main difference relative to the production process shown in figures 3a to 3e being that the outer leads 24 are not etched in the area outside the inner lead area 30 of the lead frame plate 29, but rather they are formed by pressing. The pressing process shortens production time and reduces costs as compared with the etching process.
Figure 5 is a cross-section through a TAB type of semi-conductor device according to another embodiment of the invention. In this embodiment inner leads 42 of a lead frame 41 are formed to a thickness of 30 sum to 50 pm, which is much thinner than a 150 pm thickness of outer leads 43. Therefore, the ends of the inner leads 42 become 30 pm to 50 pm wide, and the pitch interval of
the inner leads 42 is 50 pm to 100 pm. The inner leads
42 and parts of the outer leads 43 are mounted on and
adhered to an insulator substrate 44. Each of the inner
leads 42 of the lead frame 41 is connected to a
corresponding bonding pad of the semi-conductor element
26.And the semi-conductor element 26, the insulator
substrate 24, the inner leads 42 and parts of the outer leads lead 43 are sealed in a package 45 made from epoxy
resin. The outer leads 43 projecting from the package
45 are bent and used as terminals, whereby the TAB type
of semi-conductor device is produced.
In this semi-conductor device, the pitch interval
of the inner leads 42 of the lead frame 41 is reduced
from 250 pm in the case of the prior art to 50 pm to
100 pm, while the thickness of the outer leads 43
remains the same as in the prior art, thus making it
possible to increase the number of inner leads 42 and
realise a TAB type of semi-conductor device with an
increased number of pins.
As described above, the inner leads of the lead
frame in the wire bonding type of semi-conductor device
according to the invention are formed to be one-fifth to
one-third as thick as the outer leads, while the
thickness of the outer leads is kept the same as in the
prior art and their strength is maintained. Therefore,
the inner leads and their pitch interval can be made
narrower and the number of inner leads can be increased
for realising a package with many pins.
Further, by bringing the ends of the inner leads
closer to the semi-conductor element, the wires in a
wire bonding type of semi-conductor device can be made
shorter, thus preventing sag in the wires and avoiding
edge short-circuiting during sealing. Also, during
connection of the thin inner leads adhered to the insulator substrate and the bonding pads of the semiconductor element adhered on top of the die pad with wires, the inner leads are reinforced by the insulator substrate, which prevents them from moving, thus facilitating smooth and reliable connection of the wires.
The semi-conductor device of the invention may be produced by half etching an inner lead area in the centre of the top surface of the lead frame plate to have a thickness one-fifth to one-third the thickness of the lead frame plate. This may be effected after adhering the insulator substrate to the centre of the bottom surface of the lead frame plate, or before adhering the insulator substrate to the centre of the bottom surface of the lead frame plate. Next, outer leads are etched in the area outside the inner lead area of the lead frame plate, and the die pad is etched in the centre of the inner lead area together with inner leads around the centre whose thickness is one-fifth to one-third the thickness of the outer leads.Therefore, the strength of the inner leads, which are thinner than the outer leads, can be reinforced by the insulator substrate, and it becomes possible to perform micro-processing by a conventional etching process to make the inner leads narrower, whereby a large number of inner leads can be achieved without great cost. Further, by forming the outer leads in the area outside the inner lead area of the lead frame plate by pressing, production time may be shortened and production costs may be lower than by using an etching process.
In the TAB type of semi-conductor device according to the invention, the inner leads of the fingers on the film carrier are formed to be one-fifth to one-third as thick as the outer leads, and therefore the inner leads can be made narrower while keeping the outer leads as thick as in the case of the prior art and maintaining their strength. Thus, it is possible to increase the number of inner leads by reducing the pitch interval of the inner leads and to realise a package with many pins.
Also, when the bonding pads of the semi-conductor element are connected directly to the thin inner leads adhered to the insulator substrate, the inner leads are reinforced by the insulator substrate thus preventing them from moving during the connection and facilitating smooth, reliable connection to the semi-conductor chip.
Claims (19)
1. A semi-conductor device comprising a lead frame having integrally formed inner and outer leads, wherein the inner leads are thinner than the outer leads, an insulator substrate to which the inner leads and parts of the outer leads are adhered, a semi-conductor element connected to the inner leads, and a package in which the semi-conductor element, the insulator substrate, the inner leads and parts of the outer leads are sealed.
2. A device as claimed in claim 1 in which the thickness of the inner leads is one-fifth to one-third the thickness of the outer leads.
3. A device as claimed in claim 1 or 2 of the wire bonding type including a die pad, which is adhered to the insulator substrate and on which the semi-conductor element is fixed, and wires connecting bonding pads of the semi-conductor element to the inner leads.
4. A device as claimed in claim 3 in which the thickness of the die pad is the same as the thickness of the inner leads.
5. A semi-conductor device as claimed in claim 1 in which the thickness of the inner leads is one-third to one-half the thickness of the outer leads.
6. A device as claimed in claim 1 or 5 of the TAB type in which bonding pads of the semi-conductor element are connected directly to the inner leads.
7. A method of producing a semi-conductor device including the steps of adhering an insulator substrate on a lead frame plate, half-etching an inner lead area in an inner region of the lead frame plate, forming outer leads outside the inner lead area, etching the inner lead area to produce inner leads, connecting a semi-conductor element to the inner leads, and sealing the semi-conductor element, the insulator substrate, the inner leads and part of the outer leads in a package.
8. A method as claimed in claim 7 in which the step of half-etching comprises etching the inner lead area such that its thickness becomes one-fifth to one-third the thickness of the lead frame plate.
9. A method as claimed in claim 7 or 8 in which the step of adhering comprises adhering the insulator substrate to the lead frame plate after the step of half-etching.
10. A method as claimed in any of claims 7 to 9 in which the step of forming the outer leads comprises an etching step.
11. A method as claimed in any of claims 7 to 9 in which the step of forming the outer leads comprises a pressing step.
12. A method as claimed in any of claims 7 to 11 further comprising the step of etching a die pad in the centre of the inner lead area.
13. A semi-conductor device substantially as herein particularly described with reference to and as illustrated in figures 1 and 2, or figures 1 and 2 when modified by figure 5, of the accompanying drawings.
14. A method of producing a semi-conductor device substantially as herein particularly described with reference to and as illustrated in figure 3 or figure 4 of the accompanying drawings.
15. A semi-conductor device comprising inner leads whose thickness is one-fifth to one-third the thickness of the outer leads in a lead frame, a die pad of the same thickness as the inner leads in the lead frame, an insulator substrate to which is adhered the die pad, part of the outer leads and the inner leads, a semi conductor element fixed on top of the die pad, wires connecting the bonding pads of the semi-conductor element and the inner leads, and a package in which is sealed the semi-conductor element, the insulator substrate, part of the outer leads and the inner leads.
16. A semi-conductor device comprising inner leads whose thickness is one-third to one-half the thickness of the outer leads in the fingers of the film carrier, an insulator substrate to which is adhered part of the outer leads of the fingers and the inner leads, a semiconductor element whose bonding pads are connected to the inner leads, and a package in which is sealed the semi-conductor element, the insulator substrate, part of the outer leads the inner leads.
17. A semi-conductor device production method that produces semi-conductor devices by half-etching an inner lead area in the centre of the top surface of the lead frame material plate whose thickness is one-fifth to one-third the thickness of the lead frame material plate after adhering the insulator substrate to the centre of the bottom surface of the lead frame material plate, or by adhering the insulator substrate to the centre of the bottom surface of the lead frame material plate after forming the inner lead area in the top surface of the lead frame material plate, then etching outer leads in the area outside the inner lead area of the lead frame material plate, etching die pads in the centre of the inner lead area and inner leads around the centre whose thickness is one-fifth to one-third the thickness of the outer leads, fixing the semi-conductor element on top of the die pad, connecting the die pads of the semiconductor element and the inner leads with wires, and sealing the semi-conductor element, insulator substrate, part of the outer leads and the inner leads in a sealing material.
18. A semi-conductor device production method that produces semi-conductor devices by half-etching an inner lead area in the centre of the top surface of the lead frame material plate whose thickness is one-fifth to one-third the thickness of the lead frame material plate after adhering the insulator substrate to the centre of the bottom surface of the lead frame material plate, then forming outer leads by pressing the area outside the inner lead area of the lead frame material plate together with the insulator substrate, etching die pads in the centre of the inner lead area and inner leads around the centre whose thickness is one-fifth to onethird the thickness of the outer leads, fixing the semiconductor element on top of the die pad, connecting the bonding pads of the semi-conductor element and the inner leads with wires, and sealing the semi conductor element, the insulator substrate, part of the outer leads and the inner leads in a sealing material.
19. Any novel integer or step, or combination of integers or steps, hereinbefore described and/or as shown in the accompanying drawings, irrespective of whether the present claim is within the scope of or relates to the same, or a different, invention from that of the preceding claims.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2240161A JPH04120765A (en) | 1990-09-12 | 1990-09-12 | Semiconductor device and manufacture thereof |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9119362D0 GB9119362D0 (en) | 1991-10-23 |
| GB2247988A true GB2247988A (en) | 1992-03-18 |
| GB2247988B GB2247988B (en) | 1995-03-29 |
Family
ID=17055406
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9119362A Expired - Fee Related GB2247988B (en) | 1990-09-12 | 1991-09-11 | Semi-conductor device and method of producing the same |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPH04120765A (en) |
| KR (1) | KR970000219B1 (en) |
| GB (1) | GB2247988B (en) |
| HK (1) | HK101497A (en) |
| TW (1) | TW198767B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6153922A (en) * | 1997-08-25 | 2000-11-28 | Hitachi, Ltd. | Semiconductor device |
| US7102216B1 (en) * | 2001-08-17 | 2006-09-05 | Amkor Technology, Inc. | Semiconductor package and leadframe with horizontal leads spaced in the vertical direction and method of making |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2550900B2 (en) * | 1993-11-18 | 1996-11-06 | 日本電気株式会社 | Semiconductor device |
| JP3506341B2 (en) * | 1994-06-28 | 2004-03-15 | 株式会社ルネサステクノロジ | Semiconductor device |
| US5929513A (en) * | 1994-08-16 | 1999-07-27 | Fujitsu Limited | Semiconductor device and heat sink used therein |
| US5834831A (en) * | 1994-08-16 | 1998-11-10 | Fujitsu Limited | Semiconductor device with improved heat dissipation efficiency |
| KR0156622B1 (en) * | 1995-04-27 | 1998-10-15 | 문정환 | Semiconductor leadframe and the manufacturing method |
| US5796158A (en) * | 1995-07-31 | 1998-08-18 | Micron Technology, Inc. | Lead frame coining for semiconductor devices |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3711625A (en) * | 1971-03-31 | 1973-01-16 | Microsystems Int Ltd | Plastic support means for lead frame ends |
| GB1458846A (en) * | 1973-12-03 | 1976-12-15 | Raytheon Co | Semiconductor packages |
| EP0063408A1 (en) * | 1981-03-27 | 1982-10-27 | AMP INCORPORATED (a New Jersey corporation) | Semiconductor chip carrier |
| GB2178895A (en) * | 1985-08-06 | 1987-02-18 | Gen Electric Co Plc | Improved preparation of fragile devices |
| GB2178894A (en) * | 1985-08-06 | 1987-02-18 | Gen Electric Co Plc | Preparation of fragile devices such as lead frames |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0405330A3 (en) * | 1989-06-29 | 1992-05-06 | Motorola, Inc. | Flagless leadframe, package and method |
-
1990
- 1990-09-12 JP JP2240161A patent/JPH04120765A/en active Pending
-
1991
- 1991-09-05 TW TW080107045A patent/TW198767B/zh active
- 1991-09-06 KR KR1019910015564A patent/KR970000219B1/en not_active IP Right Cessation
- 1991-09-11 GB GB9119362A patent/GB2247988B/en not_active Expired - Fee Related
-
1997
- 1997-06-26 HK HK101497A patent/HK101497A/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3711625A (en) * | 1971-03-31 | 1973-01-16 | Microsystems Int Ltd | Plastic support means for lead frame ends |
| GB1458846A (en) * | 1973-12-03 | 1976-12-15 | Raytheon Co | Semiconductor packages |
| EP0063408A1 (en) * | 1981-03-27 | 1982-10-27 | AMP INCORPORATED (a New Jersey corporation) | Semiconductor chip carrier |
| GB2178895A (en) * | 1985-08-06 | 1987-02-18 | Gen Electric Co Plc | Improved preparation of fragile devices |
| GB2178894A (en) * | 1985-08-06 | 1987-02-18 | Gen Electric Co Plc | Preparation of fragile devices such as lead frames |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6153922A (en) * | 1997-08-25 | 2000-11-28 | Hitachi, Ltd. | Semiconductor device |
| US6285074B2 (en) | 1997-08-25 | 2001-09-04 | Hitachi, Ltd. | Semiconductor device |
| US6297545B1 (en) | 1997-08-25 | 2001-10-02 | Hitachi, Ltd. | Semiconductor device |
| US7102216B1 (en) * | 2001-08-17 | 2006-09-05 | Amkor Technology, Inc. | Semiconductor package and leadframe with horizontal leads spaced in the vertical direction and method of making |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04120765A (en) | 1992-04-21 |
| HK101497A (en) | 1997-08-15 |
| GB9119362D0 (en) | 1991-10-23 |
| KR920007155A (en) | 1992-04-28 |
| GB2247988B (en) | 1995-03-29 |
| KR970000219B1 (en) | 1997-01-06 |
| TW198767B (en) | 1993-01-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20080911 |