GB2244183A

GB2244183A - Control circuit for a solid state switching device

Info

Publication number: GB2244183A
Application number: GB9010986A
Authority: GB
Inventors: Brian Peter Rogers
Original assignee: Plessey Aerospace Ltd
Current assignee: Plessey Aerospace Ltd
Priority date: 1990-05-16
Filing date: 1990-05-16
Publication date: 1991-11-20
Anticipated expiration: 2010-05-16
Also published as: GB9010986D0; GB2244183B

Abstract

Solid state switching devices have the ability to switch off very rapidly when fault currents are detected. However, in certain circumstances the slower circuit breaker characteristic can be advantageous by avoiding unwanted switch off during short power surges or momentary overloads. A sample of monitored current is supplied 2 to an analogue comparator and logic circuit 1, which provides a digital sample to multiplexer 3. If no overload is detected, logic 1a causes the multiplexer to select a fixed input B0-B5 as output to a divider 4 so that a counter 5 counts down to zero at a fixed rate and switching device 7 is held on. Excessive current turns off the device 7 immediately. Moderate overloads cause multiplexer 3 to select the sample input A0-A5 to control divider 4 which controls the up count rate of counter 5 until a turn-off level is reached or the overload ceases and count down is resumed. <IMAGE>

Description

A Control Circuit for a Solid State Switching Device The present invention relates to a control circuit for a solid state switching device, and may find utility in power control systems.

Solid state switching devices offer many improvements over conventional circuit breakers, particularly the ability to switch off very rapidly when fault currents are detected.

Such switch off times are measured in micro-seconds compared to many milliseconds for a conventional circuit breaker.

However, in certain circumstances the slower circuit breaker characteristic can be advantageous by avoiding unwanted switch-off during short power surges or momentary overloads, which may occur in motor circuits for example.

The control circuit in accordance with the present invention, provides a digital emulator of the circuit breaker characteristic, say to 400% of its rated current, whilst retaining the fast fault isolation of higher (e.g. short circuit) fault currents.

According to the present invention, there is provided a control circuit for a solid state switching device, the control circuit comprising an analogue comparator and logic means having an input line arranged to receive an analogue voltage which is proportional to input current, and a plurality of output lines connected to a multiplexer and upon which a selectable digital sample of the input current is generated, the multiplexer further being provided with a number of input lines which are tied to electrical inputs to represent a fixed digital sample, the multiplexer is controlled by the logic means to select the fixed digital sample or the samples generated by the analogue comparator, and the multiplexer is connected to a programmable divider which receives a fixed frequency signal and generates an output frequency signal in dependence upon the signals received from the multiplexer, said programmable divider is connected to a clock input of a counter which is controlled by the logic means and provides an output signal which is presented to the solid state switching device and is arranged to switch said device off when an over current is detected by the control circuit.

The present invention has the advantage of selecting when the solid state switching device is switched off in accordance with the digital samples presented by the multiplexer to the parallel inputs of the programmable divider circuit.

An embodiment of the present invention will now be described with reference to the accompanying drawings in which, Figure 1 shows a schematic circuit diagram of the control circuit connected to a solid state switching device; and Figure 2 shows a table of typical values representing selectable current levels, the comparator output samples for the respective current level, the divide ratio, and the switch off time for the solid state switching device.

Referring to Figure 1, an analogue comparator 1 and logic means la is shown. The analogue comparator receives an analogue input voltage which is proportional to the input current I on the input line 2. The analogue comparator converts the analogue voltage into a set of selectable digital output samples which control the over current operation. The selected sample generated by the analogue comparator 1 is fed to the inputs aO to a5 of a 2 to 1 multiplexer 3. The multiplexer 3 also has a number of inputs b0 to b5 which are connected to the power supply to generate a fixed digital sample. The inputs bo b1 b2 and b5 are connected to a positive voltage supply and the inputs b3 and b4 are connected to ground.A multiplexer 3 is used to provide the inputs to a programmable divider 4, and are selectable by a "no overload" signal which is generated by the logic circuit la. When the "no overload" signal is present the input b0 to b5 are selected and when an overload situation is present the inputs aO to aS are selected.

The programmable divider 4 is connected to a fixed frequency oscillator Fosc and the frequency used is 262 KHz, for example. The divider circuit 4 divides the input frequency (Fosc) by a ratio determined by the sample presented to its programmable inputs. An output frequency Fout is generated and is passed to a clock input of a binary counter circuit 5. The up/down counter 5 has its up/down control determined by the logic circuit la, and is arranged such that when it reaches its maximum value, the solid state switching device 7 is set to an off state, and when it reaches a minimum value the solid state switching device 7 assumes a hold state.

A reset and zero hold circuit 6 is provided which receives as an input, the output of the solid state switching device 7, as a further input it receives the minimum count value from the up down counter 5, and it also receives as an input, the "no overload" signal from the logic circuit la.

The output of the reset and zero hold circuit 6 is used to reset the up/down counter 5 and hold it in a zero condition.

In the normal operating state of the control circuit, the "no overload" output from the logic circuit la will be active. The up/down counter 5 will be on hold at zero count by virtue of the state of the reset and zero hold circuit 6, and the hold circuit will be stable. Reference should now be made to Figure 2 which shows the selectable current levels between 100% and 400%, together with the selectable comparator output samples, the divide ratio and the switch-off (trip) time.

If the analogue input voltage reaches a level representing a limited overload condition (i.e. current between 100% and 400% rated value), the no overload output becomes inactive. This will select the inputs aO to a5 of the multiplexer 3, and the selected input sample will be presented to the parallel inputs of the programmable divider 4. The up/down counter 5 will have its up down input set to the count up mode. The count frequency will be derived from the programmable divider. The over-current level will determine the output frequency of the divider, and hence the time to generate the "trip" signal.

Once the "trip" signal is generated, the circuit is reset by the reset and hold circuit 6. An external reset is required to re-enable the solid state switching device 7.

If the overload is cleared before the "trip" signal is generated, the "no overload" signal again becomes active, selecting the inputs bo to b5 of the multiplexer 3. These inputs are applied to the programmable divider 4 and the up/down counter 5 is set to counter down mode of operation.

The counter 5 will then count down at a fixed slow rate until the initial zero condition is reached. This is analogous to the cooling period of a thermally operated circuit breaker.

In the event of an excessive overload condition being recognised (i.e. a current in excess of 400% of the rated value) the "trip" output is generated instantly, by-passing the counter circuits. The logic circuit la generates an excess current signal which is directly applied to an input of the solid state switching device 7 and causes the device 7 to immediately trip to the off state.

It will be appreciated that the elements used to perform the invention are of conventional type and their use and operation is well known to those skilled in the art.

The above description has been of one embodiment of the present invention, and it will readily be appreciated by those skilled in the art that alternative arrangements can be used within the spirit and scope of the present invention.

For example a different frequency value for Fosc may be used. The binary up/down counter is shown having 16 bits whereas a different number of bits may be used. Furthermore, the digital implementation of the present invention allows the control circuit to be embodied in ASIC chip technology and may form part of larger circuit elements.

Claims

1. A control circuit for a solid switching device, the control circuit comprising an analogue comparator and logic means having an input line arranged to receive an analogue voltage which is proportional to input current, and a plurality of output lines connected to a multiplexer and upon which a selectable digital sample of the input current is generated, the multiplexer further being provided with a number of input lines which are tied to electrical inputs to represent a fixed digital sample, the multiplexer is controlled by the logic means to select the fixed digital sample or the samples generated by the analogue comparator, and the multiplexer is connected to a programmable divider which receives a fixed frequency signal and generates an output frequency signal in dependence upon the signals received from the multiplexer, said programmable divider is connected to a clock input of a counter which is controlled by the logic means and provides an output signal which is presented to the solid state switching device and is arranged to switch said device off when an over current is detected by the control circuit.

2. A control circuit as claimed in claim 1, wherein the counter its an up/down counter.

3. A control circuit as claimed in claim 2, wherein a reset and zero hold circuit is connected to the logic means and the up/down counter to hold the counter at a zero count, while under no-overload conditions, preventing the solid state switching device from switching off.

4. A control circuit as claimed in claim 3, wherein the analogue comparator is arranged to provide a selectable digital sample for various overload conditions between 100% and 400% of a rated maximum no overload condition.

5. A control circuit as claimed in claim 5, wherein the logic means is provided with an output directly connected to an input of the solid state switching device thereby by-passing the counter, and is arranged to generate a signal when a current in excess of 400% is determined, said signal being applied to the input of the solid state switching device to instantly switch said device off.

6. A control circuit substantially as hereinbefore described.

7. A control circuit substantially as hereinbefore described with reference to Figures 1 and 2 of the accompanying drawings.