GB2243485A - Semiconductor device contact pads - Google Patents

Semiconductor device contact pads Download PDF

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Publication number
GB2243485A
GB2243485A GB9009500A GB9009500A GB2243485A GB 2243485 A GB2243485 A GB 2243485A GB 9009500 A GB9009500 A GB 9009500A GB 9009500 A GB9009500 A GB 9009500A GB 2243485 A GB2243485 A GB 2243485A
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United Kingdom
Prior art keywords
pad
connection site
region
semi
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB9009500A
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GB9009500D0 (en
Inventor
Manfred Paul
Allen Wagner
Ray Sundstrom
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Germany GmbH
Original Assignee
Motorola GmbH
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Filing date
Publication date
Application filed by Motorola GmbH filed Critical Motorola GmbH
Priority to GB9009500A priority Critical patent/GB2243485A/en
Publication of GB9009500D0 publication Critical patent/GB9009500D0/en
Publication of GB2243485A publication Critical patent/GB2243485A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance

Abstract

In order to reduce the effect of the stray capacitance associated with a contact pad formed on an insulating layer 15 of an integrated circuit a region 20 of opposite conductivity type to the surrounding epitaxial region 16 is formed immediately below the contact pad 11. This region 20 floats electrically and the capacitance C22 associated with the junction appears in series with that (C101) between the pad 11, (12) and the semiconductor. The pad 11 may be connected by the track 12 to an input protection circuit including a diffused resistor 23. The floating zone 20 may be produced at the same time as resistor 23. <IMAGE>

Description

IMPROVEMENTS IN OR RELATING TO INTEGRATED CIRCUIT CONNECTION SITES The present invention relates to semi-conductor integrated circuits and in particular to the formation of sites suitable for external connections to such devices, such that parasitic capacitance associated with such sites is reduced.
In an integrated circuit devices, formed in the semi-conductor material by various selective diffusion and implantation processes to create co-operating regions of p-type and n-type semi-conductor, may be interconnected by metal tracks running on the surface of the semi-conductor and selectively insulated therefrom. The tracks are laid by well known metalisation processes and for a typical circuit several mutually insulated metalisations giving rise to a layered track pattern may be necessary to establish the required interconnection pattern. An external (i.e. circuit input or output) connection may be made by laying track to an area allocated for the purpose where an extended region of metalisation is formed to provide a connection site, such a site is referred to in the art as a pad.The external connection itself may be made for example by bonding a wire between the pad and a connection pin of the package that is to contain the circuit.
Since the pad is formed on the surface of the semi-conductor material and is insulated from it a capacitor structure is formed by sandwiches an insulator between the conductive metal and semiconductor material; hence a parasitic capacitance is inevitably associated with each pad. It is generally desirable that parasitic capacitance be as low as possible since it degrades circuit performance, parasitism taking greater effect as circuit operating speed is increased and being of particular importance in very high speed circuits such as those of the emitter coupled logic families.
The loading of an emitter coupled logic gate by the parasitic capacitance for example reduces the total number of other gates that can be driven as well as adversely affecting the propagation delay through the gate due to the charging or discharging of the parasitic capacitance as the gate changes state.
The parasitic capacitance associated with a metalised track is proportional to the surface area of the track and as such can be reduced by good design practices which reduce track length and size to the minimum possible. Equally, pad capacitance is reduced if pad area is decreased. Unfortunately, several factor militate against a reduction in pad area. The tolerance of positioning the bond wire is eased if a large pad is employed and a more robust bond is produced with a large area pad. Indeed, with moves to increase quality and reliability it is likely that pad size would be increased rather than decreased compounding the problem of parasitic capacitance.
It is well known that semi-conductor devices can be damaged or destroyed by electro-static discharge and protection circuits are incorporated into many integrated circuits. Such a protection circuit may include a diode connected to an input to clamp any voltage appearing to a safe value whilst discharging the electro-static energy. Unfortunately, such a diode has a certain capacitance associated with it and the combined effect of this capacitance together with the parasitic pad capacitance may degrade circuit performance to the point where it is unacceptable. Very high speed emitter coupled logic integrated circuits, for example, are sometimes unprotected.However, if the objective of reduced pad capacitance can be achieved, addition of electro-static discharge protection to emitter coupled logic circuits becomes possible to unprotected devices or enlargement of existing electro-static discharge protection structure to improve performance may be made..
In accordance with the present invention there is provided a connection site structure for an integrated circuit comprising interconnected devices formed by co-operating regions of semiconductor material of different types on a semi-conductor substrate the connection site including a pad formed on the semi-conductor material and an isolating layer between the pad and the semiconductor, the pad being subject to parasitic capacitance and wherein a region of semi-conductor material opposite in type to surrounding material exists proximate the pad giving rise to further capacitance appearing in series with at least a component of the parasitic capacitance thereby to reduce its effective value.
In one form of the present invention the material surrounding the region is substrate material. In an alternative form of the present invention the material surrounding the region is epi-taxial layer material opposite in type to the substrate.
The invention m#ay be applied to isolated device structures such as junction isolated structures wherein the pad is formed proximate an isolated island and an associated buried layer is present, for example.
In use the pad is connected to an adjacent device, for example a diffused resistor, formed contemporaneously with the region, a protection diode or an emitter coupled logic gate.
In order that features and advantages of the present invention may be further appreciated, an embodiment will now be described with reference to the accompanying diagrammatic drawings, of which: - Fig 1 represents a prior art connection site, and Fig 2 represents a connection site in accordance with the present with its pad connected to a resistor.
In a connection site structure 10 typical in the prior art, a pad is formed by a metalisation 12 being a track leading away to a circuit node (not shown) to which connection is to be made and a further metalisation 11 to provide a pad substantial enough for a wire to be attached for example by bonding. To isolate the metalisations 11 and 12 from the semi-conductor material 14 to which they are applied, a dielectric layer 15 of for example silicon oxide is first provided. The active devices (not shown) of the circuit are formed by co-operating regions of different semi-conductor type including n-type epi-taxial region 16 formed on p-type substrate 17.
The site is isolated from neighbouring devices and site by a isolation region 18 which is thus arranged to give an isolated island in the epi-taxial layer. The structure described thus for will be recognised by those skilled in the art as a junction isolated epi-taxial arrangement, which is well known and described for example in Basic Integrated Circuit Engineering by Hamilton and Howard (McGraw-Hill, 1975), especially pages 4 to 8. The structure is completed by di-electric layer 19 of for example phosphor silica glass which serves to isolate selectively the two metalisations to increase the interconnection possibilities and a passivation layer 100 of for example to provide protection.
In accordance with good design practice, no device is formed in the island beneath the pad, however the pad will interact with the semi-conductor beneath. In particular it will be noted that the di-electric layer 15 is sandwiched between two conductive layers (the pad and the semi-conductor) and so a parasitic capacitance arises between the pad and the substrate which is indicated diagrammatically by capacitor symbol Cm 01. Capacitance contributing to the overall parasitic capacitance also occurs at each junction due to charge storage by depletion and again this is diagrammatically indicated by capacitor symbols C102 (epi-taxial layer to isolation) and C103 (epi-taxial layer to substrate).It will be appreciated that since the p+ isolation diffusion and the substrate are electrically common, the parasitic capacitance effectively comprises Cloy in series with the parallel combination of C102 and C103.
A connection site in accordance with the present invention 21, by contrast, includes a region 20 (Figure 2 in which integers common with Fig 1 have been given common reference numerals) of semi-conductor of the type opposite to the surrounding epi-taxial layer material 16, that is p type since the epi-taxial layer is of ntype material. An extra junction is created which has an associated capacitance (diagrammatically indicated by capacitor symbol C22).
It will be observed that this capacitance appears in series with the components contributing to parasitism, that is C 101 and the parallel combination of C102 and C103 thereby to reduce the effective parasitic capacitance as follows The effective parasitic capacitance (C1) associated with the pad of the prior art connection site (10), is given by: 1 = 1 + 1 C1 C101 C102 + C103 The effective parasitic capacitance (C1) associated with the pad of the prior art connection site (10), is given by: 1 = 1 + 1 + 1 = 1+ 1 C2 C101 C22 C102 + C103 C1 C22 Hence C2 is less than C1 and parasitic capacitance associated with the pad is reduced compared with the prior art structure.
In a practical circuit, the metalisation 12 may form a track to a circuit device and to this end the metalisation is shown extended to a neighbouring junction isolated island 27 to contact a region 23 constituting a diffused resistor. A further metalisation 24 is made to the remote end of diffused resistor 23 and enhanced regions 25 ensure good contact with the resistor terminations. For the structure described (n-type epi-taxial layer, p substrate) the resistor would be formed by a p diffusion processing step, which is also the diffusion required to form the p implant region 20 to reduce pad parasitic capacitance in accordance with the present invention.
Hence it will be appreciated that the region 20 can be provided without adding an extra processing step to circuit fabrication over and above that required to form a diffused resistor.
In cell 27 the n+ buried layer 26 associated with the formation of transistors in junction isolated processes has been retained since it is found to be advantageous in maintaining the resistor island equi-potential (in practice resistor 23 would be one of many resistors present on the island, their reverse bias assuring independence). Indeed, it is standard practice in some processes to form a buried layer under each and every island, including connection sites. The extra junctions formed by buried layer (n+ diffusion) create a further component to contribute to pad parasitic capacitance namely that due to the buried layer/isolation junctions.
Moreover, the buried layer to substrate junction is likely to be of higher value than the epi-taxial layer to substrate junction it replaces, both capacitance appearing in parallel with Cl 02.
Although generally applicable the present invention is particularly applicable to this buried layer structure since it provides a capacitance in series with the parallel combination. The present invention is also applicable to variations of the isolated process, such as for example oxide isolation.
Two important aspects of the present invention which have been realised are that protection diodes may be installed on high speed (e.g. emitter coupled logic) inputs since the pad capacitance is reduced and that improved insulation yielding greater reliability may be used in isolation 15 (for example silicon nitride to replace silicon oxide), which would otherwise increase pad capacitance to an unacceptable level.

Claims (15)

  1. Claims
    The matter for which the applicant seeks protection is:1. A connection site structure for an integrated circuit comprising interconnected devices formed by co-operating regions of semiconductor material of different types on a semi-conductor substrate the connection site including a pad formed on the semi-conductor material and an isolating layer between the pad and the semiconductor, the pad being subject to parasitic capacitance and wherein a region of semi-conductor material opposite in type to surrounding material exists proximate the pad giving rise to further capacitance appearing in series with at least a component of the parasitic capacitance thereby to reduce its effective value.
  2. 2. A connection site as claimed in claim 1 and wherein the material surrounding the region is substrate material.
  3. 3. A connection site as claimed in claim 1 and wherein the material surrounding the region is epi-taxial layer material opposite in type to the substrate.
  4. 4. A connection site as claimed in claim 1, 2 or claim 3 and wherein the pad is formed proximate an isolated island.
  5. 5. A connection site as claimed in claim 4 and wherein the pad is formed above said island.
  6. 6. A connection site as claimed in claim 4 or claim 5 and wherein the isolated island has an associated buried layer.
  7. 7. A connection site as claimed in any preceding claim and wherein the pad is connected to an adjacent structure.
  8. 8. A connection site as claimed in claim 7 and wherein the adjacent structure is a diffused resistor, formed contemporaneously with the region.
  9. 9. A connection site as claimed in 7 and wherein the adjacent structure is a transistor formed contemporaneously with the region.
  10. 10. A connection site as claimed in claim 7 and wherein the adjacent structure is an enhancement diffusion for a contact, said diffusion being formed contemporaneously therewith.
  11. 11. A connection site as claimed in claim 7 and wherein the pad is connected to a protection diode.
  12. 12. A connection site as claimed in claim 7 and wherein the pad is further connected to an emitter coupled logic gate.
  13. 13. A connection site as claimed in claim 7 and wherein the pad is further connected to a transistor-transistor logic gate.
  14. 14. A connection site as claimed in claim 7 and wherein the pad is further connected to a metal oxide semi-conductor gate.
  15. 15. A connection site substantially as herein described with reference to Fig 2 of the drawings.
GB9009500A 1990-04-27 1990-04-27 Semiconductor device contact pads Withdrawn GB2243485A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB9009500A GB2243485A (en) 1990-04-27 1990-04-27 Semiconductor device contact pads

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Application Number Priority Date Filing Date Title
GB9009500A GB2243485A (en) 1990-04-27 1990-04-27 Semiconductor device contact pads

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GB9009500D0 GB9009500D0 (en) 1990-06-20
GB2243485A true GB2243485A (en) 1991-10-30

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0613178A2 (en) * 1993-02-26 1994-08-31 Dow Corning Corporation Integrated circuits protected from the environment by ceramic and barrier metal layers
US5539243A (en) * 1993-08-03 1996-07-23 Nec Corporation Semiconductor device having spaces and having reduced parasitic capacitance
US5731620A (en) * 1995-09-08 1998-03-24 Sony Corporation Semiconductor device with reduced parasitic substrate capacitance
EP0892438A2 (en) * 1997-06-30 1999-01-20 Matsushita Electric Works, Ltd. Solid-state relay
WO1999012209A1 (en) * 1997-09-02 1999-03-11 Telefonaktiebolaget Lm Ericsson (Publ) Protective circuit
WO2000035013A1 (en) * 1998-12-04 2000-06-15 Koninklijke Philips Electronics N.V. An integrated circuit device
EP1035575A2 (en) * 1999-03-09 2000-09-13 Sanyo Electric Co., Ltd. Semiconductor device
EP1039545A2 (en) * 1999-03-26 2000-09-27 Sanyo Electric Co., Limited. Semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1007936A (en) * 1961-04-26 1965-10-22 Clevite Corp Improvements in or relating to semiconductive devices
GB1138029A (en) * 1965-03-19 1968-12-27 Rca Corp Semiconductor devices
EP0161983A2 (en) * 1984-05-03 1985-11-21 Digital Equipment Corporation Input protection arrangement for VLSI integrated circuit devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1007936A (en) * 1961-04-26 1965-10-22 Clevite Corp Improvements in or relating to semiconductive devices
GB1138029A (en) * 1965-03-19 1968-12-27 Rca Corp Semiconductor devices
EP0161983A2 (en) * 1984-05-03 1985-11-21 Digital Equipment Corporation Input protection arrangement for VLSI integrated circuit devices

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0613178A3 (en) * 1993-02-26 1994-11-09 Dow Corning Integrated circuits protected from the environment by ceramic and barrier metal layers.
EP0613178A2 (en) * 1993-02-26 1994-08-31 Dow Corning Corporation Integrated circuits protected from the environment by ceramic and barrier metal layers
US5539243A (en) * 1993-08-03 1996-07-23 Nec Corporation Semiconductor device having spaces and having reduced parasitic capacitance
US5936289A (en) * 1995-09-08 1999-08-10 Sony Corporation Semiconductor device
US5731620A (en) * 1995-09-08 1998-03-24 Sony Corporation Semiconductor device with reduced parasitic substrate capacitance
EP0892438A3 (en) * 1997-06-30 2000-09-13 Matsushita Electric Works, Ltd. Solid-state relay
EP0892438A2 (en) * 1997-06-30 1999-01-20 Matsushita Electric Works, Ltd. Solid-state relay
US6211551B1 (en) 1997-06-30 2001-04-03 Matsushita Electric Works, Ltd. Solid-state relay
US6373101B1 (en) 1997-06-30 2002-04-16 Matsushita Electric Works Solid-state relay
US6580126B1 (en) 1997-06-30 2003-06-17 Matsushita Electric Works, Ltd. Solid-state relay
WO1999012209A1 (en) * 1997-09-02 1999-03-11 Telefonaktiebolaget Lm Ericsson (Publ) Protective circuit
WO2000035013A1 (en) * 1998-12-04 2000-06-15 Koninklijke Philips Electronics N.V. An integrated circuit device
US6555857B1 (en) 1999-03-09 2003-04-29 Sanyo Electric Co., Ltd. Semiconductor device
EP1035575A2 (en) * 1999-03-09 2000-09-13 Sanyo Electric Co., Ltd. Semiconductor device
US6960797B2 (en) 1999-03-09 2005-11-01 Sanyo Electric Co., Ltd. Semiconductor device
EP1035575A3 (en) * 1999-03-09 2001-10-17 Sanyo Electric Co., Ltd. Semiconductor device
EP1039545A2 (en) * 1999-03-26 2000-09-27 Sanyo Electric Co., Limited. Semiconductor device
US6522012B2 (en) 1999-03-26 2003-02-18 Sanyo Electric Co., Ltd. Semiconductor device with HIHG resistivity
US6392307B1 (en) 1999-03-26 2002-05-21 Sanyo Electric Co., Ltd. Semiconductor device
EP1039545A3 (en) * 1999-03-26 2001-10-17 Sanyo Electric Co., Limited. Semiconductor device

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Publication number Publication date
GB9009500D0 (en) 1990-06-20

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