GB2236204A - Extending data storage buffer - Google Patents
Extending data storage buffer Download PDFInfo
- Publication number
- GB2236204A GB2236204A GB9019382A GB9019382A GB2236204A GB 2236204 A GB2236204 A GB 2236204A GB 9019382 A GB9019382 A GB 9019382A GB 9019382 A GB9019382 A GB 9019382A GB 2236204 A GB2236204 A GB 2236204A
- Authority
- GB
- United Kingdom
- Prior art keywords
- memory
- region
- data
- buffer
- electronic apparatus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0656—Data buffering arrangements
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
A method of extending a buffer 5 of an electronic apparatus for temporarily storing data transferred from an external memory unit 6, the buffer 5 being contained in a first region of a main memory 10, comprises determining whether or not an empty area exists in a second region 4 of the main memory 10 if a capacity of the buffer 5 is insufficient for storing data from the external memory unit 6, registering the empty area as an extended buffer 7 for storing the data when it is determined that the empty area exists, and using the registered empty area for the electronic apparatus to execute a task when a capacity of the second region 4 is otherwise insufficient for executing the task. <IMAGE>
Description
TITLE OF THE INVENTION
METHOD OF EXTENDING BUFFER
BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a method of extending a buffer for temporarily storing external data of an electronic apparatus which communicates with an external memory unit.
2. Description of the Related Art
An electronic apparatus designed to read data from an external memory unit and perform some tasks such as an arithmetic operation normally comprises a central processing unit (CPU), an interface for the CPU, an I/O management unit, and a buffer pool with a fixed capacity for storing data read from the external memory unit.
In such an electronic apparatus, for reading data from the external memory unit, the CPU issues an instruction for requesting transference of necessary data from the external memory unit to the I/O management unit through the interface. In response to the instruction, the I/O management unit reads the requested data from the external memory unit and stores it in the buffer pool.
Then, the CPU performs an operation on the data stored in the buffer pool.
The foregoing apparatus, however, has the following two shortcomings mainly resulting from the fixed capacity of the buffer pool.
(1) If the capacity of the buffer is relatively small compared with a data reading frequency, the buffer is' filled up with the read data shortly. For reading data still more, therefore, it is necessary to discard some pieces of data stored in the buffer or transfer them into the external memory unit for preparing an empty area.
This results in bringing about frequent data transference between the electronic apparatus having the buffer and the external memory unit, thereby lowering a data processing speed.
(2) To overcome the above shortcoming, if a larger capacity is allocated to the buffer, capacities of other areas (a user area provided for an application program, for example) are made relatively smaller because the total capacity of a memory included in the apparatus is fixed. It also results in lowering the data processing speed.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of extending a buffer for storing external data without suppressing other areas except the buffer.
The object of the invention can be achieved by a method of extending a buffer of an electronic apparatus for temporarily storing data transferred from an external memory unit, said buffer being contained in a first region of a main memory provided in said electronic apparatus, said method comprising the steps of:
determining whether or not an empty area exists in a second region of said main memory if a capacity of said buffer is insufficient for storing data from said external memory unit;
registering said empty area as an extended buffer for storing said data when it is determined that said empty area exists in said second region of said main memory; and
using said registered empty area for said electronic apparatus to execute a task when a capacity of said second region is insufficient for executing said task.
According to the invention, the frequency of data transference between the buffer and the external memory unit can be reduced without increasing the capacity of the buffer thereby improving the data processing speed.
Further object and advantages of the present invention will be apparent from the following description of the preferred embodiments of the invention as illustrated in the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a block diagram showing an arrangement of a memory section of an electronic apparatus to which an embodiment of the invention is applied;
Fig. 2 is a flowchart for explaining how an I/O management unit of Fig. 1 operates;
Fig. 3 is a flowchart for explaining how a memory management unit of Fig. 1 operates;
Fig. 4 is a view showing a memory section of another embodiment to which the invention is applied; and
Fig. 5 is a flowchart for explaining how the memory section of the another embodiment operates.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Herein, an embodiment of the present invention will be described with reference to the drawings.
Fig. 1 is a block diagram illustrating an arrangement of a memory section of an electronic apparatus to which the method of the invention is applied.
1 denotes an interface unit provided between a CPU (not shown) and a main memory unit 10. 2 denotes an I/O management unit for controlling data transference with an external memory unit 6. 5 denotes a buffer pool for storing data read from the external memory unit 6, 3 denotes a memory management unit for controlling the main memory unit 10 except the buffer pool 5, 4 denotes a user area for containing an application program, and 7 denotes an extended buffer pool EBP (to be described later). The main memory unit 10 comprises a region for containing the user area 4 and another region for containing the buffer pool 5.
The external memory unit 6 comprises a magnetic disk such as a floppy disk or harddisk.
Next, how to obtain the extended buffer pool 7 in the user area 4 will be described with reference to Figs.
2 and 3.
Fig. 2 is a flowchart for explaining how the I/O management unit 2 operates at the time of obtaining the extended buffer pool 7.
At first, when the CPU issues an instruction through the interface 1 for requesting data transference from the external memory unit 6, the I/O management unit 2 determines whether the requested data exists in the buffer pool 5. If not, the unit 2 issues a request for preparing an area in the main memory unit 10 for storing data read from the external memory unit 6 (step S1).
Then, it is determined if an empty area is left in the buffer pool 5 (step S2). If it is left, the process goes to step S6 and if not, the process goes to step S3. In step S3, the I/O management unit 2 requests the memory management unit 3 to spare an area to be used as the buffer pool. When a new area has been obtained with success, it is registered as the extended buffer pool EBP in step S4. If not area can be obtained, the process goes to step S5 in which some pieces of data stored in the existing buffer pool 5 is discarded or transferred to the external memory unit 6 for preparing an empty area.
In step 6, the I/O management unit 2 puts the prepared empty area under the control of the CPU. The CPU transfers desired data from the external memory unit 6 to the prepared empty area in the buffer pool through the interface 1 and the I/O management unit 2.
Fig. 3 is a flowchart for explaining the operation of the memory management unit 3 during the aforementioned step S3.
When the I/O management unit 2 issues a request for preparing an area to be used as the buffer pool, the memory management unit 3 checks if an empty area is left in the user area 4 in step S7 included in step S3 of the flowchart of Fig. 2. If not, the process goes to step S8 where the memory management unit 3 determines if an empty area (not shown) usable as the buffer pool is left within the main memory unit except the user area 4. In step S7 or S8, if an empty area is found out, the memory management unit 3 puts the empty area under the control of the I/O management unit 2. If it is not found out, it issues to the I/O management unit 2 a message indicating that it is impossible to set up a new memory area usable as the buffer pool.
The area newly registered as the extended buffer pool is not permanently used as the buffer pool. If the memory management unit 3 issues a request to the I/O management unit 2 for returning the area, the extended buffer pool 7 is separated from the buffer pool 5 and is returned to be under the control of the memory management unit 3. This will be described with reference to the arrangement of the memory section of Fig. 1. When the memory management unit 3 issues the request for returning the memory area, that is, the extended buffer pool 7 within the user area or another area, to the I/O management unit 2, the I/O management unit 2 checks if some data exists in the extended buffer pool. If some data exists, it is discarded or transferred to the external memory unit 6 and then the area is separated from the buffer pool 5.Then, the memory management unit 3 keeps the separated area under its own control for using the area.
As described above, the buffer pool for temporarily storing the external data is allowed to extend by utilizing an empty area within the main memory unit as required. It makes possible to reduce the data transference frequency thereby improving the data processing speed.
Further, if other area except the buffer pool becomes insufficient in capacity, the newly obtained extended buffer pool is given back to this other area.
Therefore, the extension of the buffer pool does not suppress other area with in the main memory unit and becomes no obstacle to the processing of a task.
Next, the description will be directed to another electronic apparatus with a virtual memory and a virtual memory management capability.
Fig. 4 shows the correspondence between an external memory and a memory included in the electronic apparatus provided with a virtual memory management capability.
The electronic apparatus has a real memory 8 and a virtual memory 9, the areas a and b within the external memory 6 are allocated to areas E and G within the virtual memory 9. The real memory 8 contains areas A, B,
C, F and G selected from the areas allocated to the virtual memory 9. With this arrangement, the virtual memory 9 can be considered as a memory virtually extended with respect to the real memory 8. In this electronic apparatus having such a memory arrangement, data is transferred between the external memory 6 and the virtual memory 9.
The data transference operation will be described with reference to the flowchart shown in Fig. 5.
When an access request to the virtual memory 9 is occurred in step S11, it is determined if the requested area exists in the real memory 8 in step S12. If the area exists in the real memory 8, this routine is finished and the process goes to another routine. If' no area exists in the real memory 8, the process goes to step S13 where it is determined if there is left an empty area in the real memory 8 to which the requested area can be allocated. If no empty area is left, the process goes to step S14 where it is determined which area among the existing areas within the real memory 8 should be deleted for preparing an empty area. Then, in step S15,#.it is checked if the area determined in step S14 is an area allocated to the external memory 6.If so, in step Si6, it is checked if the contents of the area have been changed. If they have been changed, in step S17, the contents of the area are written to the external memory 6, and if not, the area is discarded. In step S15, if it is determined that the area to be deleted is an area which is not allocated to the external memory 6, the process goes to step S19 where the contents of the area to be deleted are written in a swap area (not shown) within the external memory 6 or discarded.
Thus, an empty area is prepared within the real memory 8. Then, in step S20, the requested area within the virtual memory 9 is allocated to the empty area.
And, in step 521, it is checked if the requested area of the virtual memory 9 is allocated to an area within the external memory 6. If it is, in step S22, the contents of the area within the external memory 6 is read out into the empty area. If it is not, that is, the requested area of the virtual memory 9 is allocated to an area which is not included in the external memory 6, in step
S23, the contents of the swap area are read out into the empty area prepared within the real memory 8. After completing all these steps, the access to the area within the real memory 8 corresponding to the requested area within the virtual memory 9 is started.
It is to be understood from the above description that it is possible to realize the management of a virtual memory virtually extended with respect to a real memory by applying the present invention to the electronic apparatus provided with a virtual memory management capability.
Many widely different embodiments of the present invention may be constructed without departing from the spirit and scope of the present invention. It should be understood that the present invention is not limited to the specific embodiments described in the specification, except as defined in the appended claims.
There are described above novel features which the skilled man will appreciate give rise to advantages. These are each independent aspects of the invention to be covered by the present application, irrespective of whether or not they are included within the scope of the following claims.
Claims (11)
1. A method of extending a buffer of an electronic apparatus for temporarily storing data transferred from an external memory unit, said buffer being contained in a first region of a main memory provided in said electronic apparatus, said method comprising the steps of:
determining whether or not an empty area exists in a second region of said main memory if a capacity of said buffer is insufficient for storing data from said external memory unit;
registering said empty area as an extended buffer for storing said data when it is determined that said empty area exists in said second region of said main memory; and
using said registered empty area for said electronic apparatus to execute a task when a capacity of said second region is insufficient for executing said task.
2. A method according to claim 1, in which said second region contains a user area for storing an application program.
3. A method according to claim 1, in which if it is determined that no empty area exists in said second region, some pieces of data stored in said buffer is discarded or transferred to said external memory unit for preparing an empty area in said buffer.
4. A method according to claim 3, in which said second region contains a user area for storing an application program.
5. A method according to claim 1, in which said main memory comprises a real memory and a virtual memory which is extended virtually with respect to said real memory by utilizing said external memory unit.
6. An electronic apparatus which includes a data memory having first and second memory regions and means for controlling the storage in said data memory of data transferred from an external memory unit (eg.
a magnetic disk), said controlling means being operable to extend the first memory region, which is a region designated for storing the transferred data, if at the time of data transfer there is both insufficient space in said first memory region to store the transferred data, and also spare space in said second memory region, which is normally designated for another purpose, said spare space then being temporarily designated as an extension area of said first memory region, the controlling means also being operable to return said extension area for normal use for said another purpose if required.
7. An electronic apparatus according to claim 6 wherein said controlling means is operable if at said time of data transfer there is insufficient spare space in said first memory region but no, or insufficient space in the second memory region, to clear data from said first memory region so as to prepare space therein for receiving the transferred data.
8. A method of extending a buffer of an electronic apparatus substantially as hereinbefore described with reference to Figures 1 to 3 of the accompanying drawings.
9. A method of extending a buffer of an electronic apparatus substantially as hereinbefore described with reference to Figures 4 and 5 of the accompanying drawings.
10. An electronic apparatus substantially as hereinbefore described with reference to Figures 1 to 3 of the accompanying drawings.
11. An electronic apparatus substantially as hereinbefore described with reference to Figures 4 and 5 of the accompanying drawings.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1232576A JP2504843B2 (en) | 1989-09-06 | 1989-09-06 | Buffer expansion device |
Publications (3)
Publication Number | Publication Date |
---|---|
GB9019382D0 GB9019382D0 (en) | 1990-10-17 |
GB2236204A true GB2236204A (en) | 1991-03-27 |
GB2236204B GB2236204B (en) | 1993-08-18 |
Family
ID=16941515
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9019382A Expired - Lifetime GB2236204B (en) | 1989-09-06 | 1990-09-05 | Method of extending buffer |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP2504843B2 (en) |
GB (1) | GB2236204B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120311294A1 (en) * | 2010-02-10 | 2012-12-06 | Yoshiaki Noguchi | Storage device |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07319630A (en) * | 1994-05-27 | 1995-12-08 | Nec Corp | Buffer capacity determination system |
JP3551259B2 (en) * | 2003-04-24 | 2004-08-04 | ソニー株式会社 | Information device control system, information device and control method therefor |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0099462A2 (en) * | 1982-07-19 | 1984-02-01 | International Business Machines Corporation | Apparatus and method for buffering data in a data processing system |
EP0153553A2 (en) * | 1984-02-27 | 1985-09-04 | International Business Machines Corporation | Data storage system |
GB2222504A (en) * | 1987-06-24 | 1990-03-07 | Westinghouse Electric Corp | Multiprocessor information exchange |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51101432A (en) * | 1975-03-04 | 1976-09-07 | Hitachi Ltd | DEETABATSU FUASEIGYO HOSHIKI |
-
1989
- 1989-09-06 JP JP1232576A patent/JP2504843B2/en not_active Expired - Lifetime
-
1990
- 1990-09-05 GB GB9019382A patent/GB2236204B/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0099462A2 (en) * | 1982-07-19 | 1984-02-01 | International Business Machines Corporation | Apparatus and method for buffering data in a data processing system |
EP0153553A2 (en) * | 1984-02-27 | 1985-09-04 | International Business Machines Corporation | Data storage system |
GB2222504A (en) * | 1987-06-24 | 1990-03-07 | Westinghouse Electric Corp | Multiprocessor information exchange |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120311294A1 (en) * | 2010-02-10 | 2012-12-06 | Yoshiaki Noguchi | Storage device |
US9021230B2 (en) * | 2010-02-10 | 2015-04-28 | Nec Corporation | Storage device |
Also Published As
Publication number | Publication date |
---|---|
GB2236204B (en) | 1993-08-18 |
GB9019382D0 (en) | 1990-10-17 |
JP2504843B2 (en) | 1996-06-05 |
JPH0394346A (en) | 1991-04-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PE20 | Patent expired after termination of 20 years |
Expiry date: 20100904 |