GB2235075A - Switching module for pairs of homologous processors connected to at least one communication bus - Google Patents
Switching module for pairs of homologous processors connected to at least one communication bus Download PDFInfo
- Publication number
- GB2235075A GB2235075A GB9014070A GB9014070A GB2235075A GB 2235075 A GB2235075 A GB 2235075A GB 9014070 A GB9014070 A GB 9014070A GB 9014070 A GB9014070 A GB 9014070A GB 2235075 A GB2235075 A GB 2235075A
- Authority
- GB
- United Kingdom
- Prior art keywords
- processor
- switching
- homologous
- switching module
- communication bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
- G06F11/2023—Failover techniques
- G06F11/2028—Failover techniques eliminating a faulty processor or activating a spare
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/2015—Redundant power supplies
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
- G06F11/2023—Failover techniques
- G06F11/2025—Failover techniques using centralised failover control functionality
Abstract
A switching module SWA for at least one processor SC connected to a communication bus MB comprises means for detecting any defective operation of the processor and its consequent resetting, cutting off the line of communication between the processor and associated bit-buses, and cutting off the power supply to the processor. In order to achieve modular redundancy, the module is inserted between a pair of homologous processors (a "master" and a "slave"), connected in parallel to the bus MB; it is also connected with homologous pairs of switching boards SWI inserted between each processor and the bus MB. <IMAGE>
Description
1 \11 X\ 1 Switching module for pairs of homologous__ processors connected
to at least one communication bus The subject-matter of this invention consists of a switching module for pairs of homologous processors connected to at least one communication bus. Computer systems consisting of a number of dedicated computers connected.to one another in parallel by a communication bus are now widespread.
Figure 1 shows a diagram of a system of this..type which includes, generally, a communication bus (PSB) cominxinicating with a series of dedicated processors (SC), which in turn are used for the management of single portions of a distributed-intelligence industrial plant through serial communication lines (bit-buses). In the case illustrated, the communication bus is of the type known commercially under Intel's name of Parallel System Bus.
A structure of this type, with independent processors, allows the functions to be split up while guaranteeing at the same time coordination towards the upper structure of the hierarchy. The single processors (SC), for example, may be dedicated to several functional subas- f 2 semblies of the plant, as stated above. The abbreviation 01 indiCates a terminal for communicating with the operator.
An arrangement of this type is not sufficient from the point of view of reliability of the whole system. even if the failure of one module (SC) entails only the loss of a limited portion of the plant, as the bit-bus nodes dependent on the failed processor may be numerous and perform very important functions.
Although the single bit-bus nodes can perform independently as standalone units the analog and digital adjustments for which they are programmed, proper functioning of the processor (SC) is indispensable for:
- co-ordinating the more- complex adjustments which cannot be confined to a single bit-bus node due to the high number of 1/0 or to the complexity of the processing; - co-ordinating bit-bus nodes touching on different bit-buses by means of dialogue s with other processors (SC); implementing a connection with the higher structures of the hierarchy; supplying information of a diagnostic nature concer- i 3 ning the dependent bit-bus; - ensuring that a specific failure mode of the processor (SC), having a negative impact on the operation of the associated bit-bus expansion, even if it is functionally independent, will prejudice the associated bit- bus node/man-machine interface (01)..
Based on^the above, it is clear that a sufficient degree of reliability may be achieved by redundancy of the elements forming the system, and specifically by redundancy of the single processors (SC). The purpose of this invention is to create a switching module that, in the presence of a pair of processors. one being the master and the other the slave, is capable of detecting any failure conditions and switching the control functions from one to the other of these processors, without breaks in the operation of the associated bit-bus nodes.
According to the present invention, there is provided a switching module acccording to the appended claims, to which reference is hereby directed.
The switching module according to an embodiment of the invention, indicaited hereinafter as SWA, performs the following fundamental functions:
- monitoring the operation of the two associated processors (SC), promptly detecting their failure; - switching the bit-bus controlled by the failed ma- 4 ster processor (SC) from the latter to the other, slave, processor (SC); - ensuring a high degree of reliability of its own circuitry by electrically oversized components so as to minimise stress, redundancy of the components with limited reliability values, use of "critical' components having guaranteed reliability pin-to-pin compatible equivalen. t elements.
The switching module according to the invention may be inserted in the system of-processors linked on one side to at least one communication bus and on the other to the relevant bit-bus nodes,.in different configurations which give rise to total or modular redundancy.
The term total redundancy- is used to mean complete switching of a structure consisting of a communication bus associated with several processors (SC) having the function of master and of which one has failed, to another identical structure in proper working order. In this case each pair of homologous processors is monitOred by a switching module according to the invention, dedicated to that pair of processors. As soon as one of the switching modules according to the invention detects an upset in the operation of the associated ma- ster processor, all the bit-bus nodes controlled by the various master processors are switched to the slave structure, consisting of its own communication bus and corresponding processors (SC).
Total redundancy may also be achieved, by means of the switching module according to the invention, in such a way that he failed processor can be replaced without interrupting the power supply to the remaining processors. In this case each processor (SC) will be associated with a switching board, indicated hereinafter as SWI, and which forms the subject matter of a parallel invention by the same applicant.
The term modular redundancy is used to indicate the individual switching from one of the various master processors (SC), following its failure, to a slave processor (SC) connected to the same communication bus.
Lastly, the switching module according to the invention can be used in conjunction with said switching board (SWI) even without processor (SC) redundancy: in this case the switching module, combined with said switching board, allows only disconnection of the failed processor and its replacement without cutting of the power 6 supplies to the system.
This specific type of use of the switching module, as sociated with the switching board (SWI) is described and claimed in the parallel invention by the same applicant referred to above.
Some additional functions of the switching module according to the invention are listed below:
- signalling and instructions to switching boards (SW1) of the type indicated above; - interfacing with the centralised service modules, or so-called cabinet modules, for management of I/0 signals.
The scope and advantages of the invention are indicated in the following description referred to forms of embodiment chosen by way of example with specific reference to the attached drawings, in which:
- figure 1 shows the diagram of a computerised system to which the invention could be applied to advantage; - figure 2 shows a similar diagram, but altered by the presence of the switching module according to an embodiment of the in- vention, which, in this case,is not used to create conditions of redundancy but to allow replacement of a :S 7 switching board (SWI) without cutting off the power supplies to_ the computerised system; - figure 3 shows a similar system to that illustrated in figure 1, altered by the presence of switching mo- dules according to an embodiment of the invention, inserted in such a way as to create modular redundancy, in the presence of switching boards (SWI) which allow replacement of the failed processor (SC) while the homologous processor works properly; - figure 4 shows an application of the switching modu- le according to an embodiment of the invention in which total redundancy is achieved, with the additional use of switching boards (SWI); - figure 5 is similar to the foregoing, but the diagram shown does not call for the use of switching boards (SWI).
Figure 1 has already been illustrated in the introductory part of the description. In figure 2, a modified communication bus (MB) is shown instead of the communication bus (PSB). The modified communication bus (MB) is connected in parallel to (n) processors (SC1, Sc4,
SCn). Between each processor (SC) and the communication bus (MB) there is a corresponding switching board (SWIl, SW12,..., SWIn) according to a parallel 8 invention by the same applicant. Between each processor (SC) and its corresponding switching board (SW) there is a also inserted a switching module (SWA1, SWA2, SWAn) according to this invention.
The typology of the signals between the communication bus, the switching boards, the processors and the switching module is described below, of course schematically:
(A) Signal used for the parallel dialogue between the communication bus (MB) and the processor (SC) to exchange data during normal operation of the processor (SC).
(B) Signal used for the parallel dialogue between the communication bus (MB) and the switching board (SWI) for automatic initialisation of the processor (SC) after it is inserted. It should be remembered, in this respect, that the switching board is never removed from the communication bus (MB), and is therefore fed continuously for storage of the processor (SC) initialisation data.
(C) Power supply from the communication bus (MB) and directed towards the processor (SC) through the switching board (SWI), so that it may be cut off by the latter.
1 t, 4 9 (D) Portion of the power line to the processor (SC) comprised between the processor (SC) and the switching board (SWI) which, if necessary, can cut it off.
(E) Transmission line for the initialisation signals, contained in the switching board (SWI), to the processor (SC).
(F) Communication line between the switching board (SWI) and the processor (SC) for the transmission of a signal significant of the physical presence of the processor (SC) and for the transmission of the processor reset signal (kill board) in the event of defective operation.
(G) Communication line between the switching module (SWA) and the processor (SC) for diagnostic purposes, so as to evaluate when the switching board should step in (WATCHDOG, STOP, STOP EFFECTED, MASTER SC, INTERRUPT, functions the meanings of which are well known).
(H) Communication line between the switching module (SWA) and the switching board (SWI) to perform the logic functions associated with the operations for insertion and removal of the processor (SWITCHING PRESENT SWAPPING PRESENT - INSERT/REMOVE - PERMISSIVE) as well as those associated with the switching operations (KILL BOARD - POWER CORRECT - EXCESS CURRENT - SC PRESENT).
The function of the switching module is therefore to: - detect any upset of the-processor (SC); - communicate with the switching board (SWI) to reset the processor (SC) and monitor the power supplies); physically house the front-panel controls and signalling for the INSERT/REMOVE since the switching board will preferably have no front panel.
Other functions of the switching module (SWA)- are described with reference to the subsequent figures in which a modular or totally redundant system is described.
As far as concerns the switching board (SWI), it is essential for:
- resetting the processor (SC) detected as failed by the switching module (SWA) and controlling the power supplies; - cutting off the processor power supplies when this is detected as failed, in order to allow removal of the processor; - cutting off and reinstating the power supplies in order to allow reinsertion of the processor; - storing the processor (SC) initialisation information, so as to transmit it, after reinsertion of the 3 11 processor so as to return it to an operational status.
With specific reference to figure 3, concerning an application of the switching module in the event that modular redundancy is required, It should be remembered that the communication lines having the same names shown in figure 2 also have the same functions.
The index "A" and the index "B" appearing in the definition of the switching boards (SWIi) and in the processors (SCi), where (i) is a progressive index, represent 'homologous elements activated and deactivated respectively by the single associated switching module (SWAi).
Figur e 3 also shows the following lines of communication: - (I) line of direct communication between homologous processors "A" and "B" for updating the data; - (L) and (M), bit-bus communication lines between processor "A" or processor "B" towards the system bitbus, which in this case must pass through the switching module (SWA) so as to achieve the simplest condition of redundancy, which was lacking in the diagram of figure 2.
12 The diagram of figure 4 shows the most complete diagram of total redundancy. The presence of the switching boards (SW1) also allows individual replacement of the processor (SC) detected as having failed, with subsequent automatic restarting of the latter. For the Awitching boards (SWI) and for the switching module (SWA), the functions and the connections already illustrated with reference to figures 2 and 3 apply. The switching modules (SWA) are also serialised by means of the common line (N) for simultaneous switching from the whole set of processors related to Communication bus (MB) "A" to the whole set of processors related to the homologous communication bus (MB) "B".
Figure 5 describes the simplifie d version of total redundancy. Complete switching from the communication bus (MB) "A" to the homologous communication bus (MB) "B" allows the power supply to be completely cut off from the structure related to the communication bus involved, and thus the various initialisation operations to be performed even in the absence of the switching boards (SWI). For the various switching modules the functions and the connections described with reference to' figure 4 above apply.
11 i i 4 f 13 It is worthwhile to remember that in this case the communication bus (MB) must be modified so as to bypass the missing switching board; otherwise it may be the same standard communication bus (PSB) illustrated with reference to figure 1.
In addition to the lines of communication already illustrated, the solution shown in figure 5 also envisages the following other lines:
(0) line for parallel dialogue between the co=unication bus (MB) and each of the processors (SC), to allow non-automatic initialisation made necessary by the cutting off the power supply of the communication bus (MB) to which the failed and replaced processor (SC) belonged.
- (P) power supply, which cannot be cut off, from the communication bus (MB) towards each single processor (SC): in this case the power must be cut off by powering down the whole (MB) to which the failed processor belongs.
The foregoing embodiments of the present invention are given by way of example only, and are not intended to limit the scope of the present invention.
1 1 P 0 14
Claims (6)
1. A switching module for at least one processor connected to at least one communication bus; characterised in that it comprises: (i) means for detecting any defective operation of the processor and its consequent resetting, (ii) means for cutting off a line of communication between said processor and associated bit-buses, and (iii) means for cutting off a power supply to the processor.
2. A switching module for at least one pair of homologous processors, each said pair comprising one master and one slave, connected to at least one communication bus; characterised in that it comprises: (i) means for detecting any defective operation of the master processor and its consequent resetting, (ii) means for switching a connecting line between a bit-bus and a failed processor (SC) to a homologous processor (SC), (iii) means for cutting off the power supply to failed processor.
3. A switching module according to any preceding claim, further characterised in that it is inserted between a h dh pair of homologous processors, one master and one slave, connected in parallel to a common communication bus (MB); and in that it is connected to homologous pairs of switching boards inserted between each processor and the common communication bus.
4. A switching module according to claim 1 or 2, further characterised in that it is inserted between a pair of homologous processors, a master and a slave, connected in parallel directly to homologous communication buses (MB) "All and (MB) "B" (Figure 5).
5. A switching module according to claim 1 or 2, characterised by the fact that it is inserted between a pair of homologous processors, one master and one slave, connected in parallel to homologous communication buses (MB) "All and (MB) "B" through switching boards (SWI) "All and (SWI) "B" (figure 4.
6. A switching module substantially as described herein and with reference to the accompanying drawings.
Published 1991 at The Patent OfFice, State House. 66/71 High Holborn, London WCIR 47?. Further copies may be obtained from Sales Branch. Unit 6, Nin- Mile Point. CWmifelinfach. Cross Keys, NewporL NPI 7HZ. Printed by Multiplex techniques ltd. St Mary Cray. Kent.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT8912532A IT1232494B (en) | 1989-06-23 | 1989-06-23 | SWITCHING MODULE FOR COUPLES OF APPROVED PROCESSORS CONNECTED TO AT LEAST ONE COMMUNICATION BUS |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9014070D0 GB9014070D0 (en) | 1990-08-15 |
| GB2235075A true GB2235075A (en) | 1991-02-20 |
| GB2235075B GB2235075B (en) | 1993-05-26 |
Family
ID=11141272
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9014070A Expired - Fee Related GB2235075B (en) | 1989-06-23 | 1990-06-25 | Switching module for pairs of homologous processors connected to at least one communication bus |
Country Status (4)
| Country | Link |
|---|---|
| DE (1) | DE4019673A1 (en) |
| FR (1) | FR2648929B1 (en) |
| GB (1) | GB2235075B (en) |
| IT (1) | IT1232494B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001091477A1 (en) * | 2000-05-24 | 2001-11-29 | Centro Español De Servicios Telematicos, S.A. | Real time modular switching system for electronic communication devices |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6298376B1 (en) * | 1997-03-07 | 2001-10-02 | General Electric Company | Fault tolerant communication monitor for a master/slave system |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2086104A (en) * | 1980-09-17 | 1982-05-06 | Italtel Spa | Circuit Arrangement for Detecting Malfunctioning in Data Processing Systems |
| US4553204A (en) * | 1981-07-09 | 1985-11-12 | Pioneer Electronic Corp. | Central processing unit restoring mechanism for a system having a plurality of central processing units |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4387426A (en) * | 1979-09-06 | 1983-06-07 | Rolls-Royce Limited | Digital data processing system |
| US4835737A (en) * | 1986-07-21 | 1989-05-30 | American Telephone And Telegraph Company, At&T Bell Laboratories | Method and apparatus for controlled removal and insertion of circuit modules |
| FR2627607B1 (en) * | 1988-02-23 | 1993-03-12 | Sodeteg Tai | CENTRAL CONTROL COMPUTER UNIT |
-
1989
- 1989-06-23 IT IT8912532A patent/IT1232494B/en active
-
1990
- 1990-06-14 FR FR9007402A patent/FR2648929B1/en not_active Expired - Fee Related
- 1990-06-20 DE DE4019673A patent/DE4019673A1/en not_active Withdrawn
- 1990-06-25 GB GB9014070A patent/GB2235075B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2086104A (en) * | 1980-09-17 | 1982-05-06 | Italtel Spa | Circuit Arrangement for Detecting Malfunctioning in Data Processing Systems |
| US4553204A (en) * | 1981-07-09 | 1985-11-12 | Pioneer Electronic Corp. | Central processing unit restoring mechanism for a system having a plurality of central processing units |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001091477A1 (en) * | 2000-05-24 | 2001-11-29 | Centro Español De Servicios Telematicos, S.A. | Real time modular switching system for electronic communication devices |
| ES2162605A1 (en) * | 2000-05-24 | 2001-12-16 | Ct Espanol De Servicos Telemat | Real time modular switching system for electronic communication devices |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9014070D0 (en) | 1990-08-15 |
| FR2648929A1 (en) | 1990-12-28 |
| DE4019673A1 (en) | 1991-01-10 |
| IT8912532A0 (en) | 1989-06-23 |
| IT1232494B (en) | 1992-02-17 |
| GB2235075B (en) | 1993-05-26 |
| FR2648929B1 (en) | 1995-08-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19980625 |