GB2229600A - Differential PCM coder - Google Patents

Abstract

A differential pulse code modulation (DPCM) coder circuit provides parallel processing of prediction and code generation. This enhances the operating speed of the circuit. The two operations are performed each by a respective programmable read only memory (21, 22) provided with a look-up table from which digital words are determined. In a further embodiment, both operations are performed by a single read only memory. <IMAGE>

Description

DIFFERENTIAL PCM CODER This invention relates to coder circuits for differential pulse code modulation (DPCM) particularly for the transmission of digital signals.

Pulse code modulation (PCM) is widely used in digital communication systems. However, the application of PCM to the transmission of video signals normally requires a considerable number of bits to carry the necessary information. This in turn means that a large bandwidth is necessary. It has long been recognised that some means of bit reduction is desirable and several methods of achieving bit reduction have been proposed. One such method is differential pulse code modulation (DPCM). A description of this technique is given at pages 435 to 439 of "Cable Television Engineering", vol.ll No.9 Aug. 1981. In a DPCM coder the amplitude of incoming analogue signals is quantised according to a sliding measurement scale. The scale is referred to as sliding because the zero level of the scale is set at the quantised level of the previous sample.Each sample is then coded with reference to the previous sample. By using a non-linear scale, bit reduction is achieved since only the difference between two successive samples is coded and transmitted. This results in a significant reduction of bandwidth.

A conventional DPCM coder circuit is shown in Fig. 1 of the accompanying drawings. In this circuit an incoming analogue signal is converted to a corresponding digital signal n ), typically in the form of 6-bit words, by an analogue to digital converter 11. This signal is fed to a subtractor circuit 12 where it is compared with a predicted value yon derived from the previous 6-bit word to produce an output 7-bit word En = Yn ~ Yn the extra bit allowing for a possible carry digit. The subtractor circuit 11 introduces a time delay tl.The 7-bit word n is subjected to quantization by a compressor 13 to provide a corresponding 4-bit word Cn. n The compressor 13 includes a non-linear quantisor whereby small difference signals En are conveyed with full accuracy whilst longer difference signals are conveyed with progressively lower accuracy. The total number of quantizing levels may be significantly reduced without unduly impairing the subjective quality of the signal after transmission and decoding.

The predictionY n is determined by a feedback n loop comprising a non-linear quantizer 14, a summation circuit 15, an amplifier 16 and a delay circuit 17.

Each of these components in the feedback loop introduces its own time delay (t2, t t4). The cumulative delay represented by these components becomes significant at high bit rates and thus places a severe constraint on the rate at which the signals can be processed.

The object of the invention is to minimise or to overcome this disadvantage.

According to the invention there is provided a differential pulse code modulation (DPCM) coder circuit for providing compressed output digital words corresponding to the differences between successive input digital words, the circuit including means for generating predicted words from the input words, and means for generating compressed digital words determined from a comparison of input words each with a corresponding predicted word, the circuit being such that the generation of predicted words and the generation of output words are performed simultaneously.

According to the invention there is further provided a differential pulse code modulation (DPCM) coder circuit including first and second programmable read only memories, wherein said first memory is adapted to provide predicted digital words, and wherein said second memory is adapted to provide, from an input digital word and a corresponding predicted digital word received from the first memory, a compressed digital word corresponding to the difference between the input and predicted words, the circuit being such that the provision of predicted words and the provision of compressed digital words are performed simultaneously.

The prediction and difference/compression operations are performed in parallel. This provides a significant reduction in delay time and thus allows the circuit to operate at high bit rates.

Embodiments of the invention will now be described with reference to the accompanying drawings in which: Fig. 2 shows in schematic form a parallel architecture DPCM coder circuit; and Fig. 3 shows a modified form of circuit of Fig. 2.

The coder circuits shown in Figs. 1 and 2 are intended for use in the coding and transmission of PCM video signals. The difference, En, between each current PCM sample, Yn, along a TV line and a prediction of that sample, Y is non-uniformly n quantised and coded before transmission to a remote receiver station (not shown). The transmitted difference, E''n, is described by: = = COMPR ( E n n where: E = Y - Y n n n and COMPR( E ) implies the operation of non-uniform n quantisation followed by reduced word length coding. By quantising small picture element differences accurately and successively larger picture element differences less accurately, less quantisation levels are required within the available dynamic range and hence less bits are required for transmission.

For a digitised video signal seven bits can be employed to represent En and only four for E" The justification for this operation is a combination of video signal statistics and a property of human vision called spatial masking.

The prediction, Yn, is based on previously transmitted differences and may be described by the equation: Yn = A. E NUQ( En1 ) + Yn-l 1 or Y = A.Y' n n-l where Yln is the locally decoded version of Yn i.e.

different by the quantisation error,NUQ(En) implies the non-uniformly quantised version of En The non-uniform quantiser is included in the DPCM predictor to ensure that the same prediction may be reconstructed at the receiver.

At the receiver, the complimentary algorithm is implemented to recover an approximation, Y'n, to the original PCM samples. The algorithm is performed in two parts, expansion (the complement of compression) given by: En = EXPAND E" n and: Y' = E' + Yn n n n where E' n and YZn are the same as En and Yn but containing the quantisation error, which should not be visibly objectionable if the predictor and quantiser have been optimised. At the receiver, only ane PROM is required to recover the PCM approximation Y' n Referring now to Fig. 2, the DPCM coder circuit includes first and second programmable read only memories (PROM's) 21 and 22, and a delay latch circuit 23.Each memory is provided with a look-up table.

Input digital wordsYn, e.g. from an analogue to digital converter (not shown) are supplied to both memories.

The function of the second memory 22 is to generate predicted digital words Yn. n This is effected by comparing the input word Yn with a predicted word and using the look-up table to obtain the next prediction Yn+1. The delay latch 23 is controlled such that the current prediction r n arrives at the n input of each memory in the same time slot as the input word Yn. The prediction Yn as described above is given by the expression Yn = A [NUQ(Yn-1-Yn-1) + yn-1].

The first memory 21 receives both the input word Y and the predicted word Yn generated by the second memory 22. The first memory determines from these two words and from its own look-up table the compressed digital word '' , representing n compression of the difference En = (Y - -Y, for transmission to a remote station. Typically the input words Yn comprise six bits whilst the output n compressed words ''n ' ' comprise four bits.

n It will be appreciated that the second memory 22 performs the prediction at the same time that the first memory is performing the difference and comparison.

This is in contrast with conventional coder circuits which perform these operations serially.

Fig. 3 shows an alternative embodiment in which a single PROM 31 performs both the prediction and comparison functions from stored look-up tables. The functional operation of this circuit is similar to that of Fig. 2, the two operations being performed simultaneously by the PROM.

The differential PCM coder circuits described above with reference to Figs. 2 and 3 are of particular application in the transmission of video signals e.g.

via a satellite or an aircraft. They are also of general application to PCM transmission systems.

Claims (5)

1. A differential pulse code modulation (DPCM) coder circuit for providing compressed output digital words corresponding to the differences between successive input digital words, the circuit including means for providing predicted words from the input words, and means for providing compressed digital words determined from a comparison of said input words each with a corresponding predicted word, the circuit being such that the provision of predicted words and the provision of output words are effected simultaneously.

2. A DPCM coder circuit as claimed in claim 1, wherein the predicted words and the compressed digital words are provided from a read only memory.

3. A differential pulse code modulation (DPCM) coder circuit including first and second programmable read only memories, wherein said first memory is adapted to provide predicted digital words, and wherein said second memory is adapted to provide from an input digital word and a corresponding predicted digital word received from the first memory, a compressed digital word corresponding to the difference between the input and predicted words, the circuit being such that the provision of predicted words and the provision of compressed digital words are effected simultaneously.

4. A DPCM coder circuit as claimed in claim 3, wherein said second memory is provided with a look-up table from which the compressed words are determined.

5. A video transmission system incorporating a DPCM coder circuit as described in any one of claims 1 to 5.

5. A DPCM coder circuit substantially as described herein with reference to and as shown in Fig. 2 or Fig.

3 of the accompanying drawings.