GB2228155A - Analogue to digital converter - Google Patents

Abstract

An analogue to digital converter (ADC) generates a digital output word (Q) representing an analogue input signal (VS). The ADC comprises means for generating the most significant bit (Q1) of the output word by comparing the analogue input signal (VS) with a first reference signal (V1) and further comprises means for generating each next most significant bit (Q2 etc.) in turn by using the more significant bit(s) already determined to generate a respective further reference signal (V2 etc.) and comparing the input signal with the said further reference signal. The ADC comprises, in an asynchronous circuit (40), a separate comparator (20-k) for generating each bit (Qk) of the digital output word and a separate continuously operating digital to analogue converter (DAC) (32-k) for generating each such further reference signal (Vk). Each DAC (32-k) has an input (d1 to dk) connected to receive each of the said more significant bit(s) (q1 to qk) from the corresponding comparator. The asynchronous nature of the ADC allows high-speed operation and avoids the need for a bit-frequency clock signal. <IMAGE>

Description

Description ANALOGUE TO DIGITAL CONVERTER The invention relates to an analogue to digital converter (ADC) for generating a digital output word representing an analogue input signal, the ADC comprising means for generating the most significant bit of the output word by comparing the analogue input signal with a first reference signal and for generating each next most significant bit in turn by using the more significant bit(s) already determined to generate a respective further reference signal and comparing the analogue input signal with the said further reference signal.

Such an ADC is referred to generally in the art as a successive approximation-type ADC. Examples of successive approximation ADC's are described in European Patent Application EP-A2-O 249 986. In the known ADC's, a control circuit referred to as a successive approximation register (SAR) is used to synchronise the circuit operation and to keep track of the bits already determined. The SAR also causes a digital to analogue converter (DAC) to generate each further reference level by supplying the bits already found to the DAC, with the next bit to be determined provisionally set to a '1'. If the resulting DAC output signal is lower than the analogue input signal, then '1' is the correct value for the unknown bit and remains set in the SAR. If the DAC output signal is higher than the analogue input signal, then the bit should be a '0' and is reset in the SAR.

It is known that the successive approximation type of ADC offers a relatively high speed and accuracy of performance for such a compact circuit and for this reason it would be desirable to use such an ADC in low-cost integrated circuits for example for digital video processing in consumer apparatus. Unfortunately, in the known circuits the synchronous components and the SAR in particular require clock pulses to be applied in order to generate each reference level and each bit of the output word. In a 7-bit, 12 Hz video digitising application, for example, a clock signal of at least 84 MHz is therefore required. Such a high frequency clock signal is very difficult to generate and distribute on a low-cost integrated circuit made, for exampLe, in CMOS technology.

Higher-speed integrated circuit technologies are too expensive or otherwise unsuitable for such mass-market applications as have been described.

It has therefore been customary to use the alternative "flash" (or parallel) or "half-flash" ADC's to achieve the required performance for video digitising. A half-flash video ADC is described for example by R. E. J. van de Grift and R. J. van de Plassche in IEEE Journal of Solid State Circuits, Vol.SC-19, No. 3 (June 1984) at pages 374 to 378. Unfortunately, although such converters are fast, they require Large arrays of comparators and large decoding circuits and demand very high component accuracies.

The popular CMOS technology in particular is not capable of producing such accurate components with very high yields.

Therefore flash and half-flash ADC's remain too bulky and too expensive to be used as the "front-end" in mass-market digital signal processing chips.

It is an object of the present invention to enable the provision of a high-speed but relatively low-cost and compact ADC.

The invention provides an analogue to digital converter (ADC) for generating a digital output word representing an analogue input signal, the ADC comprising means for generating the most significant bit of the output word by comparing the analogue input signal with a first reference signal and for generating each next most significant bit in turn by using the more significant bit(s) already determined to generate a respective further reference signal and comparing the analogue input signal with the said further reference signal, characterised in that the ADC comprises, in an asynchronous circuit, a separate comparator for generating each bit of the digital output word and a separate digital to analogue converter (DAC) for generating each further reference signal, each DAC having an input connected to receive each of the said more significant bit(s) from the corresponding comparator.

In contrast with the conventional successive approximation ADC, the ADC in accordance with the invention can operate asynchronously, that is to say without internal clock signals.

Asynchronous operation affords a substantial speed advantage since each component of the ADC then operates at its maximum speed, without having to wait for a rigidly defined synchronisation signal. The digital to analogue conversion, for example, will generally take less time in the early (MSB) stages, since fewer bits need to be taken into account. In a conventional synchronous circuit, this potential time saving cannot be realised because the rigid clock period has to be long enough to allow for the longer conversion times of the later (LSB) stages.

In addition, there is a time and component overhead in synchronous circuits to provide the synchronisation itself. The ADC in accordance with the invention can be constructed using simple analogue circuit building blocks without the need for the flip-flops and other Logic circuits that are a part of a conventional successive approximation ADC. The additional comparators and DAC's of course take up extra space, but the ADC is still far more compact than a flash or half flash ADC.

It may be noted that an asychronous version of a different type of ADC has been proposed by D. G. Nairn and C. A. T. Salama in an article entitled "Algorithmic analogue/digital convertor based on current mirrors" published in Electronics Letters, Vol. 24, No. 8 (14th April 1988) at pages 471-472. However, the algorithmic type of ADC conventionally includes a separate stage (comparator and subtractor) for each bit, so that asynchronous operation is inherently possible. It may further be noted that while the known asynchronous algorithmic ADC is extremely compact and simple in construction, it is only capable of performing 6-bit conversion at a 200 kHz sampling rate, and moreover cannot readily be improved so as to achieve the level of performance countenanced by the present invention.In particular, the known ADC, being based on current mirrors, can only be improved in accuracy at the expense of speed and vice-versa. This follows because for accuracy, a current mirror ideally has infinite output impedance, which in turn means that it is slow at charging the inevitable input capacitance of the subsequent circuitry.

In an ADC in accordance with the invention, each DAC may comprise an R-2R ladder-type DAC. This type of DAC couples high speed with small size without requiring a wide range of high accuracy component values and is therefore suitable for integration in a low-cost processing chip.

The ADC may comprise sampling means for ensuring that the analogue input signal applied to the asynchronous circuit does not change significantly during the determination of the successive bits of the digital output word. The sampling means may not be necessary if the analogue input signal does not vary significantly during the time taken for a complete conversion.

The ADC may comprise Latching means for storing the bit values generated at the outputs of the comparators in the asynchronous circuit for a given analogue input value so that conversion of a further analogue input value can begin. The latching means may not be necessary for example if subsequent digital circuitry includes a latching function. The latching means may be clocked at the sampling frequency, at the instant in each cycle when it is known that the conversion should be complete.

The ADC may comprise a complementary metal oxide semiconductor (CMOS) integrated circuit. Such an ADC can be made at low cost, and can be made compact enough to be formed as just the front end of a large, predominantly digital signal processing chip, for which CMOS is a very desirable technology.

Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawing, the sole figure of which shows in block schematic form a 7-bit analogue to digital converter (ADC) in accordance with the present invention.

In the ADC shown in the figure, an analogue input 10 is connected to the input of a sample-and-hold circuit 12 which is also connected to a first clock terminal 14. The output 16 of the sample-and-hold circuit 12 is connected to the signal inputs (+) of seven comparators 20-1 to 20-7. Each comparator 20-k (where k takes values from 1 to 7) has a logic output 22-k connected to the data input of a respective one-bit clocked latch 24-k, each latch 24-k having a clock input connected to a second clock terminal 15. The outputs of the latches 24-1 to 24r7 form the outputs 26-1 to 26-7 of the ADC respectively.

A reference input 30 is connected to the reference input (-) of the first comparator 20-1. Six digital to analogue converters (DAC's) 32-2 to 32-7 are provided, and each DAC 32-k (where k takes values from 2 to 7) has an analogue output 34-k connected to the reference input (-) of the corresponding comparator 20-k. Each DAC 3 Hk has k bit inputs for receiving a digital word having k bits dl to dk. The last (least significant) bit input dk of each DAC 32-k is connected to a fixed level representing logic '1'. The k-l more significant bit input(s) dl to d(k-l) of each DAC 32-k are connected to the output(s) 22-1 to 22-(k-1) of the preceding comparators 20-1 to 20-(k-1) respectively.

Taking k = 4 as a representative example, it can be seen from the figure that the DAC 32-4 has four bit inputs dl (most significant) to d4 (least significant), and that of those inputs the first three dl, d2 and d3 are connected to the logic outputs 22-1, 22-2 and 22-3 of the comparators 20-1, 20-2 and 20-3 respectively, while the fourth bit input d4 is connected to the fixed level '1'.

The comparators 20-1 to 20-7 and the DAC's 32-2 to 32-7 are simple, continuously operating types and are not connected to any internal or external clock terminals. The main part of the ADC, referenced 40 in the drawing, thus forms a continuously operating or asynchronous circuit. The asynchronous circuit 40 thus has an analogue input 42, formed by the signal (+) inputs of the comparators 20-1 to 20-7 and connected to the output of the sample-and-hold circuit 12, and digital outputs formed by the respective outputs 22-1 to 22-7 of the comparators 20-1 to 20-7.

For the purpose of describing the operation of the ADC, it will be assumed that an unknown input signal V(t) can be represented on a scale from zero to 1, and that a corresponding 7-bit output word Q is to be generated having a value from zero (0000000 binary) to 127 (1111111 binary). In accordance with this convention, a first reference signal V1 equal to one half on the said scale of zero to one is applied to the ADC reference input 30.

In operation, the analog signal V(t) is applied to the analogue input 10, and a clock waveform defining a desired sampling period T is applied to the first clock terminal 14 of the ADC to begin the conversion of each sample. This causes the sample-and-hold circuit 12 periodically to store the instantaneous value of the input signaL V(t) as an input sample value VS, which is then applied via the input 42 of the asynchronous circuit 40 to the signal (+) inputs of the comparators 20-1 to 20-7. After a certain comparator propagation delay tc the first comparator 20-1 therefore generates a bit value ql at its output 22-1, which value ql is a '1' if the input value VS is greater than 1 and '0' if VS 2 is less than 1.The bit value ql determined by the comparator 20-1 2 is then the most significant bit (MUSE) of the required 7-bit output word Q, and has a value of 1 on the input scale (0 to 1), 2 corresponding to a value of 64 on the output scale (0 to 127).

After a further short delay td2 the first DAC 32-2 generates a second reference signal V2 which can take the value 1 or 3 44 depending on the value of the most significant bit ql. This is the result of fixing input d2 of the DAC 32-2 to the value '1' which is equivalent to the operation of the successive approximation register (SAR) in the known ADC when the next bit to be determined is set provisionally to a '1'. However, in this case the second reference signal V2 is not fed back to the same comparator 20-1 under control of synchronous logic but is fed immediately to the separate, second comparator 20-2 so that the true value of the second most significant bit q2 is available at its output 22-2, after a further comparator delay tc.

The two most significant bits ql and q2 and the fixed value '1' are therefore available at the inputs of the second DAC 32-3 which, after a further delay td3, generates a third reference signal V3 which can take a value which is 1, 3, 5 or 7 on the scale 8 8 8 of zero to one. Signal V3 is in turn used by the third comparator 20-3 to generate the third most significant bit q3 of the output word. This process continues through the following stages, in a ripple-like manner, to find the bit values q4, q5, q6 and q7 so that eventually the comparator outputs 22-1 to 22-7 carry the binary equivalent of the unknown input value VS.

At this point a second clock signal, also of period T is applied to the second clock terminal 15. This triggers the latches 24-1 to 24-7 so that the bit values ql to q7 are noted and transferred to the outputs 26-1 to 26-7 respectively, where they form the bits Q1 to Q7 of the final output word Q and are held until the end of the next sampling period T, by which time a new digital output value ql to q7 will be available for latching. The first and second clock signals may be the same signal if it can be assured that the inputs to the latched 24-1 to 24-7 will be closed before a new sample appears at the input 42 of the asynchronous circuit 40.

It will be appreciated from the above that the correct output word Q will only be obtained if each sampling period T is long enough for the asynchronous circuit 40 to settle to a steady state after each change of the input value VS. With a 12 MHz sampling rate, for example, the clock period T will be 83ns, implying an average of 12ns for each stage of the conversion. It is an advantage of the present invention that the different stages can take different times to settle so long as the total of 83ns is not exceeded. This is important because, aside from random differences that will inevitably occur between the stages, there may also be substantial systematic variations in the propagation delays which in a conventional ADC represent a substantial loss of speed relative to the theoretical maximum.

For example, the digital-to-analogue conversion performed by DAC 32-2 involves only one variable bit and in practice need not take as long as that performed by the last DAC 32-7, which involves 6 variable bits. In a conventional successive approximation ADC, the full 7-bit conversion time must be allowed for at every stage, because of the rigidity imposed by the internal bit-rate clock. In the asynchronous ADC shown in the drawing, however, the shorter delays td2, td3 for the smaller DAC's 32-2 and 32-3 can compensate for the longer delays td6, td7 in the larger DAC's 32-6 and 32-7 and so that a minimum total conversion time T can be obtained.

The R-2R ladder-type DAC can be used to advantage for the DAC's 32-2 to 32-7 in the ADC shown, since it occupies little space and requires only two accurate resistor values. R-2R DAC's suitable for incorporation in a CMOS embodiment can be constructed using simple MOSFET switches to control the ladder network as required. When using R-2R ladder-type DAC's the conversion times td2 to td7 will be successively longer because of the longer resistor ladder networks involved.

It will be appreciated by those skilled in the art that the propagation delays in the various components are reduced further due to the fact that the comparators and DAC's in the ADC according to the invention do not need to include clocking and latching circuits. This means that in any given circuit technology the invention enables the production of a faster ADC than the conventional successive approximation ADC, as well as avoiding the need to generate and distribute a very high frequency clock signal.

A further feature of the ADC shown is that if the clock sampling frequency is increased above the frequency at which the total settling time of the asynchronous circuit 40 is equal to the sampling period T, the ADC will continue to operate, although it will not produce correct values for the least significant bits.

For example, if the ADC shown is capable operating to 7-bit accuracy at a sampling frequency of 12 MHz, it will still operate at 15 MHz, say, even though only the first five bits (Q1 to Q5) might be accurate. This gradual degradation of accuracy with increased frequency contrasts with the known successive approximation ADC's which will not operate at all if supplied with a clock signal much above their maximum operating frequency.

Those skilled in the art will appreciate that the principle of the invention extends beyond the particular embodiments described.

For example, it will be readily apparent how the number of bits in the digital output word Q can be increased or decreased simply by using more or fewer stages than are in the circuit shown in the drawing. It will also be apparent that an ADC in accordance with the invention need not be constructed out of CMOS technology, but could equally well be made using other technologies, for example nMOS, pMOS or bipolar technology. Furthermore, the internal design of circuit blocks whose function is known per se (for example comparators and digital to analogue converters) is not limited to the examples mentioned above and any suitable design can be used, subject to the limit on the total settling time of the asynchronous circuit and subject to the need for compatibility between the different circuits that make up the converter.

From reading the present disclosure, other modifications will be apparent to persons skilled in the art. Such modifications may involve other features which are already known in the design, manufacture and use of analogue to digital converters and component parts thereof and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure of the present application also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

Claims (7)

Claim(s)

1. An analogue to digital converter (ADC) for generating a digital output word representing an analogue input signal, the ADC comprising means for generating the most significant bit of the output word by comparing the analogue input signal with a first reference signal and for generating each next most significant bit in turn by using the more significant bit(s) already determined to generate a respective further reference signal and comparing the analogue input signal with the said further reference signal, characterised in that the ADC comprises, in an asynchronous circuit, a separate comparator for generating each bit of the digital output word and a separate digital to analogue converter (DAC) for generating each further reference signal, each DAC having an input connected to receive each of the said more significant bit(s) from the corresponding comparator.

2. An ADC as claimed in Claim 1 wherein each DAC comprises an R-2R ladder-type DAC.

3. An ADC as claimed in Claim 1 or Claim 2 further comprising sampling means for ensuring that the analogue input signal applied to the asynchronous circuit does not change significantly during the determination of the successive bits of the digital output word.

4. An ADC as claimed in any of Claims 1 to 3 further comprising latching means for storing the bit values generated at the outputs of the comparators in the asynchronous circuit for a given analogue input value so that conversion of a further analogue input value can begin.

5. An ADC as claimed in any preceding claim comprising a complementary metal oxide semiconductor (CMOS) integrated circuit.

6. An ADC substantially as described herein with reference to the accompanying drawing.

7. A signal processing integrated circuit including an ADC as claimed in any preceding claim.