GB2226899A - An electronic circuit and signal processing arrangements using it - Google Patents
An electronic circuit and signal processing arrangements using it Download PDFInfo
- Publication number
- GB2226899A GB2226899A GB8900301A GB8900301A GB2226899A GB 2226899 A GB2226899 A GB 2226899A GB 8900301 A GB8900301 A GB 8900301A GB 8900301 A GB8900301 A GB 8900301A GB 2226899 A GB2226899 A GB 2226899A
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- GB
- United Kingdom
- Prior art keywords
- output
- input
- circuit
- vector
- signal processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
- G06F7/5443—Sum of products
Abstract
An electronic circuit, which can serve as an elementary circuit block 10 for a number of different signal processing arrangements, comprises a multiplier 14 having first and second inputs 18, 20, summing means 16 which functions as an accumulator for a feedback/recursion loop 28, and delay means 30 in the loop. One input of a two input multiplexer 26 is connected to an output of the summing means. An output connection 22, optionally including a signal delay means 24, is connected to the second input 20 of the multiplier. An output 32 is provided from the feedback loop. The circuit block 10 can, on its own, implement vector by vector product calculation and by interconnecting two or more of the blocks matrix by vector product calculations can be implemented. <IMAGE>
Description
DESCRIPmCN AN ELEEERCNIC CIRCUIT AND SIGNAL PROCESSING EEi;r33MENrS USING THE ELEITRCNIC CIRCUIT
The present invention relates to an electronic circuit which can be used as an elementary circuit block from which, depending on application, many efficient architectures can be built by connecting one block to a neighbour or neighbours.
According to the present invention there is provided an electronic circuit comprising multiplying means for forming a product of signals applied respectively to first and second inputs of the multiplying means, summing means for forming the sum of the product formed by the multiplying means and a signal applied to a third input, a feedback connection between an output of the sumning means and the third input, and first signal delay means in the feedback connection.
The electric circuit made in accordance with the present invention will enable vector by vector, matrix by vector or scaler by scaler multiplication to be achieved. Such an electronic circuit will also remit a serial matrix by vector product to be obtained using the minimum of hardware. In operation data representative of one of the vectors is applied to the first input of the multiplying means and the coefficients of the other vector are applied in synchronism (or pairwise) with the data to the second input of the multiplying means. The time delay introduced by the first delay means may correspond to the number of clock pulses between each item of data particularly if delay latches are not distributed by incorporating some of them in the multiplying and/or sining means.
If desired a multiplexer may be provided, the multiplexer having first and second inputs and an output, the first input being connected to the output of the sunning means. The provision of a multiplexer enables a series of electronic circuits to be connected together to form signal processing arrangements.
Optionally a further output can be connected to the second input of the multiplying means. A second delay means may be provided in the signal path of the further output. By having two or more of such electronic circuits with the further output of one circuit connected to the second input of the multiplying means of the next following circuit, and so on, it is possible to obtain a matrix by vector product. In a variant of this circuit arrangement the output of the multiplexer of one circuit is connected to the second input of the multiplexer of the next following circuit, and so on. By a suitable application of the signals a serial matrix by vector product can be obtained.
An output terminal may be connected to an output of the first delay means. In a signal processing arrangement comprising two or nore of such electronic circuits and in which the output terminal of one circuit is connected to the second input of the multiplying means of the next following circuit and the output of the multiplexer of one circuit is connected to the second input of the multiplexer of the next following circuit, it is possible to obtain a matrix by vector product using a smaller flutter of latches compared to the circuit arrangements described in the previous paragraph.
The present invention will now be described, by way of example, with reference to the accompanying drawings, wherein:
Figure 1 is a block schematic diagram of an elementary circuit block,
Figure 2 illustrates in full lines those parts of the elementary circuit block shown in Figure 1 which are used to obtain a vector by vector product,
Figure 3 shows two vector by vector multiplications which are carried-out using the block shown in Figure 2 and by interleaving the data and coefficients of the vectors of the two multiplications, Figure 4 is a block schematic diagram of the elementary circuit arranged to provide a serial matrix by vector product,
Figure 5 is a block schematic diagram of a signal processing arrangement comprising a plurality of interconnected elementary blocks for providing a parallel matrix by vector product,
Figure 6 is a block schematic diagram of a signal processing arrangement comprising a plurality of interconnected elementary blocks for providing a serial matrix by vector product,
Figure 7 is an alternative signal processing arrangement to that shown in Figure 6 for providing a serial matrix by vector product, and
Figure 8 comprises equations (1) to (8) relating to the operation of the signal processing arrangement shown in Figure 7.
In the drawings the same reference numbers have been used to indicate corresponding features.
Referring to Figure 1, the elementary circuit block 10 comprises an arithmetic stage 12 formed by a multiplier 14 and sunning (or accumulating) means 16 having an input connected to an output of the multiplier 14. The block 10 has first and second signal inputs 18, 20, respectively which are connected to respective inputs of the multiplier 14.
An output connection 22 is connected to a branch of the signal path from the second input 20 to the multiplier 14.
Optionally, delay means 24 formed by latches may be provided in the signal path to the output connection 22.
An output of the sunning means 16 is connected to a first input of a multiplexer 26 and is also fed back by means of a feedback connection 28 to a second input of the sunning means 16. Delay means 30 formed by latches is provided in the feedback connection 28. A signal output 32 is connected to the output side of the delay means 30. The multiplexer 26 has a second input 34 and an output 36.
The elementary circuit block 10 can be used alone or in combination with other similar circuit blocks to form signal processing arrangements. Depending on the actual application, will depend on what parts of the block will be used. However the arithmetic stage 12, the feedback connection 28 and the delay means 30 will be common to all implementations, although the time delay introduced by the delay means 30 is selected to suit the problem being solved taking into account that some of the time delay may be introduced by latches (not shown) in the arithmetic stage. Essentially the processor function is spread-out over several clock pulses through the use of delay latches in the multiply and accumulate loop.In order to facilitate an understanding of this present invention, it will be assumed that the delay latches constituting the loop delay are wholly embodied in the delay means 30. Thus by increasing the clock rate, more than one independent problem can be performed concurrently by multiplexing different data streams. The number of latches in effect determines the number of separate problems performed concurrently. Since many natural signal processing algorithms require the repetitive evaluation of the same function with different data, the operation of the elementary circuit block is directly applicable to solving such problems and in so doing reduce the overall memory requirements of some algorithms.
Figures 2 to 7 illustrate various applications of using one or more of the circuit blocks to solve a number of problems.
Figure 2 illustrates what parts of the block 10 are used to provide a vector by vector product. Input vector sequence values (xi) and (uni) applied to the first and second inputs 18, 20, respectively, are separated in time by a number of clock pulses corresponding to the number of latches # constituting the delay means 30. In Figure 2 the values x0 and α0 are the first to arrive at the first and second inputs 18, 20. After multiplication in the multiplier 14 and accumulation in the sunning means 16, the feedback connection 28 being initially zero, the result (α0x0) returns along the feedback connection 28. After \ clock pulses this result arrives at the humming means 16 to be accumulated with the result (α1x1) of the new multiplication. The accumulated result (# OXO + #1x1) is again fed back to the sunning means 16 by way of the feedback connection 28. A further o clock pulses later, the new product (α2x2) from the multiplier 14 is added to give a new result (α0x0 + α1x1+ α2x2). This is the desired result and is channelled by the multiplexer 26 to the output 36.An external control means (not shown) can determine when the elementary circuit 10 should produce an output fran the multiplexer 26 indicating a solution of a problem by, for example, monitoring the data applied to the inputs 18,20 and ascertaining if it includes a "data ready" flag which indicates that the following data is the first data relating to a new problem. Detection of the "data ready" flag is taken by the external control means to mean that the immediately preceding data is the last data of the preceding problem. Consequently when the multiply and accumulate operation has been done on the last data of the preceding problem, the multiplexer 26 is actuated to provide an output.
The order in which the vector values are applied to the first and second inputs 18, 20 can be varied provided the ordering is done pairwise. This enables a great versatility in operation when applied to real signal processing problems and considerably reduces data reordering requirements.
Figure 3 illustrates how the circuit block 10 shown in
Figure 2 can be applied to solving two vector by vector problems concurrently by multiplexing the data values. In this illustration it=2, so that by applying the data values to the first input 18 in the order xOs0x1s1x2s2 and to the second input 20 in the order ohossocZlsslol2ss2 the accumulation for one of the calculations can take place in the gumming means 16 whilst the accumulated result of the other of the calculations is being sequenced through the latches of the delay means 30. The input and output data rate is equivalent to the system clock rate.
After three accumulations for each calculation the multiplexer 26 provides the results [ y0 ] and [ to ] . There is no restriction to how the input values are ordered.
Figure 4 illustrates the use of a single circuit block 10 for producing a matrix by vector product. In general a vector of length N may be multiplied by a matrix of size NxN but the data rate is constrained to be (l/N)th of the processor clock rate.
In Figure 4 the number of latches forming the delay means 30 is
N, where N = 3. By considering the problem as three independent vector by vector products they can be multiplexed as described with reference to Figure 3. The matrix values are fed serially to the second input 20, column first and at the clock rate. Each of the input vector values Xi must however remain at the first input 20 for three clock pulses forcing the input data rate to reduce to a third of the system clock rate. The output values though are changing at the clock rate.
Figure 5 illustrates a signal processing arrangement using three of the elementary circuit blocks 10, 10' and 10" for producing a matrix by vector product at the clock rate. The blocks 10, 10' and 10" are connected together by firstly the output connection 22 being connected to the second input 20' of the block 10' and secondly the output connection 22' being connected to the second input 20" of the block 10". The delay means 24, 24 and 24" are set to zero. The problem is again treated as three vector by vector problems with each block solving a respective one of the problems and providing its result [ Yo ] , [ y1# or [ y2 ] in parallel with the others.In operation the respective rows of the matrix values are applied at the clock rate to the first inputs 18, 18' and 18F' and the vector values are applied at the clock rate to the first input 20 and, by way of the interconnections 22-20' and 22'-20 " , simultaneously to the second inputs 20' and 20".
The signal processing arrangement shown in Figure 5 can be modified as shown in Figure 6 to provide a serial output data stream. The modifications are to connect the output 36 of the multiplexer 26 to the second input 34' of the multiplexer 26' and connect its output 36' to the second input 34" of the multiplexer 26". Also the delay means 24, 24', 24" and 30', 30" introduce a delay A corresponding to a number of clock pulses.
In operation the first row of matrix values and the vector values are applied pairwise to the first and second inputs 18,20 of the block 10. The second row of matrix values is delayed by with respect to the first row and similarly the third row of matrix values is delayed by . with respect to the second row.
However the provision of the delay means 24, 24' ensures that the respective matrix and vector values are applied pairwise to the multipliers 14' and 14". The required vector (or serial) output [ Yo ] [ Y1 ] [ Y2 ] is provided by the output 36" of the multiplexer 26 ".
The use of the delay means 24, 24' and 24" can be avoided as shown in Figure 7 by connecting the output side of the delay means 30, 30', that is the outputs 32, 32' to the second inputs 20' and 20 " , respectively, of the blocks 10' and 10". The second and third rows of matrix values ss0 ", ssl ", ss2 " and '0 ", '1 ", '2 " are staggered in time with respect to the first row of matrix values by, and 2 , respectively.
Staggering the second and third rows of matrix values has the effect that in the second block 10', the signal produced by the multiply and accumulate operation in the block 10, # clock pulses earlier, is multiplied by a value of the second matrix applied to the first input 18'. Similarly in the third block 10", the signal produced by the multiply and accumulate operation in the block 10', #. clock pulses earlier, is multiplied by a value of the third matrix applied to the first input 18".
Additionally the final multiply and accumulate output [ yO ] of the arithmetic stage 12 is supplied to the output 36" by way of the multiplexers 26, 26' and 26 ". # clock pulses later the output is supplied to the output 36" and a further # clock pulses later the output [y2] is supplied to the output 36". The respective outputs are shown in Figure 8 as equations (1), (2) and (4).
Referring to Figure 8, equation (3) is equation (2) rewritten and equation (5) is equation (4) which has been manipulated and rewritten.
The values or coefficients sso ", ss1 ", ss2 " and @o ", @1 ", @2 " can be expressed in terms of the coefficients α0,
α1, α 2, ss0, ss1, ss2 and @0, @1, @2 by assuming the answers, equations (6), (7) and (8) in Figure 8, obtained by performing a matrix by vector operation as described with reference to Figure 6.
Comparing equations (1) and (6), the values of α0, α1 and α2 as multipliers are as shown without any modification.
Comparing equations (3) and (7) and assuming that they must be identical for all possible values for xg, xl and x2, then by equating parts in x0, x1 and x2, one obtains @2ss2 " = ss2, therefore ss2 " = ss2/α2 @1(ss1 " + B2/α2) = ss1, therefore ss1 " = ss1/α1 - ss2/α2 and @0(ss0 " + ssl/@ 1 - ss2/α + ss2/α2) = ss0, therefore ss0 " = ss0/α0 - ss1/α1.
Making similar assumptions in respect of equations 5 and 8, one can obtain values for @2 ", @1 " and @0 ".
The elementary circuit block and the described and illustrated architectures employing two or more of the circuit blocks enable a controlled number of problems to be computed concurrently as well as versatility in the data input and output orderings. The input and output ordering can be different for each concurrent problem. These features allow algorithms to be implemented efficiently with a minimum amount of hardware and at very high throughputs.
From reading the present disclosure, other modifications will be apparent to persons skilled in the art.
Such modifications may involve other features which are already known in the design, manufacture and use of elementary circuit blocks and component parts thereof and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure of the present application also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to such features and /or combinations of such features during the prosecution of the present application or of any further application derived therefrom.
Claims (9)
1. An electronic circuit comprising multiplying means for forming a product of signals applied respectively to first and second inputs of the multiplying means, mmming means for forming the sum of the product formed by the multiplying means and a signal applied to a third input, a feedback connection between an output of the sumning means and the third input and first signal delay means in the feedback connection.
2. A circuit as claimed in Claim 1, wherein the number of delays in a loop comprising at least the summing means and the delay means in the feedback connections equals the number of problems to be solved.
3. A circuit as claimed in Claim 1 or 2, further comprising a multiplexer having an input connected to the output of the surrrning means, a second input and an output.
4. A circuit as claimed in Claim 1, 2 or 3, further comprising a further signal output connected to the second input.
5. A circuit as claimed in Claim 4, further comprising second delay means in the signal path to the further output.
6. A circuit as claimed in any one of Claims 1 to 5, further comprising an output terminal connected to an output of the first delay means.
7. An electronic circuit constructed and arranged to operate substantially as hereinbefore described with reference to and as shown in the accompanying drawings.
8. A signal processing arrangement comprising n circuits as claimed in Claim 4, where n is 2 or more, wherein the further output of a first to the (n-l)th circuits is connected to a second input of the multiplying means in a second to the nth circuits, respectively.
9. A signal processing arrangement carrprising n circuits as claimed in Claim 5 when appended to Claim 3, where n is 2 or more, wherein the further output of a first to the (n-l)th circuits is connected to the second input of the multiplying means of the second to the nth circuits, respectively, the output
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8900301A GB2226899A (en) | 1989-01-06 | 1989-01-06 | An electronic circuit and signal processing arrangements using it |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8900301A GB2226899A (en) | 1989-01-06 | 1989-01-06 | An electronic circuit and signal processing arrangements using it |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8900301D0 GB8900301D0 (en) | 1989-03-08 |
| GB2226899A true GB2226899A (en) | 1990-07-11 |
Family
ID=10649711
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8900301A Withdrawn GB2226899A (en) | 1989-01-06 | 1989-01-06 | An electronic circuit and signal processing arrangements using it |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2226899A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0472387A2 (en) * | 1990-08-21 | 1992-02-26 | Fujitsu Limited | Small-sized matrix operation apparatus |
| WO1994013066A1 (en) * | 1992-11-24 | 1994-06-09 | Qualcomm Incorporated | Dot product circuit for multipath receivers |
| US5422836A (en) * | 1990-11-15 | 1995-06-06 | Siemens Aktiengesellschaft | Circuit arrangement for calculating matrix operations in signal processing |
| GB2286909A (en) * | 1994-02-24 | 1995-08-30 | Wu Chen Mie | Pipelined SIMD-systolic array processor. |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3805043A (en) * | 1972-10-11 | 1974-04-16 | Bell Telephone Labor Inc | Serial-parallel binary multiplication using pairwise addition |
| GB1523750A (en) * | 1974-12-20 | 1978-09-06 | Western Electric Co | Apparatus for forming the product of two binary data word |
| GB2166272A (en) * | 1984-10-27 | 1986-04-30 | Stc Plc | Serial multiplier circuit |
| EP0206763A2 (en) * | 1985-06-19 | 1986-12-30 | Advanced Micro Devices, Inc. | Digital electronic multiplier circuits |
| EP0260515A2 (en) * | 1986-09-17 | 1988-03-23 | INTERSIL, INC. (a Delaware corp.) | Digital multiplier architecture with triple array summation of partial products |
-
1989
- 1989-01-06 GB GB8900301A patent/GB2226899A/en not_active Withdrawn
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3805043A (en) * | 1972-10-11 | 1974-04-16 | Bell Telephone Labor Inc | Serial-parallel binary multiplication using pairwise addition |
| GB1523750A (en) * | 1974-12-20 | 1978-09-06 | Western Electric Co | Apparatus for forming the product of two binary data word |
| GB2166272A (en) * | 1984-10-27 | 1986-04-30 | Stc Plc | Serial multiplier circuit |
| EP0206763A2 (en) * | 1985-06-19 | 1986-12-30 | Advanced Micro Devices, Inc. | Digital electronic multiplier circuits |
| EP0260515A2 (en) * | 1986-09-17 | 1988-03-23 | INTERSIL, INC. (a Delaware corp.) | Digital multiplier architecture with triple array summation of partial products |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0472387A2 (en) * | 1990-08-21 | 1992-02-26 | Fujitsu Limited | Small-sized matrix operation apparatus |
| EP0472387A3 (en) * | 1990-08-21 | 1993-05-19 | Fujitsu Limited | Small-sized matrix operation apparatus |
| US5313274A (en) * | 1990-08-21 | 1994-05-17 | Fujitsu Limited | Color signal matrix circuit |
| US5422836A (en) * | 1990-11-15 | 1995-06-06 | Siemens Aktiengesellschaft | Circuit arrangement for calculating matrix operations in signal processing |
| WO1994013066A1 (en) * | 1992-11-24 | 1994-06-09 | Qualcomm Incorporated | Dot product circuit for multipath receivers |
| US5506865A (en) * | 1992-11-24 | 1996-04-09 | Qualcomm Incorporated | Pilot carrier dot product circuit |
| AU676249B2 (en) * | 1992-11-24 | 1997-03-06 | Qualcomm Incorporated | Pilot carrier dot product circuit |
| CN1078026C (en) * | 1992-11-24 | 2002-01-16 | 夸尔柯姆股份有限公司 | Pilot carrier dot product circuit |
| GB2286909A (en) * | 1994-02-24 | 1995-08-30 | Wu Chen Mie | Pipelined SIMD-systolic array processor. |
| DE19504089A1 (en) * | 1994-02-24 | 1996-08-14 | Wu Chen Mie | Pipelined SIMD-systolic array processor in computer, video image processing, DSP |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8900301D0 (en) | 1989-03-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |