GB2224160A - Integrated semiconductor circuits - Google Patents

Abstract

The circuit for use as a frequency mixer comprises semiconductor devices such as F.E.T.'s formed in a substrate in which treated areas of the substrate act simultaneously as a region for at least two semiconductor devices. The construction enables the size of the circuit and the conductor tracks to be reduced. <IMAGE>

Description

Semiconductor Arrangement This invention relates to semi-conductor arrangements and in particular to monolithic semi-conductor arrangements. In a specific embodiment it relates to a mixer cell incorporated within a monolithic semi-conductor arrangement.

Mixer cells are well known and perform the function of mixing a plurality of frequency signals. Typically a first signal (F1), which may be derived from an oscillator, is applied to a first input terminal. A second signal (F2), is applied to a second input terminal and mixed with the first signal. The output from the cell is in the form of a sum and/or a difference of the two frequencies i.e. F1 + F2 and F1 - F2.

One type of mixer cell to which the invention is particularly relevant is the Gilbert mixer cell. This consists of a number of interlinked Field Effect Transistors (FETs), typically six, connected together.

These are interlinked in such a manner as to permit frequency variations of input signals to a first pair of FETs, to alter the current-voltage characteristics of two further pairs of FETs. Previously the layout of these FETs as a semiconductor circuit arrangement, despite being on a very small scale, has led to a considerable amount of inter-connecting material being required. This has in turn resulted in a relatively complex configuration of the inter- connecting tracks on a semi-conductor substrate. Moreover- as a resulted of these -intricate and complicated track patterns and: because it is important to strive to save space, considerable amounts of - straycapacitance and inductance arise due to the necessary proximity of the tracks.

The present invention arose in an effort to reduce the amount of stray capacitance and inductance between such tracks and to maintain at least the present packing density of components and interconnections whilst not sacrificing any yield losses in mass production 'runs.

According to the present invention there is provided a semi-conductor arrangement comprising a monolithic substrate carrying a plurality of treated areas adapted to act as respective regions of nominal semi-conductor devices, wherein at least one of the treated areas acts simultaneously as a region for at least two semi-conductor devices An embodiment of the present invention will now be described by way of example only, with reference to the accompanying drawings, in which: Figure 1 is a circuit diagram of a Gilbert mixer cell showing input and output terminals.

Figure 2 shows a conventional monolithic arrangement of a Gilbert cell, and Figure 3 shows an arrangement, embodying the invention, of a Gilbert cell.

Although the present invention is not directly related to the functioning of any particular circuit, a brief description of one circuit, in this case a Gilbert Mixer circuit, is useful in gaining an understanding of the invention and the benefits that it can achieve.

Referring to Figure 1, there is shown schematically a typical Mixer cell.

A first signal is input at la and lb, on the gates of FET1 and FET2 respectively. A second signal, typically from a local oscillator LO, is input at 2a and 2b and serves to drive the other gates of the remaining four FETs, (FETs 3 to FET 6 inclusive). The input signal at 1 causes balanced offset currents to flow through a first pair of FETs, FET1 and FET2. These'currents in turn are used to drive the two respective pairs of FETs, namely a second pair comprising FET3 and FET4, and a third pair comprising FET5 and FET6. The signals are therefore mixed in the second and third pairs of FETs respectively and are output at the drains of FET3 and FET4 from the second pair of FETs and at the drains on FET5 and FET6 from the third pair of FETs. This mixing occurs with the frequency provided by the local oscillator.Switching of the balance current obtained from the driver signals of FET1 and FET2 gives rise to two currents at different frequencies, which are then separately output on the drains of the second and third pairs of FETs. The output frequencies are respectively F1 + F2, obtained from FET3 and FET4 and F1-F2 obtained from FET5 and FET6. These two signals are output at 3a and 3b.

Figure 2 illustrates an example - of- a physical representation of-the circuit shown:in figure 1. The FETs: are numbered FET1 - FET6, also-shown- are the interconnecting tracks 7a-7j, a curr-ent source 8, and the respective input and output conductors 1, 2 and 3 and some of the supporting posts (9) for said tracks 7.

It should be appreciated that the number of interconnecting tracks together with their lengths and cross-sectional areas may be varied, according to resistive requirements sof the mixer cell. Typically because operating frequencies may vary, modifications in such interconnections may be necessary. An alternative way in which this effect may be achieved, is by duplicating interconnecting tracks between the same regions or to provide duplicate tracks of different dimensions.

Typically an area of 81.2 x 10 3 my 2 of or substrate are required in a conventional layout of such a cell. It is apparent from figure 2 that the regions FET1 drain, FET3 source and FET5 source are all held at the same potential, due to the interconnecting track 7c. Similarly this is the case for FET2, FET4 and FET6 and their corresponding drains and sources, by way of interconnecting track 7i. Furthermore regions between FET1 and FET2 are common by way of interconnectors 7f, 7j and connector 8. An embodiment of the present invention, shown in figure 3 minimizes the number of tracks and connectors within the device. The improved circuit of figure 3, is shown with corresponding regions and their operations indicated similarly to those in figure 2.

Figure 3 shows a preferred embodiment of the invention in a monolithic layout in which the drains of FET3 and FET5 are common, as are the drains of FET4 and FET6 and the drains of FET1 and FET2. These three common pairs are simultaneously joined to the sources of FET3 and FET4 and FET5 and FET6, as shown in the layout.

With reference to the improved layout in figure 3 the area of substrate is approximately 36.8 x 10 m 2 and and substantially less support posts are used. There is thus not only a substantial saving in the number of support posts, simply due to the improved layout, but also a considerable saving on area. Clearly this leads to a cheaper device and one which is easier to manufacture.

However, more importantly, due to the fact that common essential elements have been incorporated into one region of the substrate, a substantial saving has been made on the size of the device and on the conductor tracks.

Accordingly a considerable reduction in stray capacitance has resulted. This leads to an improved circuit with no loss in production yield.

Although this technique is shown to be used in a mixer cell it may be readily adapted for use within any semi-conductor arrangement which employs a number of transistor type elements, such as field effect transistors MOS-FETs, JUG-FETs, CMOS and NMOS devices and in which at least some interconnections are designed to be at a common.

potential. a common.The exact configuration would -of course depend- upon the requirements imposed upon-the-circuit and such a technique is clearly adaptable for a wide variety of uses.

Claims (10)

1. A semi-conductor arrangement comprising a monolithic substrate carrying a plurality of treated areas adapted to act as respective regions of semi-conductor devices, wherein at least one of the treated areas acts simultaneously as a region for at least two semi-conductor devices.

2. A semi-conductor arrangement as claimed in claim 1 configured as a mixer cell.

3. A semi-conductor arrangement as claimed in claim 1 or claim 2 wherein the areas are electrically connected, so as to produce the desired electrical circuit.

4. A semi conductor arrangement as claimed in any of the previous claims wherein at least some of the connecting tracks are duplicated to produce a chosen impedance value.

5. A semi-conductor arrangement as claimed in claim 6 wherein portions of separate areas are connected so as to form common regions of a plurality of separate Field Effect Transistors.

6. A semi-conductor arrangement as claimed in any of the preceding claims wherein an area comprises the drain of a first FET and the source of a 2nd FET simultaneously.

7. A semi-conductor arrangement as claimed in any preceding claim wherein the said regions are substantially parallel to one another.

8. A semi-conductor arrangement as claimed in anyone of the preceding claims wherein the semi-conductor substrate is of Gallium Arsenide.

9 A semi-conductor:arrangement as claimed in claim 8 wherein a further conductor is interposed between two parallel areas of treated substrate.

10. A Gilbert mixer cell as shown in Figure 3 and substantially as hereinbefore described.